/
translate-a64.c
3909 lines (3524 loc) · 111 KB
/
translate-a64.c
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/*
* ARM translation
*
* Copyright (c) 2003 Fabrice Bellard
* Copyright (c) 2005-2007 CodeSourcery
* Copyright (c) 2007 OpenedHand, Ltd.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include "cpu.h"
#include "disas/disas.h"
#include "tcg-op.h"
#include "qemu/log.h"
#include "translate.h"
#include "qemu/host-utils.h"
#include "helper.h"
#define GEN_HELPER 1
#include "helper.h"
// #define DEBUG_SINGLESTEP 1
// #define DEBUG_FLUSH 1
static TCGv_i64 cpu_X[32];
static TCGv_i64 cpu_pc;
static TCGv_i64 cpu_sp;
static TCGv_i32 pstate;
static TCGv_i64 cpu_exclusive_addr;
static TCGv_i64 cpu_exclusive_val;
static TCGv_i64 cpu_exclusive_high;
#ifdef CONFIG_USER_ONLY
static TCGv_i64 cpu_exclusive_test;
static TCGv_i64 cpu_exclusive_info;
#endif
static const char *regnames[] =
{ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27", "x28", "x29", "lr", "xzr" };
/* initialize TCG globals. */
void a64_translate_init(void)
{
int i;
cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, pc),
"pc");
cpu_sp = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, sp),
"sp");
for (i = 0; i < 32; i++) {
cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, xregs[i]),
regnames[i]);
}
pstate = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUARMState, pstate),
"pstate");
cpu_exclusive_addr = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
cpu_exclusive_val = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_val), "exclusive_val");
cpu_exclusive_high = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_high), "exclusive_high");
#ifdef CONFIG_USER_ONLY
cpu_exclusive_test = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_test), "exclusive_test");
cpu_exclusive_info = tcg_global_mem_new_i64(TCG_AREG0,
offsetof(CPUARMState, exclusive_info), "exclusive_info");
#endif
}
void cpu_dump_state_a64(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
int i;
cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", env->pc, env->sp);
for(i = 0; i < 31; i++) {
cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
if ((i % 4) == 3)
cpu_fprintf(f, "\n");
else
cpu_fprintf(f, " ");
}
cpu_fprintf(f, "XZR=%016"PRIx64"\n", env->xregs[31]);
cpu_fprintf(f, "PSTATE=%c%c%c%c\n",
env->pstate & PSTATE_N ? 'n' : '.',
env->pstate & PSTATE_Z ? 'z' : '.',
env->pstate & PSTATE_C ? 'c' : '.',
env->pstate & PSTATE_V ? 'v' : '.');
cpu_fprintf(f, "\n");
if (1) { //flags & CPU_DUMP_FPU) {
int numvfpregs = 32;
for (i = 0; i < numvfpregs; i++) {
uint64_t v = float64_val(env->vfp.regs[i * 2]);
uint64_t v1 = float64_val(env->vfp.regs[(i * 2) + 1]);
if (!v && !v1) continue;
cpu_fprintf(f, "d%02d.0=%016" PRIx64 " " "d%02d.0=%016" PRIx64 "\n",
i, v, i, v1);
}
cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]);
}
}
static int get_bits(uint32_t inst, int start, int len)
{
return (inst >> start) & ((1 << len) - 1);
}
static int get_sbits(uint32_t inst, int start, int len)
{
int r = get_bits(inst, start, len);
if (r & (1 << (len - 1))) {
/* Extend the MSB 1 to the higher bits */
r |= -1 & ~((1ULL << len) - 1);
}
return r;
}
static int get_reg(uint32_t inst)
{
return get_bits(inst, 0, 5);
}
static TCGv_i64 cpu_reg(int reg)
{
if (reg == 31) {
/* XXX leaks temps */
return tcg_const_i64(0);
} else {
return cpu_X[reg];
}
}
static TCGv_i64 cpu_reg_sp(int reg)
{
if (reg == 31) {
return cpu_sp;
} else {
return cpu_X[reg];
}
}
static TCGv_ptr get_fpstatus_ptr(void)
{
TCGv_ptr statusptr = tcg_temp_new_ptr();
int offset;
offset = offsetof(CPUARMState, vfp.standard_fp_status);
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
return statusptr;
}
static void clear_fpreg(int dest)
{
int freg_offs = offsetof(CPUARMState, vfp.regs[dest * 2]);
TCGv_i64 tcg_zero = tcg_const_i64(0);
tcg_gen_st_i64(tcg_zero, cpu_env, freg_offs);
tcg_gen_st_i64(tcg_zero, cpu_env, freg_offs + sizeof(float64));
}
static int get_mem_index(DisasContext *s)
{
/* XXX only user mode for now */
return 1;
}
void gen_a64_set_pc_im(uint64_t val)
{
tcg_gen_movi_i64(cpu_pc, val);
}
static void gen_exception(int excp)
{
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_movi_i32(tmp, excp);
gen_helper_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
}
static void gen_exception_insn(DisasContext *s, int offset, int excp)
{
gen_a64_set_pc_im(s->pc - offset);
gen_exception(excp);
s->is_jmp = DISAS_JUMP;
}
static void _unallocated_encoding(DisasContext *s)
{
fprintf(stderr, "Unknown instruction: %#x\n",
arm_ldl_code(current_cpu->env_ptr, s->pc - 4, s->bswap_code));
gen_exception_insn(s, 4, EXCP_UDEF);
}
#define unallocated_encoding(s) do { \
fprintf(stderr, "unallocated encoding at line: %d\n", __LINE__); \
_unallocated_encoding(s); \
} while(0)
static void reserved(DisasContext *s, uint32_t insn, int start, int len,
uint32_t val)
{
uint32_t field = get_bits(insn, start, len);
if (field != val) {
fprintf(stderr, "Broken ins: %08x %08x %08x", insn, field, val);
unallocated_encoding(s);
}
}
static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
{
TranslationBlock *tb;
tb = s->tb;
if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
tcg_gen_goto_tb(n);
gen_a64_set_pc_im(dest);
tcg_gen_exit_tb((tcg_target_long)tb + n);
} else {
gen_a64_set_pc_im(dest);
tcg_gen_exit_tb(0);
}
}
static void handle_b(DisasContext *s, uint32_t insn)
{
uint64_t addr = s->pc - 4 + (get_sbits(insn, 0, 26) << 2);
if (get_bits(insn, 31, 1)) {
/* BL */
tcg_gen_movi_i64(cpu_reg(30), s->pc);
}
gen_goto_tb(s, 0, addr);
s->is_jmp = DISAS_TB_JUMP;
}
static void handle_br(DisasContext *s, uint32_t insn)
{
int branch_type = get_bits(insn, 21, 2);
int source = get_bits(insn, 5, 5);
switch (branch_type) {
case 0: /* JMP */
break;
case 1: /* CALL */
tcg_gen_movi_i64(cpu_reg(30), s->pc);
break;
case 2: /* RET */
source = 30;
break;
case 3:
unallocated_encoding(s);
return;
}
tcg_gen_mov_i64(cpu_pc, cpu_reg(source));
s->is_jmp = DISAS_JUMP;
}
static void handle_condb(DisasContext *s, uint32_t insn)
{
uint64_t addr = s->pc - 4 + (get_sbits(insn, 5, 19) << 2);
int cond = get_bits(insn, 0, 4);
int no_match;
TCGv_i32 tcg_zero = tcg_const_i32(0);
TCGv_i32 tcg_cond = tcg_const_i32(cond);
TCGv_i32 tcg_condmatch = tcg_temp_new_i32();
no_match = gen_new_label();
gen_helper_cond(tcg_condmatch, pstate, tcg_cond);
tcg_gen_brcond_i32(TCG_COND_EQ, tcg_condmatch, tcg_zero, no_match);
gen_goto_tb(s, 0, addr);
gen_set_label(no_match);
gen_goto_tb(s, 1, s->pc);
tcg_temp_free_i32(tcg_zero);
tcg_temp_free_i32(tcg_cond);
tcg_temp_free_i32(tcg_condmatch);
s->is_jmp = DISAS_TB_JUMP;
}
static void handle_cb(DisasContext *s, uint32_t insn)
{
uint64_t addr = s->pc - 4 + (get_sbits(insn, 5, 19) << 2);
bool is_zero = !get_bits(insn, 24, 1);
bool is_32bit = !get_bits(insn, 31, 1);
int dest = get_reg(insn);
int no_match;
TCGv_i64 tcg_cmp, tcg_zero;
tcg_cmp = tcg_temp_new_i64();
tcg_zero = tcg_const_i64(0);
if (is_32bit) {
tcg_gen_ext32u_i64(tcg_cmp, cpu_reg(dest));
} else {
tcg_gen_mov_i64(tcg_cmp, cpu_reg(dest));
}
no_match = gen_new_label();
if (is_zero) {
tcg_gen_brcond_i64(TCG_COND_NE, tcg_cmp, tcg_zero, no_match);
} else {
tcg_gen_brcond_i64(TCG_COND_EQ, tcg_cmp, tcg_zero, no_match);
}
gen_goto_tb(s, 0, addr);
gen_set_label(no_match);
gen_goto_tb(s, 1, s->pc);
s->is_jmp = DISAS_TB_JUMP;
tcg_temp_free_i64(tcg_cmp);
tcg_temp_free_i64(tcg_zero);
}
static void handle_tbz(DisasContext *s, uint32_t insn)
{
uint64_t addr = s->pc - 4 + (get_sbits(insn, 5, 14) << 2);
bool is_one = get_bits(insn, 24, 1);
int shift = get_bits(insn, 19, 5) | (get_bits(insn, 31, 1) << 5);
int source = get_reg(insn);
int no_match;
uint64_t mask = 1ULL << shift;
TCGv_i64 tcg_cmp, tcg_mask;
tcg_cmp = tcg_temp_new_i64();
tcg_mask = tcg_const_i64(mask);
tcg_gen_and_i64(tcg_cmp, cpu_reg(source), tcg_mask);
no_match = gen_new_label();
if (is_one) {
tcg_gen_brcond_i64(TCG_COND_NE, tcg_cmp, tcg_mask, no_match);
} else {
tcg_gen_brcond_i64(TCG_COND_EQ, tcg_cmp, tcg_mask, no_match);
}
gen_goto_tb(s, 0, addr);
tcg_gen_exit_tb(0);
gen_set_label(no_match);
gen_goto_tb(s, 1, s->pc);
tcg_temp_free_i64(tcg_cmp);
tcg_temp_free_i64(tcg_mask);
s->is_jmp = DISAS_TB_JUMP;
}
static void handle_msr(DisasContext *s, uint32_t insn)
{
int dest = get_reg(insn);
int op0 = get_bits(insn, 19, 2);
int op1 = get_bits(insn, 16, 3);
int crm = get_bits(insn, 8, 4);
int crn = get_bits(insn, 12, 4);
int op2 = get_bits(insn, 5, 3);
/* XXX what are these? */
if (op0 == 3 && op1 == 3 && op2 == 2 && !crm && crn == 13) {
tcg_gen_st_i64(cpu_reg(dest), cpu_env, offsetof(CPUARMState, sr.tpidr_el0));
} else if (op0 == 3 && op1 == 3 && (op2 == 0 || op2 == 1) && crm == 4 && crn == 4) {
/* XXX this is wrong! */
tcg_gen_st32_i64(cpu_reg(dest), cpu_env,
offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
} else {
fprintf(stderr, "MSR: %d %d %d %d %d\n", op0, op1, op2, crm, crn);
unallocated_encoding(s);
}
}
static void handle_mrs(DisasContext *s, uint32_t insn)
{
int dest = get_reg(insn);
int op0 = get_bits(insn, 19, 2);
int op1 = get_bits(insn, 16, 3);
int crm = get_bits(insn, 8, 4);
int crn = get_bits(insn, 12, 4);
int op2 = get_bits(insn, 5, 3);
/* XXX what are these? */
if (op0 == 3 && op1 == 3 && op2 == 2 && !crm && crn == 13) {
tcg_gen_ld_i64(cpu_reg(dest), cpu_env, offsetof(CPUARMState, sr.tpidr_el0));
} else if (op0 == 3 && op1 == 3 && (op2 == 0 || op2 == 1) && crm == 4 && crn == 4) {
/* XXX this is wrong! */
tcg_gen_ld32u_i64(cpu_reg(dest), cpu_env,
offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
} else if (op0 == 3 && op1 == 3 && op2 == 1 && crm == 0 && crn == 0) {
/* ctr_el0 */
/* CTR_EL0 [3:0] contains log2 of icache line size in words.
CTR_EL0 [19:16] contains log2 of dcache line size in words. */
tcg_gen_movi_i64(cpu_reg(dest), 0x30003);
} else if (op0 == 3 && op1 == 3 && op2 == 7 && crm == 0 && crn == 0) {
/* dczid_el0 */
/* [3:0] contain log2(blocksize cleared by "dc zva" instruction)
[4] is tested by glibc, and if set dc zva isn't used. */
tcg_gen_movi_i64(cpu_reg(dest), 0x10);
} else {
fprintf(stderr, "MRS: %d %d %d %d %d\n", op0, op1, op2, crm, crn);
unallocated_encoding(s);
}
}
static void handle_sys(DisasContext *s, uint32_t insn)
{
int rt = get_reg(insn);
int op2 = get_bits(insn, 5, 3);
int crn = get_bits(insn, 12, 4);
int op1 = get_bits(insn, 16, 3);
int op0 = get_bits(insn, 19, 2);
bool is_l = get_bits(insn, 21, 1);
/* XXX simply ignore sys for now, need to start worrying when we implement
system emulation */
/* XXX Some sys insns can also be done in userspace, e.g. 'dc zva',
which clears memory (part of the data-cache sys ops). */
if ((insn & ~0xf) == 0xd50b7420) {
unallocated_encoding(s);
return;
}
if (op1 == 3 && crn == 3 && !is_l && op0 == 0 && op2 == 2 && rt == 31) {
/* CLREX */
tcg_gen_movi_i64(cpu_exclusive_addr, -1);
}
}
/* PC relative address calculation */
static void handle_adr(DisasContext *s, uint32_t insn)
{
int reg = get_reg(insn);
int is_page = get_bits(insn, 31, 1);
uint64_t imm;
uint64_t base;
imm = get_sbits(insn, 5, 19) << 2;
imm |= get_bits(insn, 29, 2);
base = s->pc - 4;
if (is_page) {
/* ADRP (page based) */
base &= ~0xFFFULL;
imm <<= 12;
}
tcg_gen_movi_i64(cpu_reg(reg), base + imm);
}
static void handle_movi(DisasContext *s, uint32_t insn)
{
int reg = get_reg(insn);
uint64_t imm = get_bits(insn, 5, 16);
int is_32bit = !get_bits(insn, 31, 1);
int is_k = get_bits(insn, 29, 1);
int is_n = !get_bits(insn, 30, 1);
int pos = get_bits(insn, 21, 2) << 4;
TCGv_i64 tcg_imm;
reserved(s, insn, 23, 1, 1);
if (is_k && is_n) {
unallocated_encoding(s);
}
if (is_k) {
tcg_imm = tcg_const_i64(imm);
tcg_gen_deposit_i64(cpu_reg(reg), cpu_reg(reg), tcg_imm, pos, 16);
tcg_temp_free_i64(tcg_imm);
} else {
tcg_gen_movi_i64(cpu_reg(reg), imm << pos);
}
if (is_n) {
tcg_gen_not_i64(cpu_reg(reg), cpu_reg(reg));
}
if (is_32bit) {
tcg_gen_ext32u_i64(cpu_reg(reg), cpu_reg(reg));
}
}
static uint64_t replicate(uint64_t mask, int esize)
{
int i;
uint64_t out_mask = 0;
for (i = 0; (i * esize) < 64; i++) {
out_mask = out_mask | (mask << (i * esize));
}
return out_mask;
}
static uint64_t bitmask(int len)
{
if (len == 64) {
return -1;
}
return (1ULL << len) - 1;
}
#define MASK_TMASK 0
#define MASK_WMASK 1
static uint64_t decode_mask(int immn, int imms, int immr, int type)
{
uint64_t mask;
int len = 31 - clz32((immn << 6) | (~imms & 0x3f));
int esize = 1 << len;
int levels = (esize - 1) & 0x3f;
int s = imms & levels;
int r = immr & levels;
int d = (s - r) & 0x3f;
if (type == MASK_WMASK) {
mask = bitmask(s + 1);
mask = ((mask >> r) | (mask << (esize - r)));
mask &= bitmask(esize);
mask = replicate(mask, esize);
} else {
mask = bitmask(d + 1);
}
return mask;
}
#if 0
static uint64_t decode_tmask(int immn, int imms, int immr)
{
return decode_mask(immn, imms, immr, MASK_TMASK);
}
#endif
static uint64_t decode_wmask(int immn, int imms, int immr)
{
return decode_mask(immn, imms, immr, MASK_WMASK);
}
static void handle_orri(DisasContext *s, uint32_t insn)
{
int is_32bit = !get_bits(insn, 31, 1);
int is_n = get_bits(insn, 22, 1);
int opc = get_bits(insn, 29, 2);
int dest = get_reg(insn);
int source = get_bits(insn, 5, 5);
int imms = get_bits(insn, 10, 6);
int immr = get_bits(insn, 16, 6);
TCGv_i64 tcg_dst;
TCGv_i64 tcg_op2;
bool setflags = false;
uint64_t wmask;
if (is_32bit && is_n) {
/* reserved */
unallocated_encoding(s);
}
if (opc == 0x3) {
setflags = true;
}
if (setflags) {
tcg_dst = cpu_reg(dest);
} else {
tcg_dst = cpu_reg_sp(dest);
}
wmask = decode_wmask(is_n, imms, immr);
if (is_32bit) {
wmask = (uint32_t)wmask;
}
tcg_op2 = tcg_const_i64(wmask);
switch (opc) {
case 0x3:
case 0x0:
tcg_gen_and_i64(tcg_dst, cpu_reg(source), tcg_op2);
break;
case 0x1:
tcg_gen_or_i64(tcg_dst, cpu_reg(source), tcg_op2);
break;
case 0x2:
tcg_gen_xor_i64(tcg_dst, cpu_reg(source), tcg_op2);
break;
}
if (is_32bit) {
tcg_gen_ext32u_i64(tcg_dst, tcg_dst);
}
if (setflags) {
gen_helper_pstate_add(pstate, pstate, tcg_dst, cpu_reg(31), tcg_dst);
}
tcg_temp_free_i64(tcg_op2);
}
static TCGv_i64 get_shift(int reg, int shift_type, TCGv_i64 tcg_shift,
int is_32bit)
{
TCGv_i64 r;
r = tcg_temp_new_i64();
/* XXX carry_out */
/* Careful with the width. We work on 64bit, but must make sure
that we zero-extend the result on out, and ignore any upper bits,
that might still be set in that register. */
switch (shift_type) {
case 0: /* LSL */
/* left shift is easy, simply zero-extend on out */
tcg_gen_shl_i64(r, cpu_reg(reg), tcg_shift);
if (is_32bit)
tcg_gen_ext32u_i64 (r, r);
break;
case 1: /* LSR */
/* For logical right shift we zero extend first, to zero
the upper bits. We don't need to extend on out. */
if (is_32bit) {
tcg_gen_ext32u_i64 (r, cpu_reg(reg));
tcg_gen_shr_i64 (r, r, tcg_shift);
} else
tcg_gen_shr_i64(r, cpu_reg(reg), tcg_shift);
break;
case 2: /* ASR */
/* For arithmetic right shift we sign extend first, then shift,
and then need to clear the upper bits again. */
if (is_32bit) {
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
tcg_gen_ext32s_i64(tcg_tmp, cpu_reg(reg));
tcg_gen_sar_i64(r, tcg_tmp, tcg_shift);
tcg_gen_ext32u_i64 (r, r);
tcg_temp_free_i64(tcg_tmp);
} else {
tcg_gen_sar_i64(r, cpu_reg(reg), tcg_shift);
}
break;
case 3: /* ROR */
/* For rotation extending doesn't help, we really have to use
a 32bit rotate. */
if (is_32bit) {
TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_trunc_i64_i32(tmp, cpu_reg(reg));
tcg_gen_rotr_i32(tmp, tmp, tcg_shift);
tcg_gen_extu_i32_i64(r, tmp);
tcg_temp_free_i32(tmp);
} else
tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
break;
}
return r;
}
static TCGv_i64 get_shifti(int reg, int shift_type, int shift, int is_32bit)
{
TCGv_i64 tcg_shift;
TCGv_i64 r;
if (!shift) {
r = tcg_temp_new_i64();
if (is_32bit)
tcg_gen_ext32u_i64 (r, cpu_reg(reg));
else
tcg_gen_mov_i64(r, cpu_reg(reg));
return r;
}
tcg_shift = tcg_const_i64(shift);
r = get_shift(reg, shift_type, tcg_shift, is_32bit);
tcg_temp_free_i64(tcg_shift);
return r;
}
static void handle_orr(DisasContext *s, uint32_t insn)
{
int is_32bit = !get_bits(insn, 31, 1);
int dest = get_reg(insn);
int source = get_bits(insn, 5, 5);
int rm = get_bits(insn, 16, 5);
int shift_amount = get_sbits(insn, 10, 6);
int is_n = get_bits(insn, 21, 1);
int shift_type = get_bits(insn, 22, 2);
int opc = get_bits(insn, 29, 2);
bool setflags = (opc == 0x3);
TCGv_i64 tcg_op2;
TCGv_i64 tcg_dest;
if (is_32bit && (shift_amount < 0)) {
/* reserved value */
unallocated_encoding(s);
}
/* MOV is dest = xzr & (source & ~0) */
if (!shift_amount && source == 0x1f) {
if (is_32bit) {
tcg_gen_ext32u_i64(cpu_reg_sp(dest), cpu_reg(rm));
} else {
tcg_gen_mov_i64(cpu_reg_sp(dest), cpu_reg(rm));
}
if (is_n) {
tcg_gen_not_i64(cpu_reg_sp(dest), cpu_reg_sp(dest));
}
if (is_32bit) {
tcg_gen_ext32u_i64(cpu_reg_sp(dest), cpu_reg_sp(dest));
}
return;
}
tcg_op2 = get_shifti(rm, shift_type, shift_amount & (is_32bit ? 31 : 63),
is_32bit);
if (is_n) {
tcg_gen_not_i64(tcg_op2, tcg_op2);
}
tcg_dest = cpu_reg(dest);
switch (opc) {
case 0x3:
setflags = true;
/* fall through */
case 0x0:
tcg_gen_and_i64(tcg_dest, cpu_reg(source), tcg_op2);
break;
case 0x1:
tcg_gen_or_i64(tcg_dest, cpu_reg(source), tcg_op2);
break;
case 0x2:
tcg_gen_xor_i64(tcg_dest, cpu_reg(source), tcg_op2);
break;
}
if (is_32bit) {
tcg_gen_ext32u_i64(tcg_dest, tcg_dest);
}
if (setflags) {
gen_helper_pstate_add(pstate, pstate, tcg_dest, cpu_reg(31), tcg_dest);
}
tcg_temp_free_i64(tcg_op2);
}
static void setflags_add(bool sub_op, bool is_32bit, TCGv_i64 src,
TCGv_i64 op2, TCGv_i64 res)
{
if (sub_op) {
if (is_32bit) {
gen_helper_pstate_sub32(pstate, pstate, src, op2, res);
} else {
gen_helper_pstate_sub(pstate, pstate, src, op2, res);
}
} else {
if (is_32bit) {
gen_helper_pstate_add32(pstate, pstate, src, op2, res);
} else {
gen_helper_pstate_add(pstate, pstate, src, op2, res);
}
}
}
static void reg_extend(TCGv_i64 tcg_offset, int option, int shift, int reg)
{
int extsize = get_bits(option, 0, 2);
bool is_signed = get_bits(option, 2, 1);
if (is_signed) {
switch (extsize) {
case 0:
tcg_gen_ext8s_i64(tcg_offset, cpu_reg(reg));
break;
case 1:
tcg_gen_ext16s_i64(tcg_offset, cpu_reg(reg));
break;
case 2:
tcg_gen_ext32s_i64(tcg_offset, cpu_reg(reg));
break;
case 3:
tcg_gen_mov_i64(tcg_offset, cpu_reg(reg));
break;
}
} else {
switch (extsize) {
case 0:
tcg_gen_ext8u_i64(tcg_offset, cpu_reg(reg));
break;
case 1:
tcg_gen_ext16u_i64(tcg_offset, cpu_reg(reg));
break;
case 2:
tcg_gen_ext32u_i64(tcg_offset, cpu_reg(reg));
break;
case 3:
tcg_gen_mov_i64(tcg_offset, cpu_reg(reg));
break;
}
}
if (shift) {
tcg_gen_shli_i64(tcg_offset, tcg_offset, shift);
}
}
static void handle_add(DisasContext *s, uint32_t insn)
{
int dest = get_reg(insn);
int source = get_bits(insn, 5, 5);
int shift_amount = get_sbits(insn, 10, 6);
int rm = get_bits(insn, 16, 5);
bool extend = get_bits(insn, 21, 1);
int shift_type = get_bits(insn, 22, 2);
bool setflags = get_bits(insn, 29, 1);
bool sub_op = get_bits(insn, 30, 1);
bool is_32bit = !get_bits(insn, 31, 1);
bool is_carry = (get_bits(insn, 24, 5) == 0x1a);
int extend_type = 0;
TCGv_i64 tcg_op2;
TCGv_i64 tcg_src = tcg_temp_new_i64();
TCGv_i64 tcg_dst;
TCGv_i64 tcg_result = tcg_temp_new_i64();
if (extend && shift_type) {
unallocated_encoding(s);
}
tcg_gen_mov_i64(tcg_src, cpu_reg(source));
tcg_dst = cpu_reg(dest);
if (extend) {
extend_type = (shift_amount >> 3) & 0x7;
shift_amount &= 7;
if (shift_amount > 4) {
/* reserved value */
unallocated_encoding(s);
}
tcg_gen_mov_i64(tcg_src, cpu_reg_sp(source));
if (!setflags) {
tcg_dst = cpu_reg_sp(dest);
}
} else {
if (shift_type == 3) {
/* reserved value */
unallocated_encoding(s);
}
if (is_32bit && (shift_amount < 0)) {
/* reserved value */
unallocated_encoding(s);
}
}
if (extend) {
tcg_op2 = tcg_temp_new_i64();
reg_extend(tcg_op2, extend_type, shift_amount, rm);
} else {
tcg_op2 = get_shifti(rm, shift_type, shift_amount, is_32bit);
}
if (is_32bit) {
tcg_gen_ext32s_i64(tcg_src, tcg_src);
tcg_gen_ext32s_i64(tcg_op2, tcg_op2);
}
if (sub_op) {
tcg_gen_sub_i64(tcg_result, tcg_src, tcg_op2);
} else {
tcg_gen_add_i64(tcg_result, tcg_src, tcg_op2);
}
if (is_carry) {
TCGv_i64 tcg_carry = tcg_temp_new_i64();
tcg_gen_shri_i64(tcg_carry, pstate, PSTATE_C_SHIFT);
tcg_gen_andi_i64(tcg_carry, tcg_carry, 1);
tcg_gen_add_i64(tcg_result, tcg_result, tcg_carry);
if (sub_op) {
tcg_gen_subi_i64(tcg_result, tcg_result, 1);
}
tcg_temp_free_i64(tcg_carry);
}
if (setflags) {
setflags_add(sub_op, is_32bit, tcg_src, tcg_op2, tcg_result);
}
if (is_32bit) {
tcg_gen_ext32u_i64(tcg_dst, tcg_result);
} else {
tcg_gen_mov_i64(tcg_dst, tcg_result);
}
tcg_temp_free_i64(tcg_src);
tcg_temp_free_i64(tcg_op2);
tcg_temp_free_i64(tcg_result);
}
static void ldst_do_vec_int(DisasContext *s, int freg_offs, TCGv_i64 tcg_addr,
int size, bool is_store)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
if (is_store) {
switch (size) {
case 0:
tcg_gen_ld8u_i64(tcg_tmp, cpu_env, freg_offs);
tcg_gen_qemu_st8(tcg_tmp, tcg_addr, get_mem_index(s));
break;
case 1:
tcg_gen_ld16u_i64(tcg_tmp, cpu_env, freg_offs);
tcg_gen_qemu_st16(tcg_tmp, tcg_addr, get_mem_index(s));
break;
case 2:
tcg_gen_ld32u_i64(tcg_tmp, cpu_env, freg_offs);
tcg_gen_qemu_st32(tcg_tmp, tcg_addr, get_mem_index(s));
break;
case 4:
tcg_gen_ld_i64(tcg_tmp, cpu_env, freg_offs);
tcg_gen_qemu_st64(tcg_tmp, tcg_addr, get_mem_index(s));
freg_offs += sizeof(uint64_t);
tcg_gen_addi_i64(tcg_addr, tcg_addr, sizeof(uint64_t));
/* fall through */
case 3:
tcg_gen_ld_i64(tcg_tmp, cpu_env, freg_offs);
tcg_gen_qemu_st64(tcg_tmp, tcg_addr, get_mem_index(s));
break;
}
} else {
switch (size) {
case 0:
tcg_gen_qemu_ld8u(tcg_tmp, tcg_addr, get_mem_index(s));
tcg_gen_st8_i64(tcg_tmp, cpu_env, freg_offs);
break;
case 1:
tcg_gen_qemu_ld16u(tcg_tmp, tcg_addr, get_mem_index(s));
tcg_gen_st16_i64(tcg_tmp, cpu_env, freg_offs);
break;
case 2:
tcg_gen_qemu_ld32u(tcg_tmp, tcg_addr, get_mem_index(s));
tcg_gen_st32_i64(tcg_tmp, cpu_env, freg_offs);
break;
case 4:
tcg_gen_qemu_ld64(tcg_tmp, tcg_addr, get_mem_index(s));
tcg_gen_st_i64(tcg_tmp, cpu_env, freg_offs);
freg_offs += sizeof(uint64_t);
tcg_gen_addi_i64(tcg_addr, tcg_addr, sizeof(uint64_t));
/* fall through */
case 3:
tcg_gen_qemu_ld64(tcg_tmp, tcg_addr, get_mem_index(s));
tcg_gen_st_i64(tcg_tmp, cpu_env, freg_offs);
break;
}
}
tcg_temp_free_i64(tcg_tmp);
}
static void ldst_do_vec(DisasContext *s, int dest, TCGv_i64 tcg_addr_real,
int size, bool is_store)
{
TCGv_i64 tcg_addr = tcg_temp_new_i64();
int freg_offs = offsetof(CPUARMState, vfp.regs[dest * 2]);
/* we don't want to modify the caller's tcg_addr */
tcg_gen_mov_i64(tcg_addr, tcg_addr_real);
if (!is_store) {
/* normal ldst clears non-loaded bits */
clear_fpreg(dest);
}
ldst_do_vec_int(s, freg_offs, tcg_addr, size, is_store);
tcg_temp_free(tcg_addr);
}
static void ldst_do_gpr(DisasContext *s, int dest, TCGv_i64 tcg_addr, int size,
bool is_store, bool is_signed)
{
if (is_store) {