forked from openjdk/panama-foreign
/
aarch64_neon.ad
6189 lines (5767 loc) · 216 KB
/
aarch64_neon.ad
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// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
// This file is automatically generated by running "m4 aarch64_neon_ad.m4". Do not edit ----
// AArch64 NEON Architecture Description File
// ====================VECTOR INSTRUCTIONS==================================
// ------------------------------ Load/store/reinterpret -----------------------
// Load Vector (16 bits)
instruct loadV2(vecD dst, vmem2 mem)
%{
predicate(n->as_LoadVector()->memory_size() == 2);
match(Set dst (LoadVector mem));
ins_cost(4 * INSN_COST);
format %{ "ldrh $dst,$mem\t# vector (16 bits)" %}
ins_encode( aarch64_enc_ldrvH(dst, mem) );
ins_pipe(vload_reg_mem64);
%}
// Load Vector (32 bits)
instruct loadV4(vecD dst, vmem4 mem)
%{
predicate(n->as_LoadVector()->memory_size() == 4);
match(Set dst (LoadVector mem));
ins_cost(4 * INSN_COST);
format %{ "ldrs $dst,$mem\t# vector (32 bits)" %}
ins_encode( aarch64_enc_ldrvS(dst, mem) );
ins_pipe(vload_reg_mem64);
%}
// Load Vector (64 bits)
instruct loadV8(vecD dst, vmem8 mem)
%{
predicate(n->as_LoadVector()->memory_size() == 8);
match(Set dst (LoadVector mem));
ins_cost(4 * INSN_COST);
format %{ "ldrd $dst,$mem\t# vector (64 bits)" %}
ins_encode( aarch64_enc_ldrvD(dst, mem) );
ins_pipe(vload_reg_mem64);
%}
// Load Vector (128 bits)
instruct loadV16(vecX dst, vmem16 mem)
%{
predicate(UseSVE == 0 && n->as_LoadVector()->memory_size() == 16);
match(Set dst (LoadVector mem));
ins_cost(4 * INSN_COST);
format %{ "ldrq $dst,$mem\t# vector (128 bits)" %}
ins_encode( aarch64_enc_ldrvQ(dst, mem) );
ins_pipe(vload_reg_mem128);
%}
// Store Vector (16 bits)
instruct storeV2(vecD src, vmem2 mem)
%{
predicate(n->as_StoreVector()->memory_size() == 2);
match(Set mem (StoreVector mem src));
ins_cost(4 * INSN_COST);
format %{ "strh $mem,$src\t# vector (16 bits)" %}
ins_encode( aarch64_enc_strvH(src, mem) );
ins_pipe(vstore_reg_mem64);
%}
// Store Vector (32 bits)
instruct storeV4(vecD src, vmem4 mem)
%{
predicate(n->as_StoreVector()->memory_size() == 4);
match(Set mem (StoreVector mem src));
ins_cost(4 * INSN_COST);
format %{ "strs $mem,$src\t# vector (32 bits)" %}
ins_encode( aarch64_enc_strvS(src, mem) );
ins_pipe(vstore_reg_mem64);
%}
// Store Vector (64 bits)
instruct storeV8(vecD src, vmem8 mem)
%{
predicate(n->as_StoreVector()->memory_size() == 8);
match(Set mem (StoreVector mem src));
ins_cost(4 * INSN_COST);
format %{ "strd $mem,$src\t# vector (64 bits)" %}
ins_encode( aarch64_enc_strvD(src, mem) );
ins_pipe(vstore_reg_mem64);
%}
// Store Vector (128 bits)
instruct storeV16(vecX src, vmem16 mem)
%{
predicate(n->as_StoreVector()->memory_size() == 16);
match(Set mem (StoreVector mem src));
ins_cost(4 * INSN_COST);
format %{ "strq $mem,$src\t# vector (128 bits)" %}
ins_encode( aarch64_enc_strvQ(src, mem) );
ins_pipe(vstore_reg_mem128);
%}
instruct reinterpretD(vecD dst)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ " # reinterpret $dst" %}
ins_encode %{
// empty
%}
ins_pipe(pipe_class_empty);
%}
instruct reinterpretX(vecX dst)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ " # reinterpret $dst" %}
ins_encode %{
// empty
%}
ins_pipe(pipe_class_empty);
%}
instruct reinterpretD2X(vecX dst, vecD src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src\t# D2X" %}
ins_encode %{
// If registers are the same, no register move is required - the
// upper 64 bits of 'src' are expected to have been initialized
// to zero.
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
}
%}
ins_pipe(vlogical64);
%}
instruct reinterpretX2D(vecD dst, vecX src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src\t# X2D" %}
ins_encode %{
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
// the "dst" register must be cleared to zero.
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
%}
ins_pipe(vlogical64);
%}
// ------------------------------ Vector cast -------------------------------
instruct vcvt4Bto4S(vecD dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (VectorCastB2X src));
format %{ "sxtl $dst, T8H, $src, T8B\t# convert 4B to 4S vector" %}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt8Bto8S(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (VectorCastB2X src));
format %{ "sxtl $dst, T8H, $src, T8B\t# convert 8B to 8S vector" %}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt4Sto4B(vecD dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorCastS2X src));
format %{ "xtn $dst, T8B, $src, T8H\t# convert 4S to 4B vector" %}
ins_encode %{
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt8Sto8B(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorCastS2X src));
format %{ "xtn $dst, T8B, $src, T8H\t# convert 8S to 8B vector" %}
ins_encode %{
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt4Sto4I(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (VectorCastS2X src));
format %{ "sxtl $dst, T4S, $src, T4H\t# convert 4S to 4I vector" %}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt4Ito4S(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (VectorCastI2X src));
format %{ "xtn $dst, T4H, $src, T4S\t# convert 4I to 4S vector" %}
ins_encode %{
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Ito2L(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (VectorCastI2X src));
format %{ "sxtl $dst, T2D, $src, T2S\t# convert 2I to 2L vector" %}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Lto2I(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (VectorCastL2X src));
format %{ "xtn $dst, T2S, $src, T2D\t# convert 2L to 2I vector" %}
ins_encode %{
__ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt4Bto4I(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (VectorCastB2X src));
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
"sxtl $dst, T4S, $dst, T4H\t# convert 4B to 4I vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
%}
ins_pipe(pipe_slow);
%}
instruct vcvt4Ito4B(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (VectorCastI2X src));
format %{ "xtn $dst, T4H, $src, T4S\n\t"
"xtn $dst, T8B, $dst, T8H\t# convert 4I to 4B vector"
%}
ins_encode %{
__ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
__ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
%}
ins_pipe(pipe_slow);
%}
instruct vcvt4Bto4F(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastB2X src));
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
"sxtl $dst, T4S, $dst, T4H\n\t"
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vcvt4Sto4F(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastS2X src));
format %{ "sxtl $dst, T4S, $src, T4H\n\t"
"scvtfv T4S, $dst, $dst\t# convert 4S to 4F vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vcvt2Ito2D(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (VectorCastI2X src));
format %{ "sxtl $dst, T2D, $src, T2S\n\t"
"scvtfv T2D, $dst, $dst\t# convert 2I to 2D vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vcvt2Ito2F(vecD dst, vecD src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastI2X src));
format %{ "scvtfv T2S, $dst, $src\t# convert 2I to 2F vector" %}
ins_encode %{
__ scvtfv(__ T2S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt4Ito4F(vecX dst, vecX src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastI2X src));
format %{ "scvtfv T4S, $dst, $src\t# convert 4I to 4F vector" %}
ins_encode %{
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Lto2D(vecX dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (VectorCastL2X src));
format %{ "scvtfv T2D, $dst, $src\t# convert 2L to 2D vector" %}
ins_encode %{
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Fto2D(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (VectorCastF2X src));
format %{ "fcvtl $dst, T2D, $src, T2S\t# convert 2F to 2D vector" %}
ins_encode %{
__ fcvtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Dto2F(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastD2X src));
format %{ "fcvtn $dst, T2S, $src, T2D\t# convert 2D to 2F vector" %}
ins_encode %{
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
%}
ins_pipe(pipe_class_default);
%}
instruct vcvt2Lto2F(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastL2X src));
format %{ "scvtfv T2D, $dst, $src\n\t"
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
%}
ins_encode %{
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
%}
ins_pipe(pipe_slow);
%}
// ------------------------------ Reduction -------------------------------
instruct reduce_add8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addv $tmp, T8B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"addw $dst, $dst, $isrc\n\t"
"sxtb $dst, $dst\t# add reduction8B"
%}
ins_encode %{
__ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
__ addw($dst$$Register, $dst$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_add16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addv $tmp, T16B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"addw $dst, $dst, $isrc\n\t"
"sxtb $dst, $dst\t# add reduction16B"
%}
ins_encode %{
__ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
__ addw($dst$$Register, $dst$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_add4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addv $tmp, T4H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"addw $dst, $dst, $isrc\n\t"
"sxth $dst, $dst\t# add reduction4S"
%}
ins_encode %{
__ addv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
__ addw($dst$$Register, $dst$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_add8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addv $tmp, T8H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"addw $dst, $dst, $isrc\n\t"
"sxth $dst, $dst\t# add reduction8S"
%}
ins_encode %{
__ addv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
__ addw($dst$$Register, $dst$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_add2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, vecX tmp)
%{
match(Set dst (AddReductionVL isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addpd $tmp, $vsrc\n\t"
"umov $dst, $tmp, D, 0\n\t"
"add $dst, $isrc, $dst\t# add reduction2L"
%}
ins_encode %{
__ addpd(as_FloatRegister($tmp$$reg), as_FloatRegister($vsrc$$reg));
__ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ D, 0);
__ add($dst$$Register, $isrc$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp1, vecD vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, S, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
"ins $vtmp2, H, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, B, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxtb $dst, $dst\n\t"
"umov $itmp, $vtmp2, B, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxtb $dst, $dst\t# mul reduction8B"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ S,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ H,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
"ins $vtmp2, S, $vtmp1, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp2, $vtmp1\n\t"
"ins $vtmp2, H, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, B, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxtb $dst, $dst\n\t"
"umov $itmp, $vtmp2, B, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxtb $dst, $dst\t# mul reduction16B"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ D,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ S,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ H,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp, TEMP itmp);
format %{ "ins $vtmp, S, $vsrc, 0, 1\n\t"
"mulv $vtmp, T4H, $vtmp, $vsrc\n\t"
"umov $itmp, $vtmp, H, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxth $dst, $dst\n\t"
"umov $itmp, $vtmp, H, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxth $dst, $dst\t# mul reduction4S"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp$$reg), __ S,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp$$reg), __ T4H,
as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T4H, $vtmp1, $vsrc\n\t"
"ins $vtmp2, S, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T4H, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, H, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxth $dst, $dst\n\t"
"umov $itmp, $vtmp2, H, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxth $dst, $dst\t# mul reduction8S"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ D,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T4H,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ S,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T4H,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
%{
match(Set dst (MulReductionVL isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"mul $dst, $isrc, $tmp\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"mul $dst, $dst, $tmp\t# mul reduction2L"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ mul($dst$$Register, $isrc$$Register, $tmp$$Register);
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ mul($dst$$Register, $dst$$Register, $tmp$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxv $tmp, T8B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction8B"
%}
ins_encode %{
__ smaxv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxv $tmp, T16B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction16B"
%}
ins_encode %{
__ smaxv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxv $tmp, T4H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction4S"
%}
ins_encode %{
__ smaxv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxv $tmp, T8H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction8S"
%}
ins_encode %{
__ smaxv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxv $tmp, T4S, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction4I"
%}
ins_encode %{
__ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminv $tmp, T8B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction8B"
%}
ins_encode %{
__ sminv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminv $tmp, T16B, $vsrc\n\t"
"smov $dst, $tmp, B, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction16B"
%}
ins_encode %{
__ sminv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminv $tmp, T4H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction4S"
%}
ins_encode %{
__ sminv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminv $tmp, T8H, $vsrc\n\t"
"smov $dst, $tmp, H, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction8S"
%}
ins_encode %{
__ sminv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
__ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminv $tmp, T4S, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction4I"
%}
ins_encode %{
__ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "smaxp $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc GT\t# max reduction2I"
%}
ins_encode %{
__ smaxp(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "sminp $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc LT\t# min reduction2I"
%}
ins_encode %{
__ sminp(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (MaxReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"cmp $isrc,$tmp\n\t"
"csel $dst, $isrc, $tmp GT\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"cmp $dst, $tmp\n\t"
"csel $dst, $dst, $tmp GT\t# max reduction2L"
%}
ins_encode %{
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
__ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::GT);
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
__ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::GT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_min2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (MinReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"cmp $isrc,$tmp\n\t"
"csel $dst, $isrc, $tmp LT\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"cmp $dst, $tmp\n\t"
"csel $dst, $dst, $tmp LT\t# min reduction2L"
%}
ins_encode %{
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
__ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::LT);
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
__ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::LT);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_max2F(vRegF dst, vRegF fsrc, vecD vsrc) %{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (MaxReductionV fsrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst);
format %{ "fmaxp $dst, $vsrc, S\n\t"
"fmaxs $dst, $dst, $fsrc\t# max reduction2F" %}
ins_encode %{
__ fmaxp(as_FloatRegister($dst$$reg), as_FloatRegister($vsrc$$reg), __ S);
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct reduce_max4F(vRegF dst, vRegF fsrc, vecX vsrc) %{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (MaxReductionV fsrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst);
format %{ "fmaxv $dst, T4S, $vsrc\n\t"
"fmaxs $dst, $dst, $fsrc\t# max reduction4F" %}
ins_encode %{
__ fmaxv(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
__ fmaxs(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($fsrc$$reg));
%}
ins_pipe(pipe_class_default);
%}
instruct reduce_max2D(vRegD dst, vRegD dsrc, vecX vsrc) %{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (MaxReductionV dsrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst);
format %{ "fmaxp $dst, $vsrc, D\n\t"
"fmaxd $dst, $dst, $dsrc\t# max reduction2D" %}
ins_encode %{