forked from openjdk/panama-foreign
/
aarch64_neon_ad.m4
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aarch64_neon_ad.m4
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// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
dnl Generate the warning
// This file is automatically generated by running "m4 aarch64_neon_ad.m4". Do not edit ----
dnl
// AArch64 NEON Architecture Description File
dnl
define(`ORL2I', `ifelse($1,I,orL2I)')dnl
dnl
define(`error', `__program__:__file__:__line__: Invalid argument ``$1''m4exit(`1')')dnl
dnl
define(`iTYPE2SIMD',
`ifelse($1, `B', `B',
$1, `S', `H',
$1, `I', `S',
$1, `L', `D',
`error($1)')')dnl
dnl
define(`fTYPE2SIMD',
`ifelse($1, `F', `S',
$1, `D', `D',
`error($1)')')dnl
dnl
define(`TYPE2DATATYPE',
`ifelse($1, `B', `BYTE',
$1, `S', `SHORT',
$1, `I', `INT',
$1, `L', `LONG',
$1, `F', `FLOAT',
$1, `D', `DOUBLE',
`error($1)')')dnl
dnl
// ====================VECTOR INSTRUCTIONS==================================
// ------------------------------ Load/store/reinterpret -----------------------
define(`VLoadStore', `
// ifelse(load, $3, Load, Store) Vector ($6 bits)
instruct $3V$4`'(vec$5 $7, vmem$4 mem)
%{
predicate($8`n->as_'ifelse(load, $3, Load, Store)Vector()->memory_size() == $4);
match(Set ifelse(load, $3, dst (LoadVector mem), mem (StoreVector mem src)));
ins_cost(4 * INSN_COST);
format %{ "$1 ifelse(load, $3, `$dst,$mem', `$mem,$src')\t# vector ($6 bits)" %}
ins_encode( `aarch64_enc_'ifelse(load, $3, ldr, str)v$2($7, mem) );
ins_pipe(v$3`_reg_mem'ifelse(eval($4 * 8), 128, 128, 64));
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
VLoadStore(ldrh, H, load, 2, D, 16, dst, )
VLoadStore(ldrs, S, load, 4, D, 32, dst, )
VLoadStore(ldrd, D, load, 8, D, 64, dst, )
VLoadStore(ldrq, Q, load, 16, X, 128, dst, UseSVE == 0 && )
VLoadStore(strh, H, store, 2, D, 16, src, )
VLoadStore(strs, S, store, 4, D, 32, src, )
VLoadStore(strd, D, store, 8, D, 64, src, )
VLoadStore(strq, Q, store, 16, X, 128, src, )
dnl
define(`REINTERPRET', `
instruct reinterpret$1`'(vec$1 dst)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == $2 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == $2);
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ " # reinterpret $dst" %}
ins_encode %{
// empty
%}
ins_pipe(pipe_class_empty);
%}')dnl
dnl $1 $2
REINTERPRET(D, 8)
REINTERPRET(X, 16)
dnl
instruct reinterpretD2X(vecX dst, vecD src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src\t# D2X" %}
ins_encode %{
// If registers are the same, no register move is required - the
// upper 64 bits of 'src' are expected to have been initialized
// to zero.
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
}
%}
ins_pipe(vlogical64);
%}
instruct reinterpretX2D(vecD dst, vecX src)
%{
predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
match(Set dst (VectorReinterpret src));
ins_cost(INSN_COST);
format %{ " # reinterpret $dst,$src\t# X2D" %}
ins_encode %{
// Resize the vector from 128-bits to 64-bits. The higher 64-bits of
// the "dst" register must be cleared to zero.
__ orr(as_FloatRegister($dst$$reg), __ T8B,
as_FloatRegister($src$$reg),
as_FloatRegister($src$$reg));
%}
ins_pipe(vlogical64);
%}
// ------------------------------ Vector cast -------------------------------
dnl
define(`VECTOR_CAST_I2I', `
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$5 src)
%{
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorCast$2`'2X src));
format %{ "$6 $dst, T$8, $src, T$7\t# convert $1$2 to $1$3 vector" %}
ins_encode %{
__ $6(as_FloatRegister($dst$$reg), __ T$8, as_FloatRegister($src$$reg), __ T$7);
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
VECTOR_CAST_I2I(4, B, S, D, D, sxtl, 8B, 8H)
VECTOR_CAST_I2I(8, B, S, X, D, sxtl, 8B, 8H)
VECTOR_CAST_I2I(4, S, B, D, D, xtn, 8H, 8B)
VECTOR_CAST_I2I(8, S, B, D, X, xtn, 8H, 8B)
VECTOR_CAST_I2I(4, S, I, X, D, sxtl, 4H, 4S)
VECTOR_CAST_I2I(4, I, S, D, X, xtn, 4S, 4H)
VECTOR_CAST_I2I(2, I, L, X, D, sxtl, 2S, 2D)
VECTOR_CAST_I2I(2, L, I, D, X, xtn, 2D, 2S)
dnl
define(`VECTOR_CAST_B2I', `
instruct vcvt4$1to4$2`'(vec$3 dst, vec$4 src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorCast$1`'2X src));
format %{ "$5 $dst, T$7, $src, T$6\n\t"
"$5 $dst, T$9, $dst, T$8\t# convert 4$1 to 4$2 vector"
%}
ins_encode %{
__ $5(as_FloatRegister($dst$$reg), __ T$7, as_FloatRegister($src$$reg), __ T$6);
__ $5(as_FloatRegister($dst$$reg), __ T$9, as_FloatRegister($dst$$reg), __ T$8);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8 $9
VECTOR_CAST_B2I(B, I, X, D, sxtl, 8B, 8H, 4H, 4S)
VECTOR_CAST_B2I(I, B, D, X, xtn, 4S, 4H, 8H, 8B)
instruct vcvt4Bto4F(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastB2X src));
format %{ "sxtl $dst, T8H, $src, T8B\n\t"
"sxtl $dst, T4S, $dst, T4H\n\t"
"scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
__ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
__ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}
dnl
define(`VECTOR_CAST_I2F_L', `
instruct vcvt$1$2to$1$3`'(vecX dst, vecD src)
%{
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorCast$2`'2X src));
format %{ "sxtl $dst, T$5, $src, T$4\n\t"
"scvtfv T$5, $dst, $dst\t# convert $1$2 to $1$3 vector"
%}
ins_encode %{
__ sxtl(as_FloatRegister($dst$$reg), __ T$5, as_FloatRegister($src$$reg), __ T$4);
__ scvtfv(__ T$5, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5
VECTOR_CAST_I2F_L(4, S, F, 4H, 4S)
VECTOR_CAST_I2F_L(2, I, D, 2S, 2D)
dnl
define(`VECTOR_CAST_I2F', `
instruct vcvt$1$2to$1$3`'(vec$4 dst, vec$4 src)
%{
predicate(n->as_Vector()->length() == $1 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorCast$2`'2X src));
format %{ "scvtfv T$5, $dst, $src\t# convert $1$2 to $1$3 vector" %}
ins_encode %{
__ scvtfv(__ T$5, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5
VECTOR_CAST_I2F(2, I, F, D, 2S)
VECTOR_CAST_I2F(4, I, F, X, 4S)
VECTOR_CAST_I2F(2, L, D, X, 2D)
dnl
define(`VECTOR_CAST_F2F', `
instruct vcvt2$1to2$2`'(vec$3 dst, vec$4 src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorCast$1`'2X src));
format %{ "$5 $dst, T$7, $src, T$6\t# convert 2$1 to 2$2 vector" %}
ins_encode %{
__ $5(as_FloatRegister($dst$$reg), __ T$7, as_FloatRegister($src$$reg), __ T$6);
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
VECTOR_CAST_F2F(F, D, X, D, fcvtl, 2S, 2D)
VECTOR_CAST_F2F(D, F, D, X, fcvtn, 2D, 2S)
dnl
instruct vcvt2Lto2F(vecD dst, vecX src)
%{
predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (VectorCastL2X src));
format %{ "scvtfv T2D, $dst, $src\n\t"
"fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
%}
ins_encode %{
__ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
__ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
%}
ins_pipe(pipe_slow);
%}
// ------------------------------ Reduction -------------------------------
dnl
define(`REDUCE_ADD_BORS', `
instruct reduce_add$1$2`'(iRegINoSp dst, iRegIorL2I isrc, vec$3 vsrc, vec$3 tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (AddReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addv $tmp, T$1`'iTYPE2SIMD($2), $vsrc\n\t"
"smov $dst, $tmp, iTYPE2SIMD($2), 0\n\t"
"addw $dst, $dst, $isrc\n\t"
"sxt$4 $dst, $dst\t# add reduction$1$2"
%}
ins_encode %{
__ addv(as_FloatRegister($tmp$$reg), __ T$1`'iTYPE2SIMD($2), as_FloatRegister($vsrc$$reg));
__ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ iTYPE2SIMD($2), 0);
__ addw($dst$$Register, $dst$$Register, $isrc$$Register);
__ sxt$4($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4
REDUCE_ADD_BORS(8, B, D, b)
REDUCE_ADD_BORS(16, B, X, b)
REDUCE_ADD_BORS(4, S, D, h)
REDUCE_ADD_BORS(8, S, X, h)
dnl
instruct reduce_add2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, vecX tmp)
%{
match(Set dst (AddReductionVL isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "addpd $tmp, $vsrc\n\t"
"umov $dst, $tmp, D, 0\n\t"
"add $dst, $isrc, $dst\t# add reduction2L"
%}
ins_encode %{
__ addpd(as_FloatRegister($tmp$$reg), as_FloatRegister($vsrc$$reg));
__ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ D, 0);
__ add($dst$$Register, $isrc$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp1, vecD vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, S, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
"ins $vtmp2, H, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, B, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxtb $dst, $dst\n\t"
"umov $itmp, $vtmp2, B, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxtb $dst, $dst\t# mul reduction8B"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ S,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ H,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
"ins $vtmp2, S, $vtmp1, 0, 1\n\t"
"mulv $vtmp1, T8B, $vtmp2, $vtmp1\n\t"
"ins $vtmp2, H, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, B, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxtb $dst, $dst\n\t"
"umov $itmp, $vtmp2, B, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxtb $dst, $dst\t# mul reduction16B"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ D,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ S,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ H,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxtb($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp, TEMP itmp);
format %{ "ins $vtmp, S, $vsrc, 0, 1\n\t"
"mulv $vtmp, T4H, $vtmp, $vsrc\n\t"
"umov $itmp, $vtmp, H, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxth $dst, $dst\n\t"
"umov $itmp, $vtmp, H, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxth $dst, $dst\t# mul reduction4S"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp$$reg), __ S,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp$$reg), __ T4H,
as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (MulReductionVI isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
"mulv $vtmp1, T4H, $vtmp1, $vsrc\n\t"
"ins $vtmp2, S, $vtmp1, 0, 1\n\t"
"mulv $vtmp2, T4H, $vtmp2, $vtmp1\n\t"
"umov $itmp, $vtmp2, H, 0\n\t"
"mulw $dst, $itmp, $isrc\n\t"
"sxth $dst, $dst\n\t"
"umov $itmp, $vtmp2, H, 1\n\t"
"mulw $dst, $itmp, $dst\n\t"
"sxth $dst, $dst\t# mul reduction8S"
%}
ins_encode %{
__ ins(as_FloatRegister($vtmp1$$reg), __ D,
as_FloatRegister($vsrc$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp1$$reg), __ T4H,
as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
__ ins(as_FloatRegister($vtmp2$$reg), __ S,
as_FloatRegister($vtmp1$$reg), 0, 1);
__ mulv(as_FloatRegister($vtmp2$$reg), __ T4H,
as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 0);
__ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
__ sxth($dst$$Register, $dst$$Register);
__ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 1);
__ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}
instruct reduce_mul2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
%{
match(Set dst (MulReductionVL isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"mul $dst, $isrc, $tmp\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"mul $dst, $dst, $tmp\t# mul reduction2L"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ mul($dst$$Register, $isrc$$Register, $tmp$$Register);
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ mul($dst$$Register, $dst$$Register, $tmp$$Register);
%}
ins_pipe(pipe_slow);
%}
dnl
define(`REDUCE_MAX_MIN_INT', `
instruct reduce_$1$2$3`'(iRegINoSp dst, iRegIorL2I isrc, vec$4 vsrc, vec$4 tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst ($5ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "s$1v $tmp, T$2`'iTYPE2SIMD($3), $vsrc\n\t"
"$6mov $dst, $tmp, iTYPE2SIMD($3), 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc $7\t# $1 reduction$2$3"
%}
ins_encode %{
__ s$1v(as_FloatRegister($tmp$$reg), __ T$2`'iTYPE2SIMD($3), as_FloatRegister($vsrc$$reg));
__ $6mov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ iTYPE2SIMD($3), 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::$7);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
REDUCE_MAX_MIN_INT(max, 8, B, D, Max, s, GT)
REDUCE_MAX_MIN_INT(max, 16, B, X, Max, s, GT)
REDUCE_MAX_MIN_INT(max, 4, S, D, Max, s, GT)
REDUCE_MAX_MIN_INT(max, 8, S, X, Max, s, GT)
REDUCE_MAX_MIN_INT(max, 4, I, X, Max, u, GT)
REDUCE_MAX_MIN_INT(min, 8, B, D, Min, s, LT)
REDUCE_MAX_MIN_INT(min, 16, B, X, Min, s, LT)
REDUCE_MAX_MIN_INT(min, 4, S, D, Min, s, LT)
REDUCE_MAX_MIN_INT(min, 8, S, X, Min, s, LT)
REDUCE_MAX_MIN_INT(min, 4, I, X, Min, u, LT)
dnl
define(`REDUCE_MAX_MIN_2I', `
instruct reduce_$1`'2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "s$1p $tmp, T2S, $vsrc, $vsrc\n\t"
"umov $dst, $tmp, S, 0\n\t"
"cmpw $dst, $isrc\n\t"
"cselw $dst, $dst, $isrc $3\t# $1 reduction2I"
%}
ins_encode %{
__ s$1p(as_FloatRegister($tmp$$reg), __ T2S, as_FloatRegister($vsrc$$reg), as_FloatRegister($vsrc$$reg));
__ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
__ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
__ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::$3);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_MAX_MIN_2I(max, Max, GT)
REDUCE_MAX_MIN_2I(min, Min, LT)
dnl
define(`REDUCE_MAX_MIN_2L', `
instruct reduce_$1`'2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp, KILL cr);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"cmp $isrc,$tmp\n\t"
"csel $dst, $isrc, $tmp $3\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"cmp $dst, $tmp\n\t"
"csel $dst, $dst, $tmp $3\t# $1 reduction2L"
%}
ins_encode %{
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
__ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::$3);
__ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
__ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
__ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::$3);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_MAX_MIN_2L(max, Max, GT)
REDUCE_MAX_MIN_2L(min, Min, LT)
dnl
define(`REDUCE_MINMAX_FORD', `
instruct reduce_$1$4$5(vReg$5 dst, vReg$5 $6src, vec$7 vsrc) %{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_`'ifelse($5, F, FLOAT, DOUBLE));
match(Set dst (ifelse($1, max, Max, Min)ReductionV $6src vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst);
format %{ "$2 $dst, ifelse($4, 2, $vsrc`, 'ifelse($5, F, S, D), ` T4S, $vsrc')\n\t"
"$3 $dst, $dst, $$6src\t# $1 reduction$4$5" %}
ins_encode %{
__ $2(as_FloatRegister($dst$$reg), ifelse($4, 4, `__ T4S, as_FloatRegister($vsrc$$reg))',
$4$5, 2F, `as_FloatRegister($vsrc$$reg), __ S)',
$4$5, 2D, `as_FloatRegister($vsrc$$reg), __ D)');
__ $3(as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg), as_FloatRegister($$6src$$reg));
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
REDUCE_MINMAX_FORD(max, fmaxp, fmaxs, 2, F, f, D)
REDUCE_MINMAX_FORD(max, fmaxv, fmaxs, 4, F, f, X)
REDUCE_MINMAX_FORD(max, fmaxp, fmaxd, 2, D, d, X)
REDUCE_MINMAX_FORD(min, fminp, fmins, 2, F, f, D)
REDUCE_MINMAX_FORD(min, fminv, fmins, 4, F, f, X)
REDUCE_MINMAX_FORD(min, fminp, fmind, 2, D, d, X)
dnl
define(`REDUCE_LOGIC_OP_8B', `
instruct reduce_$1`'8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, S, 0\n\t"
"umov $dst, $vsrc, S, 1\n\t"
"$1w $dst, $dst, $tmp\n\t"
"$1w $dst, $dst, $dst, LSR #16\n\t"
"$1w $dst, $dst, $dst, LSR #8\n\t"
"$1w $dst, $isrc, $dst\n\t"
"sxtb $dst, $dst\t# $1 reduction8B"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
__ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
__ $1w($dst$$Register, $dst$$Register, $tmp$$Register);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
__ $1w($dst$$Register, $isrc$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2
REDUCE_LOGIC_OP_8B(and, And)
REDUCE_LOGIC_OP_8B(orr, Or)
REDUCE_LOGIC_OP_8B(eor, Xor)
define(`REDUCE_LOGIC_OP_16B', `
instruct reduce_$1`'16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"umov $dst, $vsrc, D, 1\n\t"
"$3 $dst, $dst, $tmp\n\t"
"$3 $dst, $dst, $dst, LSR #32\n\t"
"$1w $dst, $dst, $dst, LSR #16\n\t"
"$1w $dst, $dst, $dst, LSR #8\n\t"
"$1w $dst, $isrc, $dst\n\t"
"sxtb $dst, $dst\t# $1 reduction16B"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ $3($dst$$Register, $dst$$Register, $tmp$$Register);
__ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
__ $1w($dst$$Register, $isrc$$Register, $dst$$Register);
__ sxtb($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_LOGIC_OP_16B(and, And, andr)
REDUCE_LOGIC_OP_16B(orr, Or, orr )
REDUCE_LOGIC_OP_16B(eor, Xor, eor )
dnl
define(`REDUCE_LOGIC_OP_4S', `
instruct reduce_$1`'4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, S, 0\n\t"
"umov $dst, $vsrc, S, 1\n\t"
"$1w $dst, $dst, $tmp\n\t"
"$1w $dst, $dst, $dst, LSR #16\n\t"
"$1w $dst, $isrc, $dst\n\t"
"sxth $dst, $dst\t# $1 reduction4S"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
__ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
__ $1w($dst$$Register, $dst$$Register, $tmp$$Register);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
__ $1w($dst$$Register, $isrc$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2
REDUCE_LOGIC_OP_4S(and, And)
REDUCE_LOGIC_OP_4S(orr, Or)
REDUCE_LOGIC_OP_4S(eor, Xor)
dnl
define(`REDUCE_LOGIC_OP_8S', `
instruct reduce_$1`'8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"umov $dst, $vsrc, D, 1\n\t"
"$3 $dst, $dst, $tmp\n\t"
"$3 $dst, $dst, $dst, LSR #32\n\t"
"$1w $dst, $dst, $dst, LSR #16\n\t"
"$1w $dst, $isrc, $dst\n\t"
"sxth $dst, $dst\t# $1 reduction8S"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ $3($dst$$Register, $dst$$Register, $tmp$$Register);
__ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
__ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
__ $1w($dst$$Register, $isrc$$Register, $dst$$Register);
__ sxth($dst$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_LOGIC_OP_8S(and, And, andr)
REDUCE_LOGIC_OP_8S(orr, Or, orr )
REDUCE_LOGIC_OP_8S(eor, Xor, eor )
dnl
define(`REDUCE_LOGIC_OP_2I', `
instruct reduce_$1`'2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, S, 0\n\t"
"$1w $dst, $tmp, $isrc\n\t"
"umov $tmp, $vsrc, S, 1\n\t"
"$1w $dst, $tmp, $dst\t# $1 reduction2I"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
__ $1w($dst$$Register, $tmp$$Register, $isrc$$Register);
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
__ $1w($dst$$Register, $tmp$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2
REDUCE_LOGIC_OP_2I(and, And)
REDUCE_LOGIC_OP_2I(orr, Or)
REDUCE_LOGIC_OP_2I(eor, Xor)
dnl
define(`REDUCE_LOGIC_OP_4I', `
instruct reduce_$1`'4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"umov $dst, $vsrc, D, 1\n\t"
"$3 $dst, $dst, $tmp\n\t"
"$3 $dst, $dst, $dst, LSR #32\n\t"
"$1w $dst, $isrc, $dst\t# $1 reduction4I"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ $3($dst$$Register, $dst$$Register, $tmp$$Register);
__ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
__ $1w($dst$$Register, $isrc$$Register, $dst$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_LOGIC_OP_4I(and, And, andr)
REDUCE_LOGIC_OP_4I(orr, Or, orr )
REDUCE_LOGIC_OP_4I(eor, Xor, eor )
dnl
define(`REDUCE_LOGIC_OP_2L', `
instruct reduce_$1`'2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
%{
predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst ($2ReductionV isrc vsrc));
ins_cost(INSN_COST);
effect(TEMP_DEF dst, TEMP tmp);
format %{ "umov $tmp, $vsrc, D, 0\n\t"
"$3 $dst, $isrc, $tmp\n\t"
"umov $tmp, $vsrc, D, 1\n\t"
"$3 $dst, $dst, $tmp\t# $1 reduction2L"
%}
ins_encode %{
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
__ $3($dst$$Register, $isrc$$Register, $tmp$$Register);
__ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
__ $3($dst$$Register, $dst$$Register, $tmp$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3
REDUCE_LOGIC_OP_2L(and, And, andr)
REDUCE_LOGIC_OP_2L(orr, Or, orr )
REDUCE_LOGIC_OP_2L(eor, Xor, eor )
dnl
// ------------------------------ Vector insert ---------------------------------
define(`VECTOR_INSERT_I', `
instruct insert$1$2`'(vec$3 dst, vec$3 src, iReg$4`'ORL2I($4) val, immI idx)
%{
predicate(n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorInsert (Binary src val) idx));
ins_cost(INSN_COST);
format %{ "orr $dst, T$5, $src, $src\n\t"
"mov $dst, T$1`'iTYPE2SIMD($2), $idx, $val\t# insert into vector($1$2)" %}
ins_encode %{
if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
__ orr(as_FloatRegister($dst$$reg), __ T$5,
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
}
__ mov(as_FloatRegister($dst$$reg), __ T$1`'iTYPE2SIMD($2), $idx$$constant, $val$$Register);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5
VECTOR_INSERT_I(8, B, D, I, 8B)
VECTOR_INSERT_I(16, B, X, I, 16B)
VECTOR_INSERT_I(4, S, D, I, 8B)
VECTOR_INSERT_I(8, S, X, I, 16B)
VECTOR_INSERT_I(2, I, D, I, 8B)
VECTOR_INSERT_I(4, I, X, I, 16B)
VECTOR_INSERT_I(2, L, X, L, 16B)
dnl
define(`VECTOR_INSERT_F', `
instruct insert$1`'(vec$2 dst, vec$2 src, vReg$3 val, immI idx)
%{
predicate(n->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorInsert (Binary src val) idx));
ins_cost(INSN_COST);
effect(TEMP_DEF dst);
format %{ "orr $dst, T$4, $src, $src\n\t"
"ins $dst, $5, $val, $idx, 0\t# insert into vector($1)" %}
ins_encode %{
__ orr(as_FloatRegister($dst$$reg), __ T$4,
as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
__ ins(as_FloatRegister($dst$$reg), __ $5,
as_FloatRegister($val$$reg), $idx$$constant, 0);
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5
VECTOR_INSERT_F(2F, D, F, 8B, S)
VECTOR_INSERT_F(4F, X, F, 16B, S)
VECTOR_INSERT_F(2D, X, D, 16B, D)
dnl
// ------------------------------ Vector extract ---------------------------------
define(`VECTOR_EXTRACT_I', `
instruct extract$1$2`'(iReg$3NoSp dst, vec$4 src, immI idx)
%{
predicate(n->in(1)->bottom_type()->is_vect()->length() == $1);
match(Set dst (Extract$2 src idx));
ins_cost(INSN_COST);
format %{ "$5mov $dst, $src, $6, $idx\t# extract from vector($1$2)" %}
ins_encode %{
__ $5mov($dst$$Register, as_FloatRegister($src$$reg), __ $6, $idx$$constant);
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4 $5 $6
VECTOR_EXTRACT_I(8, B, I, D, s, B)
VECTOR_EXTRACT_I(16, B, I, X, s, B)
VECTOR_EXTRACT_I(4, S, I, D, s, H)
VECTOR_EXTRACT_I(8, S, I, X, s, H)
VECTOR_EXTRACT_I(2, I, I, D, u, S)
VECTOR_EXTRACT_I(4, I, I, X, u, S)
VECTOR_EXTRACT_I(2, L, L, X, u, D)
dnl
define(`VECTOR_EXTRACT_F', `
instruct extract$1$2`'(vReg$2 dst, vec$3 src, immI idx)
%{
predicate(n->in(1)->bottom_type()->is_vect()->length() == $1);
match(Set dst (Extract$2 src idx));
ins_cost(INSN_COST);
format %{ "ins $dst, $4, $src, 0, $idx\t# extract from vector($1$2)" %}
ins_encode %{
__ ins(as_FloatRegister($dst$$reg), __ $4,
as_FloatRegister($src$$reg), 0, $idx$$constant);
%}
ins_pipe(pipe_class_default);
%}')dnl
dnl $1 $2 $3 $4
VECTOR_EXTRACT_F(2, F, D, S)
VECTOR_EXTRACT_F(4, F, X, S)
VECTOR_EXTRACT_F(2, D, X, D)
dnl
// ------------------------------ Vector comparison ---------------------------------
define(`VECTOR_CMP_EQ_GT_GE', `
instruct vcm$1$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2, immI cond)
%{
predicate(n->as_Vector()->length() == $2 &&
n->as_VectorMaskCmp()->get_predicate() == BoolTest::$1 &&
n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
format %{ "$6cm$1 $dst, T$2$5, $src1, $src2\t# vector cmp ($2$3)" %}
ins_cost(INSN_COST);
ins_encode %{
__ $6cm$1(as_FloatRegister($dst$$reg), __ T$2$5,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
%}
ins_pipe(vdop$7);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7
VECTOR_CMP_EQ_GT_GE(eq, 8, B, D, B, , 64)
VECTOR_CMP_EQ_GT_GE(eq, 16,B, X, B, , 128)
VECTOR_CMP_EQ_GT_GE(eq, 4, S, D, H, , 64)
VECTOR_CMP_EQ_GT_GE(eq, 8, S, X, H, , 128)
VECTOR_CMP_EQ_GT_GE(eq, 2, I, D, S, , 64)
VECTOR_CMP_EQ_GT_GE(eq, 4, I, X, S, , 128)
VECTOR_CMP_EQ_GT_GE(eq, 2, L, X, D, , 128)
VECTOR_CMP_EQ_GT_GE(eq, 2, F, D, S, f, 64)
VECTOR_CMP_EQ_GT_GE(eq, 4, F, X, S, f, 128)
VECTOR_CMP_EQ_GT_GE(eq, 2, D, X, D, f, 128)
VECTOR_CMP_EQ_GT_GE(gt, 8, B, D, B, , 64)
VECTOR_CMP_EQ_GT_GE(gt, 16,B, X, B, , 128)
VECTOR_CMP_EQ_GT_GE(gt, 4, S, D, H, , 64)
VECTOR_CMP_EQ_GT_GE(gt, 8, S, X, H, , 128)
VECTOR_CMP_EQ_GT_GE(gt, 2, I, D, S, , 64)
VECTOR_CMP_EQ_GT_GE(gt, 4, I, X, S, , 128)
VECTOR_CMP_EQ_GT_GE(gt, 2, L, X, D, , 128)
VECTOR_CMP_EQ_GT_GE(gt, 2, F, D, S, f, 64)
VECTOR_CMP_EQ_GT_GE(gt, 4, F, X, S, f, 128)
VECTOR_CMP_EQ_GT_GE(gt, 2, D, X, D, f, 128)
VECTOR_CMP_EQ_GT_GE(ge, 8, B, D, B, , 64)
VECTOR_CMP_EQ_GT_GE(ge, 16,B, X, B, , 128)
VECTOR_CMP_EQ_GT_GE(ge, 4, S, D, H, , 64)
VECTOR_CMP_EQ_GT_GE(ge, 8, S, X, H, , 128)
VECTOR_CMP_EQ_GT_GE(ge, 2, I, D, S, , 64)
VECTOR_CMP_EQ_GT_GE(ge, 4, I, X, S, , 128)
VECTOR_CMP_EQ_GT_GE(ge, 2, L, X, D, , 128)
VECTOR_CMP_EQ_GT_GE(ge, 2, F, D, S, f, 64)
VECTOR_CMP_EQ_GT_GE(ge, 4, F, X, S, f, 128)
VECTOR_CMP_EQ_GT_GE(ge, 2, D, X, D, f, 128)
dnl
define(`VECTOR_CMP_NE', `
instruct vcmne$1$2`'(vec$3 dst, vec$3 src1, vec$3 src2, immI cond)
%{
predicate(n->as_Vector()->length() == $1 &&
n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($2));
match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
format %{ "$5cmeq $dst, T$1$4, $src1, $src2\n\t# vector cmp ($1$2)"
"not $dst, T$6, $dst\t" %}
ins_cost(INSN_COST);
ins_encode %{
__ $5cmeq(as_FloatRegister($dst$$reg), __ T$1$4,
as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
__ notr(as_FloatRegister($dst$$reg), __ T$6, as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}')dnl
dnl $1 $2 $3 $4 $5 $6
VECTOR_CMP_NE(8, B, D, B, , 8B)
VECTOR_CMP_NE(16,B, X, B, , 16B)
VECTOR_CMP_NE(4, S, D, H, , 8B)
VECTOR_CMP_NE(8, S, X, H, , 16B)
VECTOR_CMP_NE(2, I, D, S, , 8B)
VECTOR_CMP_NE(4, I, X, S, , 16B)
VECTOR_CMP_NE(2, L, X, D, , 16B)
VECTOR_CMP_NE(2, F, D, S, f, 8B)
VECTOR_CMP_NE(4, F, X, S, f, 16B)
VECTOR_CMP_NE(2, D, X, D, f, 16B)
dnl
define(`VECTOR_CMP_LT_LE', `
instruct vcm$1$2$3`'(vec$4 dst, vec$4 src1, vec$4 src2, immI cond)
%{
predicate(n->as_Vector()->length() == $2 &&
n->as_VectorMaskCmp()->get_predicate() == BoolTest::$1 &&
n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_`'TYPE2DATATYPE($3));
match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
format %{ "$6cm$7 $dst, T$2$5, $src2, $src1\t# vector cmp ($2$3)" %}
ins_cost(INSN_COST);
ins_encode %{
__ $6cm$7(as_FloatRegister($dst$$reg), __ T$2$5,
as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
%}
ins_pipe(vdop$8);
%}')dnl
dnl $1 $2 $3 $4 $5 $6 $7 $8
VECTOR_CMP_LT_LE(lt, 8, B, D, B, , gt, 64)
VECTOR_CMP_LT_LE(lt, 16,B, X, B, , gt, 128)
VECTOR_CMP_LT_LE(lt, 4, S, D, H, , gt, 64)
VECTOR_CMP_LT_LE(lt, 8, S, X, H, , gt, 128)
VECTOR_CMP_LT_LE(lt, 2, I, D, S, , gt, 64)
VECTOR_CMP_LT_LE(lt, 4, I, X, S, , gt, 128)
VECTOR_CMP_LT_LE(lt, 2, L, X, D, , gt, 128)
VECTOR_CMP_LT_LE(lt, 2, F, D, S, f, gt, 64)
VECTOR_CMP_LT_LE(lt, 4, F, X, S, f, gt, 128)
VECTOR_CMP_LT_LE(lt, 2, D, X, D, f, gt, 128)
VECTOR_CMP_LT_LE(le, 8, B, D, B, , ge, 64)
VECTOR_CMP_LT_LE(le, 16,B, X, B, , ge, 128)
VECTOR_CMP_LT_LE(le, 4, S, D, H, , ge, 64)
VECTOR_CMP_LT_LE(le, 8, S, X, H, , ge, 128)
VECTOR_CMP_LT_LE(le, 2, I, D, S, , ge, 64)
VECTOR_CMP_LT_LE(le, 4, I, X, S, , ge, 128)
VECTOR_CMP_LT_LE(le, 2, L, X, D, , ge, 128)
VECTOR_CMP_LT_LE(le, 2, F, D, S, f, ge, 64)
VECTOR_CMP_LT_LE(le, 4, F, X, S, f, ge, 128)
VECTOR_CMP_LT_LE(le, 2, D, X, D, f, ge, 128)
dnl
// ------------------------------ Vector mul -----------------------------------
instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
%{
predicate(n->as_Vector()->length() == 2);
match(Set dst (MulVL src1 src2));
ins_cost(INSN_COST);
effect(TEMP tmp1, TEMP tmp2);
format %{ "umov $tmp1, $src1, D, 0\n\t"
"umov $tmp2, $src2, D, 0\n\t"
"mul $tmp2, $tmp2, $tmp1\n\t"
"mov $dst, T2D, 0, $tmp2\t# insert into vector(2L)\n\t"
"umov $tmp1, $src1, D, 1\n\t"
"umov $tmp2, $src2, D, 1\n\t"
"mul $tmp2, $tmp2, $tmp1\n\t"
"mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)\n\t"
%}
ins_encode %{
__ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
__ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);