/
sharedRuntime_ppc.cpp
3743 lines (3169 loc) · 136 KB
/
sharedRuntime_ppc.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "code/debugInfoRec.hpp"
#include "code/compiledIC.hpp"
#include "code/icBuffer.hpp"
#include "code/vtableStubs.hpp"
#include "frame_ppc.hpp"
#include "compiler/oopMap.hpp"
#include "gc/shared/gcLocker.hpp"
#include "interpreter/interpreter.hpp"
#include "interpreter/interp_masm.hpp"
#include "memory/resourceArea.hpp"
#include "oops/compiledICHolder.hpp"
#include "oops/klass.inline.hpp"
#include "prims/methodHandles.hpp"
#include "runtime/continuation.hpp"
#include "runtime/continuationEntry.inline.hpp"
#include "runtime/jniHandles.hpp"
#include "runtime/os.inline.hpp"
#include "runtime/safepointMechanism.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/signature.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/vframeArray.hpp"
#include "utilities/align.hpp"
#include "utilities/macros.hpp"
#include "vmreg_ppc.inline.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
#endif
#ifdef COMPILER2
#include "opto/ad.hpp"
#include "opto/runtime.hpp"
#endif
#include <alloca.h>
#define __ masm->
#ifdef PRODUCT
#define BLOCK_COMMENT(str) // nothing
#else
#define BLOCK_COMMENT(str) __ block_comment(str)
#endif
#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
class RegisterSaver {
// Used for saving volatile registers.
public:
// Support different return pc locations.
enum ReturnPCLocation {
return_pc_is_lr,
return_pc_is_pre_saved,
return_pc_is_thread_saved_exception_pc
};
static OopMap* push_frame_reg_args_and_save_live_registers(MacroAssembler* masm,
int* out_frame_size_in_bytes,
bool generate_oop_map,
int return_pc_adjustment,
ReturnPCLocation return_pc_location,
bool save_vectors = false);
static void restore_live_registers_and_pop_frame(MacroAssembler* masm,
int frame_size_in_bytes,
bool restore_ctr,
bool save_vectors = false);
static void push_frame_and_save_argument_registers(MacroAssembler* masm,
Register r_temp,
int frame_size,
int total_args,
const VMRegPair *regs, const VMRegPair *regs2 = NULL);
static void restore_argument_registers_and_pop_frame(MacroAssembler*masm,
int frame_size,
int total_args,
const VMRegPair *regs, const VMRegPair *regs2 = NULL);
// During deoptimization only the result registers need to be restored
// all the other values have already been extracted.
static void restore_result_registers(MacroAssembler* masm, int frame_size_in_bytes);
// Constants and data structures:
typedef enum {
int_reg,
float_reg,
special_reg,
vs_reg
} RegisterType;
typedef enum {
reg_size = 8,
half_reg_size = reg_size / 2,
vs_reg_size = 16
} RegisterConstants;
typedef struct {
RegisterType reg_type;
int reg_num;
VMReg vmreg;
} LiveRegType;
};
#define RegisterSaver_LiveIntReg(regname) \
{ RegisterSaver::int_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveFloatReg(regname) \
{ RegisterSaver::float_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveSpecialReg(regname) \
{ RegisterSaver::special_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveVSReg(regname) \
{ RegisterSaver::vs_reg, regname->encoding(), regname->as_VMReg() }
static const RegisterSaver::LiveRegType RegisterSaver_LiveRegs[] = {
// Live registers which get spilled to the stack. Register
// positions in this array correspond directly to the stack layout.
//
// live special registers:
//
RegisterSaver_LiveSpecialReg(SR_CTR),
//
// live float registers:
//
RegisterSaver_LiveFloatReg( F0 ),
RegisterSaver_LiveFloatReg( F1 ),
RegisterSaver_LiveFloatReg( F2 ),
RegisterSaver_LiveFloatReg( F3 ),
RegisterSaver_LiveFloatReg( F4 ),
RegisterSaver_LiveFloatReg( F5 ),
RegisterSaver_LiveFloatReg( F6 ),
RegisterSaver_LiveFloatReg( F7 ),
RegisterSaver_LiveFloatReg( F8 ),
RegisterSaver_LiveFloatReg( F9 ),
RegisterSaver_LiveFloatReg( F10 ),
RegisterSaver_LiveFloatReg( F11 ),
RegisterSaver_LiveFloatReg( F12 ),
RegisterSaver_LiveFloatReg( F13 ),
RegisterSaver_LiveFloatReg( F14 ),
RegisterSaver_LiveFloatReg( F15 ),
RegisterSaver_LiveFloatReg( F16 ),
RegisterSaver_LiveFloatReg( F17 ),
RegisterSaver_LiveFloatReg( F18 ),
RegisterSaver_LiveFloatReg( F19 ),
RegisterSaver_LiveFloatReg( F20 ),
RegisterSaver_LiveFloatReg( F21 ),
RegisterSaver_LiveFloatReg( F22 ),
RegisterSaver_LiveFloatReg( F23 ),
RegisterSaver_LiveFloatReg( F24 ),
RegisterSaver_LiveFloatReg( F25 ),
RegisterSaver_LiveFloatReg( F26 ),
RegisterSaver_LiveFloatReg( F27 ),
RegisterSaver_LiveFloatReg( F28 ),
RegisterSaver_LiveFloatReg( F29 ),
RegisterSaver_LiveFloatReg( F30 ),
RegisterSaver_LiveFloatReg( F31 ),
//
// live integer registers:
//
RegisterSaver_LiveIntReg( R0 ),
//RegisterSaver_LiveIntReg( R1 ), // stack pointer
RegisterSaver_LiveIntReg( R2 ),
RegisterSaver_LiveIntReg( R3 ),
RegisterSaver_LiveIntReg( R4 ),
RegisterSaver_LiveIntReg( R5 ),
RegisterSaver_LiveIntReg( R6 ),
RegisterSaver_LiveIntReg( R7 ),
RegisterSaver_LiveIntReg( R8 ),
RegisterSaver_LiveIntReg( R9 ),
RegisterSaver_LiveIntReg( R10 ),
RegisterSaver_LiveIntReg( R11 ),
RegisterSaver_LiveIntReg( R12 ),
//RegisterSaver_LiveIntReg( R13 ), // system thread id
RegisterSaver_LiveIntReg( R14 ),
RegisterSaver_LiveIntReg( R15 ),
RegisterSaver_LiveIntReg( R16 ),
RegisterSaver_LiveIntReg( R17 ),
RegisterSaver_LiveIntReg( R18 ),
RegisterSaver_LiveIntReg( R19 ),
RegisterSaver_LiveIntReg( R20 ),
RegisterSaver_LiveIntReg( R21 ),
RegisterSaver_LiveIntReg( R22 ),
RegisterSaver_LiveIntReg( R23 ),
RegisterSaver_LiveIntReg( R24 ),
RegisterSaver_LiveIntReg( R25 ),
RegisterSaver_LiveIntReg( R26 ),
RegisterSaver_LiveIntReg( R27 ),
RegisterSaver_LiveIntReg( R28 ),
RegisterSaver_LiveIntReg( R29 ),
RegisterSaver_LiveIntReg( R30 ),
RegisterSaver_LiveIntReg( R31 ) // must be the last register (see save/restore functions below)
};
static const RegisterSaver::LiveRegType RegisterSaver_LiveVSRegs[] = {
//
// live vector scalar registers (optional, only these ones are used by C2):
//
RegisterSaver_LiveVSReg( VSR32 ),
RegisterSaver_LiveVSReg( VSR33 ),
RegisterSaver_LiveVSReg( VSR34 ),
RegisterSaver_LiveVSReg( VSR35 ),
RegisterSaver_LiveVSReg( VSR36 ),
RegisterSaver_LiveVSReg( VSR37 ),
RegisterSaver_LiveVSReg( VSR38 ),
RegisterSaver_LiveVSReg( VSR39 ),
RegisterSaver_LiveVSReg( VSR40 ),
RegisterSaver_LiveVSReg( VSR41 ),
RegisterSaver_LiveVSReg( VSR42 ),
RegisterSaver_LiveVSReg( VSR43 ),
RegisterSaver_LiveVSReg( VSR44 ),
RegisterSaver_LiveVSReg( VSR45 ),
RegisterSaver_LiveVSReg( VSR46 ),
RegisterSaver_LiveVSReg( VSR47 ),
RegisterSaver_LiveVSReg( VSR48 ),
RegisterSaver_LiveVSReg( VSR49 ),
RegisterSaver_LiveVSReg( VSR50 ),
RegisterSaver_LiveVSReg( VSR51 )
};
OopMap* RegisterSaver::push_frame_reg_args_and_save_live_registers(MacroAssembler* masm,
int* out_frame_size_in_bytes,
bool generate_oop_map,
int return_pc_adjustment,
ReturnPCLocation return_pc_location,
bool save_vectors) {
// Push an abi_reg_args-frame and store all registers which may be live.
// If requested, create an OopMap: Record volatile registers as
// callee-save values in an OopMap so their save locations will be
// propagated to the RegisterMap of the caller frame during
// StackFrameStream construction (needed for deoptimization; see
// compiledVFrame::create_stack_value).
// If return_pc_adjustment != 0 adjust the return pc by return_pc_adjustment.
// Updated return pc is returned in R31 (if not return_pc_is_pre_saved).
// calculate frame size
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) /
sizeof(RegisterSaver::LiveRegType))
: 0;
const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size;
const int frame_size_in_bytes = align_up(register_save_size, frame::alignment_in_bytes)
+ frame::abi_reg_args_size;
*out_frame_size_in_bytes = frame_size_in_bytes;
const int frame_size_in_slots = frame_size_in_bytes / sizeof(jint);
const int register_save_offset = frame_size_in_bytes - register_save_size;
// OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words.
OopMap* map = generate_oop_map ? new OopMap(frame_size_in_slots, 0) : NULL;
BLOCK_COMMENT("push_frame_reg_args_and_save_live_registers {");
// push a new frame
__ push_frame(frame_size_in_bytes, noreg);
// Save some registers in the last (non-vector) slots of the new frame so we
// can use them as scratch regs or to determine the return pc.
__ std(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP);
__ std(R30, frame_size_in_bytes - 2*reg_size - vsregstosave_num * vs_reg_size, R1_SP);
// save the flags
// Do the save_LR_CR by hand and adjust the return pc if requested.
__ mfcr(R30);
__ std(R30, frame_size_in_bytes + _abi0(cr), R1_SP);
switch (return_pc_location) {
case return_pc_is_lr: __ mflr(R31); break;
case return_pc_is_pre_saved: assert(return_pc_adjustment == 0, "unsupported"); break;
case return_pc_is_thread_saved_exception_pc: __ ld(R31, thread_(saved_exception_pc)); break;
default: ShouldNotReachHere();
}
if (return_pc_location != return_pc_is_pre_saved) {
if (return_pc_adjustment != 0) {
__ addi(R31, R31, return_pc_adjustment);
}
__ std(R31, frame_size_in_bytes + _abi0(lr), R1_SP);
}
// save all registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (reg_num < 30) { // We spilled R30-31 right at the beginning.
__ std(as_Register(reg_num), offset, R1_SP);
}
break;
}
case RegisterSaver::float_reg: {
__ stfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
if (reg_num == SR_CTR.encoding()) {
__ mfctr(R30);
__ std(R30, offset, R1_SP);
} else {
Unimplemented();
}
break;
}
default:
ShouldNotReachHere();
}
if (generate_oop_map) {
map->set_callee_saved(VMRegImpl::stack2reg(offset>>2),
RegisterSaver_LiveRegs[i].vmreg);
map->set_callee_saved(VMRegImpl::stack2reg((offset + half_reg_size)>>2),
RegisterSaver_LiveRegs[i].vmreg->next());
}
offset += reg_size;
}
for (int i = 0; i < vsregstosave_num; i++) {
int reg_num = RegisterSaver_LiveVSRegs[i].reg_num;
int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
__ li(R30, offset);
__ stxvd2x(as_VectorSRegister(reg_num), R30, R1_SP);
if (generate_oop_map) {
map->set_callee_saved(VMRegImpl::stack2reg(offset>>2),
RegisterSaver_LiveVSRegs[i].vmreg);
}
offset += vs_reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
BLOCK_COMMENT("} push_frame_reg_args_and_save_live_registers");
// And we're done.
return map;
}
// Pop the current frame and restore all the registers that we
// saved.
void RegisterSaver::restore_live_registers_and_pop_frame(MacroAssembler* masm,
int frame_size_in_bytes,
bool restore_ctr,
bool save_vectors) {
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) /
sizeof(RegisterSaver::LiveRegType))
: 0;
const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size;
const int register_save_offset = frame_size_in_bytes - register_save_size;
BLOCK_COMMENT("restore_live_registers_and_pop_frame {");
// restore all registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (reg_num != 31) // R31 restored at the end, it's the tmp reg!
__ ld(as_Register(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::float_reg: {
__ lfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
if (reg_num == SR_CTR.encoding()) {
if (restore_ctr) { // Nothing to do here if ctr already contains the next address.
__ ld(R31, offset, R1_SP);
__ mtctr(R31);
}
} else {
Unimplemented();
}
break;
}
default:
ShouldNotReachHere();
}
offset += reg_size;
}
for (int i = 0; i < vsregstosave_num; i++) {
int reg_num = RegisterSaver_LiveVSRegs[i].reg_num;
int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
__ li(R31, offset);
__ lxvd2x(as_VectorSRegister(reg_num), R31, R1_SP);
offset += vs_reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
// restore link and the flags
__ ld(R31, frame_size_in_bytes + _abi0(lr), R1_SP);
__ mtlr(R31);
__ ld(R31, frame_size_in_bytes + _abi0(cr), R1_SP);
__ mtcr(R31);
// restore scratch register's value
__ ld(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP);
// pop the frame
__ addi(R1_SP, R1_SP, frame_size_in_bytes);
BLOCK_COMMENT("} restore_live_registers_and_pop_frame");
}
void RegisterSaver::push_frame_and_save_argument_registers(MacroAssembler* masm, Register r_temp,
int frame_size,int total_args, const VMRegPair *regs,
const VMRegPair *regs2) {
__ push_frame(frame_size, r_temp);
int st_off = frame_size - wordSize;
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "");
continue;
}
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ std(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ stfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
if (regs2 != NULL) {
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs2[i].first();
VMReg r_2 = regs2[i].second();
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "");
continue;
}
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ std(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ stfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
}
}
void RegisterSaver::restore_argument_registers_and_pop_frame(MacroAssembler*masm, int frame_size,
int total_args, const VMRegPair *regs,
const VMRegPair *regs2) {
int st_off = frame_size - wordSize;
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ ld(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ lfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
if (regs2 != NULL)
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs2[i].first();
VMReg r_2 = regs2[i].second();
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ ld(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ lfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
__ pop_frame();
}
// Restore the registers that might be holding a result.
void RegisterSaver::restore_result_registers(MacroAssembler* masm, int frame_size_in_bytes) {
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int register_save_size = regstosave_num * reg_size; // VS registers not relevant here.
const int register_save_offset = frame_size_in_bytes - register_save_size;
// restore all result registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (as_Register(reg_num)==R3_RET) // int result_reg
__ ld(as_Register(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::float_reg: {
if (as_FloatRegister(reg_num)==F1_RET) // float result_reg
__ lfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
// Special registers don't hold a result.
break;
}
default:
ShouldNotReachHere();
}
offset += reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
}
// Is vector's size (in bytes) bigger than a size saved by default?
bool SharedRuntime::is_wide_vector(int size) {
// Note, MaxVectorSize == 8/16 on PPC64.
assert(size <= (SuperwordUseVSX ? 16 : 8), "%d bytes vectors are not supported", size);
return size > 8;
}
static int reg2slot(VMReg r) {
return r->reg2stack() + SharedRuntime::out_preserve_stack_slots();
}
static int reg2offset(VMReg r) {
return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
}
// ---------------------------------------------------------------------------
// Read the array of BasicTypes from a signature, and compute where the
// arguments should go. Values in the VMRegPair regs array refer to 4-byte
// quantities. Values less than VMRegImpl::stack0 are registers, those above
// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
// as framesizes are fixed.
// VMRegImpl::stack0 refers to the first slot 0(sp).
// and VMRegImpl::stack0+1 refers to the memory word 4-bytes higher. Register
// up to Register::number_of_registers) are the 64-bit
// integer registers.
// Note: the INPUTS in sig_bt are in units of Java argument words, which are
// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
// units regardless of build. Of course for i486 there is no 64 bit build
// The Java calling convention is a "shifted" version of the C ABI.
// By skipping the first C ABI register we can call non-static jni methods
// with small numbers of arguments without having to shuffle the arguments
// at all. Since we control the java ABI we ought to at least get some
// advantage out of it.
const VMReg java_iarg_reg[8] = {
R3->as_VMReg(),
R4->as_VMReg(),
R5->as_VMReg(),
R6->as_VMReg(),
R7->as_VMReg(),
R8->as_VMReg(),
R9->as_VMReg(),
R10->as_VMReg()
};
const VMReg java_farg_reg[13] = {
F1->as_VMReg(),
F2->as_VMReg(),
F3->as_VMReg(),
F4->as_VMReg(),
F5->as_VMReg(),
F6->as_VMReg(),
F7->as_VMReg(),
F8->as_VMReg(),
F9->as_VMReg(),
F10->as_VMReg(),
F11->as_VMReg(),
F12->as_VMReg(),
F13->as_VMReg()
};
const int num_java_iarg_registers = sizeof(java_iarg_reg) / sizeof(java_iarg_reg[0]);
const int num_java_farg_registers = sizeof(java_farg_reg) / sizeof(java_farg_reg[0]);
STATIC_ASSERT(num_java_iarg_registers == Argument::n_int_register_parameters_j);
STATIC_ASSERT(num_java_farg_registers == Argument::n_float_register_parameters_j);
int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
int total_args_passed) {
// C2c calling conventions for compiled-compiled calls.
// Put 8 ints/longs into registers _AND_ 13 float/doubles into
// registers _AND_ put the rest on the stack.
const int inc_stk_for_intfloat = 1; // 1 slots for ints and floats
const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles
int i;
VMReg reg;
int stk = 0;
int ireg = 0;
int freg = 0;
// We put the first 8 arguments into registers and the rest on the
// stack, float arguments are already in their argument registers
// due to c2c calling conventions (see calling_convention).
for (int i = 0; i < total_args_passed; ++i) {
switch(sig_bt[i]) {
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
if (ireg < num_java_iarg_registers) {
// Put int/ptr in register
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put int/ptr on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (ireg < num_java_iarg_registers) {
// Put long in register.
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put long on stack. They must be aligned to 2 slots.
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
if (ireg < num_java_iarg_registers) {
// Put ptr in register.
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put ptr on stack. Objects must be aligned to 2 slots too,
// because "64-bit pointers record oop-ishness on 2 aligned
// adjacent registers." (see OopFlow::build_oop_map).
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_FLOAT:
if (freg < num_java_farg_registers) {
// Put float in register.
reg = java_farg_reg[freg];
++freg;
} else {
// Put float on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (freg < num_java_farg_registers) {
// Put double in register.
reg = java_farg_reg[freg];
++freg;
} else {
// Put double on stack. They must be aligned to 2 slots.
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_VOID:
// Do not count halves.
regs[i].set_bad();
break;
default:
ShouldNotReachHere();
}
}
return align_up(stk, 2);
}
#if defined(COMPILER1) || defined(COMPILER2)
// Calling convention for calling C code.
int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
VMRegPair *regs2,
int total_args_passed) {
// Calling conventions for C runtime calls and calls to JNI native methods.
//
// PPC64 convention: Hoist the first 8 int/ptr/long's in the first 8
// int regs, leaving int regs undefined if the arg is flt/dbl. Hoist
// the first 13 flt/dbl's in the first 13 fp regs but additionally
// copy flt/dbl to the stack if they are beyond the 8th argument.
const VMReg iarg_reg[8] = {
R3->as_VMReg(),
R4->as_VMReg(),
R5->as_VMReg(),
R6->as_VMReg(),
R7->as_VMReg(),
R8->as_VMReg(),
R9->as_VMReg(),
R10->as_VMReg()
};
const VMReg farg_reg[13] = {
F1->as_VMReg(),
F2->as_VMReg(),
F3->as_VMReg(),
F4->as_VMReg(),
F5->as_VMReg(),
F6->as_VMReg(),
F7->as_VMReg(),
F8->as_VMReg(),
F9->as_VMReg(),
F10->as_VMReg(),
F11->as_VMReg(),
F12->as_VMReg(),
F13->as_VMReg()
};
// Check calling conventions consistency.
assert(sizeof(iarg_reg) / sizeof(iarg_reg[0]) == Argument::n_int_register_parameters_c &&
sizeof(farg_reg) / sizeof(farg_reg[0]) == Argument::n_float_register_parameters_c,
"consistency");
// `Stk' counts stack slots. Due to alignment, 32 bit values occupy
// 2 such slots, like 64 bit values do.
const int inc_stk_for_intfloat = 2; // 2 slots for ints and floats
const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles
int i;
VMReg reg;
// Leave room for C-compatible ABI_REG_ARGS.
int stk = (frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size;
int arg = 0;
int freg = 0;
// Avoid passing C arguments in the wrong stack slots.
#if defined(ABI_ELFv2)
assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_size == 96,
"passing C arguments in wrong stack slots");
#else
assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_size == 112,
"passing C arguments in wrong stack slots");
#endif
// We fill-out regs AND regs2 if an argument must be passed in a
// register AND in a stack slot. If regs2 is NULL in such a
// situation, we bail-out with a fatal error.
for (int i = 0; i < total_args_passed; ++i, ++arg) {
// Initialize regs2 to BAD.
if (regs2 != NULL) regs2[i].set_bad();
switch(sig_bt[i]) {
//
// If arguments 0-7 are integers, they are passed in integer registers.
// Argument i is placed in iarg_reg[i].
//
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
// We must cast ints to longs and use full 64 bit stack slots
// here. Thus fall through, handle as long.
case T_LONG:
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
case T_METADATA:
// Oops are already boxed if required (JNI).
if (arg < Argument::n_int_register_parameters_c) {
reg = iarg_reg[arg];
} else {
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
//
// Floats are treated differently from int regs: The first 13 float arguments
// are passed in registers (not the float args among the first 13 args).
// Thus argument i is NOT passed in farg_reg[i] if it is float. It is passed
// in farg_reg[j] if argument i is the j-th float argument of this call.
//
case T_FLOAT:
#if defined(LINUX)
// Linux uses ELF ABI. Both original ELF and ELFv2 ABIs have float
// in the least significant word of an argument slot.
#if defined(VM_LITTLE_ENDIAN)
#define FLOAT_WORD_OFFSET_IN_SLOT 0
#else
#define FLOAT_WORD_OFFSET_IN_SLOT 1
#endif
#elif defined(AIX)
// Although AIX runs on big endian CPU, float is in the most
// significant word of an argument slot.
#define FLOAT_WORD_OFFSET_IN_SLOT 0
#else
#error "unknown OS"
#endif
if (freg < Argument::n_float_register_parameters_c) {
// Put float in register ...
reg = farg_reg[freg];
++freg;
// Argument i for i > 8 is placed on the stack even if it's
// placed in a register (if it's a float arg). Aix disassembly
// shows that xlC places these float args on the stack AND in
// a register. This is not documented, but we follow this
// convention, too.
if (arg >= Argument::n_regs_not_on_stack_c) {
// ... and on the stack.
guarantee(regs2 != NULL, "must pass float in register and stack slot");
VMReg reg2 = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT);
regs2[i].set1(reg2);
stk += inc_stk_for_intfloat;
}
} else {
// Put float on stack.
reg = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (freg < Argument::n_float_register_parameters_c) {
// Put double in register ...
reg = farg_reg[freg];
++freg;
// Argument i for i > 8 is placed on the stack even if it's
// placed in a register (if it's a double arg). Aix disassembly
// shows that xlC places these float args on the stack AND in
// a register. This is not documented, but we follow this
// convention, too.
if (arg >= Argument::n_regs_not_on_stack_c) {
// ... and on the stack.
guarantee(regs2 != NULL, "must pass float in register and stack slot");
VMReg reg2 = VMRegImpl::stack2reg(stk);
regs2[i].set2(reg2);
stk += inc_stk_for_longdouble;
}
} else {
// Put double on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_VOID:
// Do not count halves.
regs[i].set_bad();
--arg;
break;
default:
ShouldNotReachHere();
}
}
return align_up(stk, 2);
}
#endif // COMPILER2
int SharedRuntime::vector_calling_convention(VMRegPair *regs,
uint num_bits,
uint total_args_passed) {
Unimplemented();
return 0;
}
static address gen_c2i_adapter(MacroAssembler *masm,
int total_args_passed,
int comp_args_on_stack,
const BasicType *sig_bt,
const VMRegPair *regs,
Label& call_interpreter,
const Register& ientry) {
address c2i_entrypoint;
const Register sender_SP = R21_sender_SP; // == R21_tmp1
const Register code = R22_tmp2;
//const Register ientry = R23_tmp3;
const Register value_regs[] = { R24_tmp4, R25_tmp5, R26_tmp6 };
const int num_value_regs = sizeof(value_regs) / sizeof(Register);
int value_regs_index = 0;
const Register return_pc = R27_tmp7;
const Register tmp = R28_tmp8;
assert_different_registers(sender_SP, code, ientry, return_pc, tmp);
// Adapter needs TOP_IJAVA_FRAME_ABI.
const int adapter_size = frame::top_ijava_frame_abi_size +
align_up(total_args_passed * wordSize, frame::alignment_in_bytes);
// regular (verified) c2i entry point
c2i_entrypoint = __ pc();
// Does compiled code exists? If yes, patch the caller's callsite.
__ ld(code, method_(code));
__ cmpdi(CCR0, code, 0);
__ ld(ientry, method_(interpreter_entry)); // preloaded
__ beq(CCR0, call_interpreter);
// Patch caller's callsite, method_(code) was not NULL which means that
// compiled code exists.
__ mflr(return_pc);
__ std(return_pc, _abi0(lr), R1_SP);
RegisterSaver::push_frame_and_save_argument_registers(masm, tmp, adapter_size, total_args_passed, regs);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), R19_method, return_pc);
RegisterSaver::restore_argument_registers_and_pop_frame(masm, adapter_size, total_args_passed, regs);
__ ld(return_pc, _abi0(lr), R1_SP);
__ ld(ientry, method_(interpreter_entry)); // preloaded
__ mtlr(return_pc);
// Call the interpreter.
__ BIND(call_interpreter);
__ mtctr(ientry);
// Get a copy of the current SP for loading caller's arguments.
__ mr(sender_SP, R1_SP);
// Add space for the adapter.
__ resize_frame(-adapter_size, R12_scratch2);
int st_off = adapter_size - wordSize;
// Write the args into the outgoing interpreter space.
for (int i = 0; i < total_args_passed; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();