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c1_LIRAssembler_arm.cpp
2854 lines (2495 loc) · 100 KB
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c1_LIRAssembler_arm.cpp
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/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_LIRAssembler.hpp"
#include "c1/c1_MacroAssembler.hpp"
#include "c1/c1_Runtime1.hpp"
#include "c1/c1_ValueStack.hpp"
#include "ci/ciArrayKlass.hpp"
#include "ci/ciInstance.hpp"
#include "gc/shared/collectedHeap.hpp"
#include "memory/universe.hpp"
#include "nativeInst_arm.hpp"
#include "oops/objArrayKlass.hpp"
#include "runtime/frame.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "utilities/powerOfTwo.hpp"
#include "vmreg_arm.inline.hpp"
#define __ _masm->
// Note: Rtemp usage is this file should not impact C2 and should be
// correct as long as it is not implicitly used in lower layers (the
// arm [macro]assembler) and used with care in the other C1 specific
// files.
bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
ShouldNotCallThis(); // Not used on ARM
return false;
}
LIR_Opr LIR_Assembler::receiverOpr() {
// The first register in Java calling conventions
return FrameMap::R0_oop_opr;
}
LIR_Opr LIR_Assembler::osrBufferPointer() {
return FrameMap::as_pointer_opr(R0);
}
#ifndef PRODUCT
void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
}
#endif // !PRODUCT
void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
__ mov_slow(Rtemp, c);
__ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
}
void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
__ mov_metadata(Rtemp, m);
__ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
}
//--------------fpu register translations-----------------------
void LIR_Assembler::breakpoint() {
__ breakpoint();
}
void LIR_Assembler::push(LIR_Opr opr) {
Unimplemented();
}
void LIR_Assembler::pop(LIR_Opr opr) {
Unimplemented();
}
//-------------------------------------------
Address LIR_Assembler::as_Address(LIR_Address* addr) {
Register base = addr->base()->as_pointer_register();
if (addr->index()->is_illegal() || addr->index()->is_constant()) {
int offset = addr->disp();
if (addr->index()->is_constant()) {
offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
}
if ((offset <= -4096) || (offset >= 4096)) {
BAILOUT_("offset not in range", Address(base));
}
return Address(base, offset);
} else {
assert(addr->disp() == 0, "can't have both");
int scale = addr->scale();
assert(addr->index()->is_single_cpu(), "should be");
return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
Address(base, addr->index()->as_register(), lsr, -scale);
}
}
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
Address base = as_Address(addr);
assert(base.index() == noreg, "must be");
if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
return Address(base.base(), base.disp() + BytesPerWord);
}
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
return as_Address(addr);
}
void LIR_Assembler::osr_entry() {
offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
BlockBegin* osr_entry = compilation()->hir()->osr_entry();
ValueStack* entry_state = osr_entry->end()->state();
int number_of_locks = entry_state->locks_size();
__ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
Register OSR_buf = osrBufferPointer()->as_pointer_register();
assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
for (int i = 0; i < number_of_locks; i++) {
int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
__ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
__ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
__ str(R1, frame_map()->address_for_monitor_lock(i));
__ str(R2, frame_map()->address_for_monitor_object(i));
}
}
int LIR_Assembler::check_icache() {
Register receiver = LIR_Assembler::receiverOpr()->as_register();
int offset = __ offset();
__ inline_cache_check(receiver, Ricklass);
return offset;
}
void LIR_Assembler::clinit_barrier(ciMethod* method) {
ShouldNotReachHere(); // not implemented
}
void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
jobject o = (jobject)Universe::non_oop_word();
int index = __ oop_recorder()->allocate_oop_index(o);
PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
__ patchable_mov_oop(reg, o, index);
patching_epilog(patch, lir_patch_normal, reg, info);
}
void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
Metadata* o = (Metadata*)Universe::non_oop_word();
int index = __ oop_recorder()->allocate_metadata_index(o);
PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
__ patchable_mov_metadata(reg, o, index);
patching_epilog(patch, lir_patch_normal, reg, info);
}
int LIR_Assembler::initial_frame_size_in_bytes() const {
// Subtracts two words to account for return address and link
return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
}
int LIR_Assembler::emit_exception_handler() {
// TODO: ARM
__ nop(); // See comments in other ports
address handler_base = __ start_a_stub(exception_handler_size());
if (handler_base == NULL) {
bailout("exception handler overflow");
return -1;
}
int offset = code_offset();
// check that there is really an exception
__ verify_not_null_oop(Rexception_obj);
__ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
__ should_not_reach_here();
assert(code_offset() - offset <= exception_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
// Emit the code to remove the frame from the stack in the exception
// unwind path.
int LIR_Assembler::emit_unwind_handler() {
#ifndef PRODUCT
if (CommentedAssembly) {
_masm->block_comment("Unwind handler");
}
#endif
int offset = code_offset();
// Fetch the exception from TLS and clear out exception related thread state
Register zero = __ zero_register(Rtemp);
__ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
__ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
__ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
__ bind(_unwind_handler_entry);
__ verify_not_null_oop(Rexception_obj);
// Preform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::R0_opr);
stub = new MonitorExitStub(FrameMap::R0_opr, true, 0);
__ unlock_object(R2, R1, R0, *stub->entry());
__ bind(*stub->continuation());
}
// remove the activation and dispatch to the unwind handler
__ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
__ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
// Emit the slow path assembly
if (stub != NULL) {
stub->emit_code(this);
}
return offset;
}
int LIR_Assembler::emit_deopt_handler() {
address handler_base = __ start_a_stub(deopt_handler_size());
if (handler_base == NULL) {
bailout("deopt handler overflow");
return -1;
}
int offset = code_offset();
__ mov_relative_address(LR, __ pc());
__ push(LR); // stub expects LR to be saved
__ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
assert(code_offset() - offset <= deopt_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
// Pop the frame before safepoint polling
__ remove_frame(initial_frame_size_in_bytes());
__ read_polling_page(Rtemp, relocInfo::poll_return_type);
__ ret();
}
int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
int offset = __ offset();
__ get_polling_page(Rtemp);
__ relocate(relocInfo::poll_type);
add_debug_info_for_branch(info); // help pc_desc_at to find correct scope for current PC
__ ldr(Rtemp, Address(Rtemp));
return offset;
}
void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
if (from_reg != to_reg) {
__ mov(to_reg, from_reg);
}
}
void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
assert(src->is_constant() && dest->is_register(), "must be");
LIR_Const* c = src->as_constant_ptr();
switch (c->type()) {
case T_ADDRESS:
case T_INT:
assert(patch_code == lir_patch_none, "no patching handled here");
__ mov_slow(dest->as_register(), c->as_jint());
break;
case T_LONG:
assert(patch_code == lir_patch_none, "no patching handled here");
__ mov_slow(dest->as_register_lo(), c->as_jint_lo());
__ mov_slow(dest->as_register_hi(), c->as_jint_hi());
break;
case T_OBJECT:
if (patch_code == lir_patch_none) {
__ mov_oop(dest->as_register(), c->as_jobject());
} else {
jobject2reg_with_patching(dest->as_register(), info);
}
break;
case T_METADATA:
if (patch_code == lir_patch_none) {
__ mov_metadata(dest->as_register(), c->as_metadata());
} else {
klass2reg_with_patching(dest->as_register(), info);
}
break;
case T_FLOAT:
if (dest->is_single_fpu()) {
__ mov_float(dest->as_float_reg(), c->as_jfloat());
} else {
// Simple getters can return float constant directly into r0
__ mov_slow(dest->as_register(), c->as_jint_bits());
}
break;
case T_DOUBLE:
if (dest->is_double_fpu()) {
__ mov_double(dest->as_double_reg(), c->as_jdouble());
} else {
// Simple getters can return double constant directly into r1r0
__ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
__ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
}
break;
default:
ShouldNotReachHere();
}
}
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
assert(src->is_constant(), "must be");
assert(dest->is_stack(), "must be");
LIR_Const* c = src->as_constant_ptr();
switch (c->type()) {
case T_INT: // fall through
case T_FLOAT:
__ mov_slow(Rtemp, c->as_jint_bits());
__ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
break;
case T_ADDRESS:
__ mov_slow(Rtemp, c->as_jint());
__ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
break;
case T_OBJECT:
__ mov_oop(Rtemp, c->as_jobject());
__ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
break;
case T_LONG: // fall through
case T_DOUBLE:
__ mov_slow(Rtemp, c->as_jint_lo_bits());
__ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
__ mov_slow(Rtemp, c->as_jint_hi_bits());
}
__ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
break;
default:
ShouldNotReachHere();
}
}
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
CodeEmitInfo* info, bool wide) {
assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
__ mov(Rtemp, 0);
int null_check_offset = code_offset();
__ str(Rtemp, as_Address(dest->as_address_ptr()));
if (info != NULL) {
assert(false, "arm32 didn't support this before, investigate if bug");
add_debug_info_for_null_check(null_check_offset, info);
}
}
void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
assert(src->is_register() && dest->is_register(), "must be");
if (src->is_single_cpu()) {
if (dest->is_single_cpu()) {
move_regs(src->as_register(), dest->as_register());
} else if (dest->is_single_fpu()) {
__ fmsr(dest->as_float_reg(), src->as_register());
} else {
ShouldNotReachHere();
}
} else if (src->is_double_cpu()) {
if (dest->is_double_cpu()) {
__ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
} else {
__ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
}
} else if (src->is_single_fpu()) {
if (dest->is_single_fpu()) {
__ mov_float(dest->as_float_reg(), src->as_float_reg());
} else if (dest->is_single_cpu()) {
__ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
} else {
ShouldNotReachHere();
}
} else if (src->is_double_fpu()) {
if (dest->is_double_fpu()) {
__ mov_double(dest->as_double_reg(), src->as_double_reg());
} else if (dest->is_double_cpu()) {
__ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
} else {
ShouldNotReachHere();
}
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
assert(src->is_register(), "should not call otherwise");
assert(dest->is_stack(), "should not call otherwise");
Address addr = dest->is_single_word() ?
frame_map()->address_for_slot(dest->single_stack_ix()) :
frame_map()->address_for_slot(dest->double_stack_ix());
assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
if (src->is_single_fpu() || src->is_double_fpu()) {
if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
}
if (src->is_single_cpu()) {
switch (type) {
case T_OBJECT:
case T_ARRAY: __ verify_oop(src->as_register()); // fall through
case T_ADDRESS:
case T_METADATA: __ str(src->as_register(), addr); break;
case T_FLOAT: // used in intBitsToFloat intrinsic implementation, fall through
case T_INT: __ str_32(src->as_register(), addr); break;
default:
ShouldNotReachHere();
}
} else if (src->is_double_cpu()) {
__ str(src->as_register_lo(), addr);
__ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
} else if (src->is_single_fpu()) {
__ str_float(src->as_float_reg(), addr);
} else if (src->is_double_fpu()) {
__ str_double(src->as_double_reg(), addr);
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
LIR_PatchCode patch_code, CodeEmitInfo* info,
bool pop_fpu_stack, bool wide) {
LIR_Address* to_addr = dest->as_address_ptr();
Register base_reg = to_addr->base()->as_pointer_register();
const bool needs_patching = (patch_code != lir_patch_none);
PatchingStub* patch = NULL;
if (needs_patching) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
}
int null_check_offset = code_offset();
switch (type) {
case T_ARRAY:
case T_OBJECT:
if (UseCompressedOops && !wide) {
ShouldNotReachHere();
} else {
__ str(src->as_register(), as_Address(to_addr));
}
break;
case T_ADDRESS:
__ str(src->as_pointer_register(), as_Address(to_addr));
break;
case T_BYTE:
case T_BOOLEAN:
__ strb(src->as_register(), as_Address(to_addr));
break;
case T_CHAR:
case T_SHORT:
__ strh(src->as_register(), as_Address(to_addr));
break;
case T_INT:
#ifdef __SOFTFP__
case T_FLOAT:
#endif // __SOFTFP__
__ str_32(src->as_register(), as_Address(to_addr));
break;
#ifdef __SOFTFP__
case T_DOUBLE:
#endif // __SOFTFP__
case T_LONG: {
Register from_lo = src->as_register_lo();
Register from_hi = src->as_register_hi();
if (to_addr->index()->is_register()) {
assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
assert(to_addr->disp() == 0, "Not yet supporting both");
__ add(Rtemp, base_reg, to_addr->index()->as_register());
base_reg = Rtemp;
__ str(from_lo, Address(Rtemp));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd str
patching_epilog(patch, lir_patch_low, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_high;
}
__ str(from_hi, Address(Rtemp, BytesPerWord));
} else if (base_reg == from_lo) {
__ str(from_hi, as_Address_hi(to_addr));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd str
patching_epilog(patch, lir_patch_high, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_low;
}
__ str(from_lo, as_Address_lo(to_addr));
} else {
__ str(from_lo, as_Address_lo(to_addr));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd str
patching_epilog(patch, lir_patch_low, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_high;
}
__ str(from_hi, as_Address_hi(to_addr));
}
break;
}
#ifndef __SOFTFP__
case T_FLOAT:
if (to_addr->index()->is_register()) {
assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
__ add(Rtemp, base_reg, to_addr->index()->as_register());
if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
__ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
} else {
__ fsts(src->as_float_reg(), as_Address(to_addr));
}
break;
case T_DOUBLE:
if (to_addr->index()->is_register()) {
assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
__ add(Rtemp, base_reg, to_addr->index()->as_register());
if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
__ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
} else {
__ fstd(src->as_double_reg(), as_Address(to_addr));
}
break;
#endif // __SOFTFP__
default:
ShouldNotReachHere();
}
if (info != NULL) {
add_debug_info_for_null_check(null_check_offset, info);
}
if (patch != NULL) {
// Offset embedded into LDR/STR instruction may appear not enough
// to address a field. So, provide a space for one more instruction
// that will deal with larger offsets.
__ nop();
patching_epilog(patch, patch_code, base_reg, info);
}
}
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
assert(src->is_stack(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
Address addr = src->is_single_word() ?
frame_map()->address_for_slot(src->single_stack_ix()) :
frame_map()->address_for_slot(src->double_stack_ix());
assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
if (dest->is_single_fpu() || dest->is_double_fpu()) {
if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
}
if (dest->is_single_cpu()) {
switch (type) {
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
case T_METADATA: __ ldr(dest->as_register(), addr); break;
case T_FLOAT: // used in floatToRawIntBits intrinsic implemenation
case T_INT: __ ldr_u32(dest->as_register(), addr); break;
default:
ShouldNotReachHere();
}
if ((type == T_OBJECT) || (type == T_ARRAY)) {
__ verify_oop(dest->as_register());
}
} else if (dest->is_double_cpu()) {
__ ldr(dest->as_register_lo(), addr);
__ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
} else if (dest->is_single_fpu()) {
__ ldr_float(dest->as_float_reg(), addr);
} else if (dest->is_double_fpu()) {
__ ldr_double(dest->as_double_reg(), addr);
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
if (src->is_single_stack()) {
switch (src->type()) {
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
case T_METADATA:
__ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
__ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
break;
case T_INT:
case T_FLOAT:
__ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
__ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
break;
default:
ShouldNotReachHere();
}
} else {
assert(src->is_double_stack(), "must be");
__ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
__ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
__ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
__ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
}
}
void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
LIR_PatchCode patch_code, CodeEmitInfo* info,
bool wide) {
assert(src->is_address(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
LIR_Address* addr = src->as_address_ptr();
Register base_reg = addr->base()->as_pointer_register();
PatchingStub* patch = NULL;
if (patch_code != lir_patch_none) {
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
}
switch (type) {
case T_OBJECT: // fall through
case T_ARRAY:
if (UseCompressedOops && !wide) {
__ ldr_u32(dest->as_register(), as_Address(addr));
} else {
__ ldr(dest->as_register(), as_Address(addr));
}
break;
case T_ADDRESS:
if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
__ ldr_u32(dest->as_pointer_register(), as_Address(addr));
} else {
__ ldr(dest->as_pointer_register(), as_Address(addr));
}
break;
case T_INT:
#ifdef __SOFTFP__
case T_FLOAT:
#endif // __SOFTFP__
__ ldr(dest->as_pointer_register(), as_Address(addr));
break;
case T_BOOLEAN:
__ ldrb(dest->as_register(), as_Address(addr));
break;
case T_BYTE:
__ ldrsb(dest->as_register(), as_Address(addr));
break;
case T_CHAR:
__ ldrh(dest->as_register(), as_Address(addr));
break;
case T_SHORT:
__ ldrsh(dest->as_register(), as_Address(addr));
break;
#ifdef __SOFTFP__
case T_DOUBLE:
#endif // __SOFTFP__
case T_LONG: {
Register to_lo = dest->as_register_lo();
Register to_hi = dest->as_register_hi();
if (addr->index()->is_register()) {
assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
assert(addr->disp() == 0, "Not yet supporting both");
__ add(Rtemp, base_reg, addr->index()->as_register());
base_reg = Rtemp;
__ ldr(to_lo, Address(Rtemp));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd ldr
patching_epilog(patch, lir_patch_low, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_high;
}
__ ldr(to_hi, Address(Rtemp, BytesPerWord));
} else if (base_reg == to_lo) {
__ ldr(to_hi, as_Address_hi(addr));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd ldr
patching_epilog(patch, lir_patch_high, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_low;
}
__ ldr(to_lo, as_Address_lo(addr));
} else {
__ ldr(to_lo, as_Address_lo(addr));
if (patch != NULL) {
__ nop(); // see comment before patching_epilog for 2nd ldr
patching_epilog(patch, lir_patch_low, base_reg, info);
patch = new PatchingStub(_masm, PatchingStub::access_field_id);
patch_code = lir_patch_high;
}
__ ldr(to_hi, as_Address_hi(addr));
}
break;
}
#ifndef __SOFTFP__
case T_FLOAT:
if (addr->index()->is_register()) {
assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
__ add(Rtemp, base_reg, addr->index()->as_register());
if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
__ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
} else {
__ flds(dest->as_float_reg(), as_Address(addr));
}
break;
case T_DOUBLE:
if (addr->index()->is_register()) {
assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
__ add(Rtemp, base_reg, addr->index()->as_register());
if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
__ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
} else {
__ fldd(dest->as_double_reg(), as_Address(addr));
}
break;
#endif // __SOFTFP__
default:
ShouldNotReachHere();
}
if (patch != NULL) {
// Offset embedded into LDR/STR instruction may appear not enough
// to address a field. So, provide a space for one more instruction
// that will deal with larger offsets.
__ nop();
patching_epilog(patch, patch_code, base_reg, info);
}
}
void LIR_Assembler::emit_op3(LIR_Op3* op) {
bool is_32 = op->result_opr()->is_single_cpu();
if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
int c = op->in_opr2()->as_constant_ptr()->as_jint();
assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
Register left = op->in_opr1()->as_register();
Register dest = op->result_opr()->as_register();
if (c == 1) {
__ mov(dest, left);
} else if (c == 2) {
__ add_32(dest, left, AsmOperand(left, lsr, 31));
__ asr_32(dest, dest, 1);
} else if (c != (int) 0x80000000) {
int power = log2i_exact(c);
__ asr_32(Rtemp, left, 31);
__ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
__ asr_32(dest, dest, power); // dest = dest >>> power;
} else {
// x/0x80000000 is a special case, since dividend is a power of two, but is negative.
// The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
__ cmp_32(left, c);
__ mov(dest, 0, ne);
__ mov(dest, 1, eq);
}
} else {
assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
__ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
add_debug_info_for_div0_here(op->info());
}
}
void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
#ifdef ASSERT
assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
if (op->block() != NULL) _branch_target_blocks.append(op->block());
if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
assert(op->info() == NULL, "CodeEmitInfo?");
#endif // ASSERT
#ifdef __SOFTFP__
assert (op->code() != lir_cond_float_branch, "this should be impossible");
#else
if (op->code() == lir_cond_float_branch) {
__ fmstat();
__ b(*(op->ublock()->label()), vs);
}
#endif // __SOFTFP__
AsmCondition acond = al;
switch (op->cond()) {
case lir_cond_equal: acond = eq; break;
case lir_cond_notEqual: acond = ne; break;
case lir_cond_less: acond = lt; break;
case lir_cond_lessEqual: acond = le; break;
case lir_cond_greaterEqual: acond = ge; break;
case lir_cond_greater: acond = gt; break;
case lir_cond_aboveEqual: acond = hs; break;
case lir_cond_belowEqual: acond = ls; break;
default: assert(op->cond() == lir_cond_always, "must be");
}
__ b(*(op->label()), acond);
}
void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
LIR_Opr src = op->in_opr();
LIR_Opr dest = op->result_opr();
switch (op->bytecode()) {
case Bytecodes::_i2l:
move_regs(src->as_register(), dest->as_register_lo());
__ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
break;
case Bytecodes::_l2i:
move_regs(src->as_register_lo(), dest->as_register());
break;
case Bytecodes::_i2b:
__ sign_extend(dest->as_register(), src->as_register(), 8);
break;
case Bytecodes::_i2s:
__ sign_extend(dest->as_register(), src->as_register(), 16);
break;
case Bytecodes::_i2c:
__ zero_extend(dest->as_register(), src->as_register(), 16);
break;
case Bytecodes::_f2d:
__ convert_f2d(dest->as_double_reg(), src->as_float_reg());
break;
case Bytecodes::_d2f:
__ convert_d2f(dest->as_float_reg(), src->as_double_reg());
break;
case Bytecodes::_i2f:
__ fmsr(Stemp, src->as_register());
__ fsitos(dest->as_float_reg(), Stemp);
break;
case Bytecodes::_i2d:
__ fmsr(Stemp, src->as_register());
__ fsitod(dest->as_double_reg(), Stemp);
break;
case Bytecodes::_f2i:
__ ftosizs(Stemp, src->as_float_reg());
__ fmrs(dest->as_register(), Stemp);
break;
case Bytecodes::_d2i:
__ ftosizd(Stemp, src->as_double_reg());
__ fmrs(dest->as_register(), Stemp);
break;
default:
ShouldNotReachHere();
}
}
void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
if (op->init_check()) {
Register tmp = op->tmp1()->as_register();
__ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
add_debug_info_for_null_check_here(op->stub()->info());
__ cmp(tmp, InstanceKlass::fully_initialized);
__ b(*op->stub()->entry(), ne);
}
__ allocate_object(op->obj()->as_register(),
op->tmp1()->as_register(),
op->tmp2()->as_register(),
op->tmp3()->as_register(),
op->header_size(),
op->object_size(),
op->klass()->as_register(),
*op->stub()->entry());
__ bind(*op->stub()->continuation());
}
void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
if (UseSlowPath ||
(!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
(!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
__ b(*op->stub()->entry());
} else {
__ allocate_array(op->obj()->as_register(),
op->len()->as_register(),
op->tmp1()->as_register(),
op->tmp2()->as_register(),
op->tmp3()->as_register(),
arrayOopDesc::header_size(op->type()),
type2aelembytes(op->type()),
op->klass()->as_register(),
*op->stub()->entry());
}
__ bind(*op->stub()->continuation());
}
void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
ciMethodData *md, ciProfileData *data,
Register recv, Register tmp1, Label* update_done) {
assert_different_registers(mdo, recv, tmp1);
uint i;
for (i = 0; i < VirtualCallData::row_limit(); i++) {
Label next_test;
// See if the receiver is receiver[n].
Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
mdo_offset_bias);
__ ldr(tmp1, receiver_addr);
__ verify_klass_ptr(tmp1);