/
sharedRuntime_arm.cpp
1907 lines (1642 loc) · 68.9 KB
/
sharedRuntime_arm.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/assembler.hpp"
#include "assembler_arm.inline.hpp"
#include "code/debugInfoRec.hpp"
#include "code/icBuffer.hpp"
#include "code/vtableStubs.hpp"
#include "interpreter/interpreter.hpp"
#include "logging/log.hpp"
#include "memory/resourceArea.hpp"
#include "oops/compiledICHolder.hpp"
#include "oops/klass.inline.hpp"
#include "prims/methodHandles.hpp"
#include "runtime/jniHandles.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/safepointMechanism.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/vframeArray.hpp"
#include "utilities/align.hpp"
#include "utilities/powerOfTwo.hpp"
#include "vmreg_arm.inline.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
#endif
#ifdef COMPILER2
#include "opto/runtime.hpp"
#endif
#define __ masm->
class RegisterSaver {
public:
// Special registers:
// 32-bit ARM 64-bit ARM
// Rthread: R10 R28
// LR: R14 R30
// Rthread is callee saved in the C ABI and never changed by compiled code:
// no need to save it.
// 2 slots for LR: the one at LR_offset and an other one at R14/R30_offset.
// The one at LR_offset is a return address that is needed by stack walking.
// A c2 method uses LR as a standard register so it may be live when we
// branch to the runtime. The slot at R14/R30_offset is for the value of LR
// in case it's live in the method we are coming from.
enum RegisterLayout {
fpu_save_size = FloatRegisterImpl::number_of_registers,
#ifndef __SOFTFP__
D0_offset = 0,
#endif
R0_offset = fpu_save_size,
R1_offset,
R2_offset,
R3_offset,
R4_offset,
R5_offset,
R6_offset,
#if (FP_REG_NUM != 7)
// if not saved as FP
R7_offset,
#endif
R8_offset,
R9_offset,
#if (FP_REG_NUM != 11)
// if not saved as FP
R11_offset,
#endif
R12_offset,
R14_offset,
FP_offset,
LR_offset,
reg_save_size,
Rmethod_offset = R9_offset,
Rtemp_offset = R12_offset,
};
// all regs but Rthread (R10), FP (R7 or R11), SP and PC
// (altFP_7_11 is the one amoung R7 and R11 which is not FP)
#define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)
// When LR may be live in the nmethod from which we are comming
// then lr_saved is true, the return address is saved before the
// call to save_live_register by the caller and LR contains the
// live value.
static OopMap* save_live_registers(MacroAssembler* masm,
int* total_frame_words,
bool lr_saved = false);
static void restore_live_registers(MacroAssembler* masm, bool restore_lr = true);
};
OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm,
int* total_frame_words,
bool lr_saved) {
*total_frame_words = reg_save_size;
OopMapSet *oop_maps = new OopMapSet();
OopMap* map = new OopMap(VMRegImpl::slots_per_word * (*total_frame_words), 0);
if (lr_saved) {
__ push(RegisterSet(FP));
} else {
__ push(RegisterSet(FP) | RegisterSet(LR));
}
__ push(SAVED_BASE_REGS);
if (HaveVFP) {
if (VM_Version::has_vfp3_32()) {
__ fpush(FloatRegisterSet(D16, 16));
} else {
if (FloatRegisterImpl::number_of_registers > 32) {
assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");
__ sub(SP, SP, 32 * wordSize);
}
}
__ fpush(FloatRegisterSet(D0, 16));
} else {
__ sub(SP, SP, fpu_save_size * wordSize);
}
int i;
int j=0;
for (i = R0_offset; i <= R9_offset; i++) {
if (j == FP_REG_NUM) {
// skip the FP register, managed below.
j++;
}
map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
j++;
}
assert(j == R10->encoding(), "must be");
#if (FP_REG_NUM != 11)
// add R11, if not managed as FP
map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
#endif
map->set_callee_saved(VMRegImpl::stack2reg(R12_offset), R12->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(R14_offset), R14->as_VMReg());
if (HaveVFP) {
for (i = 0; i < (VM_Version::has_vfp3_32() ? 64 : 32); i+=2) {
map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
map->set_callee_saved(VMRegImpl::stack2reg(i + 1), as_FloatRegister(i)->as_VMReg()->next());
}
}
return map;
}
void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_lr) {
if (HaveVFP) {
__ fpop(FloatRegisterSet(D0, 16));
if (VM_Version::has_vfp3_32()) {
__ fpop(FloatRegisterSet(D16, 16));
} else {
if (FloatRegisterImpl::number_of_registers > 32) {
assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");
__ add(SP, SP, 32 * wordSize);
}
}
} else {
__ add(SP, SP, fpu_save_size * wordSize);
}
__ pop(SAVED_BASE_REGS);
if (restore_lr) {
__ pop(RegisterSet(FP) | RegisterSet(LR));
} else {
__ pop(RegisterSet(FP));
}
}
static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {
#ifdef __ABI_HARD__
if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
__ sub(SP, SP, 8);
__ fstd(D0, Address(SP));
return;
}
#endif // __ABI_HARD__
__ raw_push(R0, R1);
}
static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {
#ifdef __ABI_HARD__
if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
__ fldd(D0, Address(SP));
__ add(SP, SP, 8);
return;
}
#endif // __ABI_HARD__
__ raw_pop(R0, R1);
}
static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
// R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment
__ push(RegisterSet(R0, R3));
// preserve arguments
// Likely not needed as the locking code won't probably modify volatile FP registers,
// but there is no way to guarantee that
if (fp_regs_in_arguments) {
// convert fp_regs_in_arguments to a number of double registers
int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
__ fpush_hardfp(FloatRegisterSet(D0, double_regs_num));
}
}
static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
if (fp_regs_in_arguments) {
int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
__ fpop_hardfp(FloatRegisterSet(D0, double_regs_num));
}
__ pop(RegisterSet(R0, R3));
}
// Is vector's size (in bytes) bigger than a size saved by default?
// All vector registers are saved by default on ARM.
bool SharedRuntime::is_wide_vector(int size) {
return false;
}
size_t SharedRuntime::trampoline_size() {
return 16;
}
void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {
InlinedAddress dest(destination);
__ indirect_jump(dest, Rtemp);
__ bind_literal(dest);
}
int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
VMRegPair *regs2,
int total_args_passed) {
assert(regs2 == NULL, "not needed on arm");
int slot = 0;
int ireg = 0;
#ifdef __ABI_HARD__
int fp_slot = 0;
int single_fpr_slot = 0;
#endif // __ABI_HARD__
for (int i = 0; i < total_args_passed; i++) {
switch (sig_bt[i]) {
case T_SHORT:
case T_CHAR:
case T_BYTE:
case T_BOOLEAN:
case T_INT:
case T_ARRAY:
case T_OBJECT:
case T_ADDRESS:
case T_METADATA:
#ifndef __ABI_HARD__
case T_FLOAT:
#endif // !__ABI_HARD__
if (ireg < 4) {
Register r = as_Register(ireg);
regs[i].set1(r->as_VMReg());
ireg++;
} else {
regs[i].set1(VMRegImpl::stack2reg(slot));
slot++;
}
break;
case T_LONG:
#ifndef __ABI_HARD__
case T_DOUBLE:
#endif // !__ABI_HARD__
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
if (ireg <= 2) {
#if (ALIGN_WIDE_ARGUMENTS == 1)
if(ireg & 1) ireg++; // Aligned location required
#endif
Register r1 = as_Register(ireg);
Register r2 = as_Register(ireg + 1);
regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
ireg += 2;
#if (ALIGN_WIDE_ARGUMENTS == 0)
} else if (ireg == 3) {
// uses R3 + one stack slot
Register r = as_Register(ireg);
regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());
ireg += 1;
slot += 1;
#endif
} else {
if (slot & 1) slot++; // Aligned location required
regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
slot += 2;
ireg = 4;
}
break;
case T_VOID:
regs[i].set_bad();
break;
#ifdef __ABI_HARD__
case T_FLOAT:
if ((fp_slot < 16)||(single_fpr_slot & 1)) {
if ((single_fpr_slot & 1) == 0) {
single_fpr_slot = fp_slot;
fp_slot += 2;
}
FloatRegister r = as_FloatRegister(single_fpr_slot);
single_fpr_slot++;
regs[i].set1(r->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(slot));
slot++;
}
break;
case T_DOUBLE:
assert(ALIGN_WIDE_ARGUMENTS == 1, "ABI_HARD not supported with unaligned wide arguments");
if (fp_slot <= 14) {
FloatRegister r1 = as_FloatRegister(fp_slot);
FloatRegister r2 = as_FloatRegister(fp_slot+1);
regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
fp_slot += 2;
} else {
if(slot & 1) slot++;
regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
slot += 2;
single_fpr_slot = 16;
}
break;
#endif // __ABI_HARD__
default:
ShouldNotReachHere();
}
}
return slot;
}
int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
int total_args_passed) {
#ifdef __SOFTFP__
// soft float is the same as the C calling convention.
return c_calling_convention(sig_bt, regs, NULL, total_args_passed);
#endif // __SOFTFP__
int slot = 0;
int ireg = 0;
int freg = 0;
int single_fpr = 0;
for (int i = 0; i < total_args_passed; i++) {
switch (sig_bt[i]) {
case T_SHORT:
case T_CHAR:
case T_BYTE:
case T_BOOLEAN:
case T_INT:
case T_ARRAY:
case T_OBJECT:
case T_ADDRESS:
if (ireg < 4) {
Register r = as_Register(ireg++);
regs[i].set1(r->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(slot++));
}
break;
case T_FLOAT:
// C2 utilizes S14/S15 for mem-mem moves
if ((freg < 16 COMPILER2_PRESENT(-2)) || (single_fpr & 1)) {
if ((single_fpr & 1) == 0) {
single_fpr = freg;
freg += 2;
}
FloatRegister r = as_FloatRegister(single_fpr++);
regs[i].set1(r->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(slot++));
}
break;
case T_DOUBLE:
// C2 utilizes S14/S15 for mem-mem moves
if (freg <= 14 COMPILER2_PRESENT(-2)) {
FloatRegister r1 = as_FloatRegister(freg);
FloatRegister r2 = as_FloatRegister(freg + 1);
regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
freg += 2;
} else {
// Keep internally the aligned calling convention,
// ignoring ALIGN_WIDE_ARGUMENTS
if (slot & 1) slot++;
regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
slot += 2;
single_fpr = 16;
}
break;
case T_LONG:
// Keep internally the aligned calling convention,
// ignoring ALIGN_WIDE_ARGUMENTS
if (ireg <= 2) {
if (ireg & 1) ireg++;
Register r1 = as_Register(ireg);
Register r2 = as_Register(ireg + 1);
regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
ireg += 2;
} else {
if (slot & 1) slot++;
regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
slot += 2;
ireg = 4;
}
break;
case T_VOID:
regs[i].set_bad();
break;
default:
ShouldNotReachHere();
}
}
if (slot & 1) slot++;
return slot;
}
static void patch_callers_callsite(MacroAssembler *masm) {
Label skip;
__ ldr(Rtemp, Address(Rmethod, Method::code_offset()));
__ cbz(Rtemp, skip);
// Pushing an even number of registers for stack alignment.
// Selecting R9, which had to be saved anyway for some platforms.
__ push(RegisterSet(R0, R3) | R9 | LR);
__ fpush_hardfp(FloatRegisterSet(D0, 8));
__ mov(R0, Rmethod);
__ mov(R1, LR);
__ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
__ fpop_hardfp(FloatRegisterSet(D0, 8));
__ pop(RegisterSet(R0, R3) | R9 | LR);
__ bind(skip);
}
void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
int total_args_passed, int comp_args_on_stack,
const BasicType *sig_bt, const VMRegPair *regs) {
// TODO: ARM - May be can use ldm to load arguments
const Register tmp = Rtemp; // avoid erasing R5_mh
// Next assert may not be needed but safer. Extra analysis required
// if this there is not enough free registers and we need to use R5 here.
assert_different_registers(tmp, R5_mh);
// 6243940 We might end up in handle_wrong_method if
// the callee is deoptimized as we race thru here. If that
// happens we don't want to take a safepoint because the
// caller frame will look interpreted and arguments are now
// "compiled" so it is much better to make this transition
// invisible to the stack walking code. Unfortunately if
// we try and find the callee by normal means a safepoint
// is possible. So we stash the desired callee in the thread
// and the vm will find there should this case occur.
Address callee_target_addr(Rthread, JavaThread::callee_target_offset());
__ str(Rmethod, callee_target_addr);
assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, Rmethod);
const Register initial_sp = Rmethod; // temporarily scratched
// Old code was modifying R4 but this looks unsafe (particularly with JSR292)
assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, initial_sp);
__ mov(initial_sp, SP);
if (comp_args_on_stack) {
__ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);
}
__ bic(SP, SP, StackAlignmentInBytes - 1);
for (int i = 0; i < total_args_passed; i++) {
if (sig_bt[i] == T_VOID) {
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
continue;
}
assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");
int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (r_1->is_stack()) {
int stack_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size;
if (!r_2->is_valid()) {
__ ldr(tmp, Address(initial_sp, arg_offset));
__ str(tmp, Address(SP, stack_offset));
} else {
__ ldr(tmp, Address(initial_sp, arg_offset - Interpreter::stackElementSize));
__ str(tmp, Address(SP, stack_offset));
__ ldr(tmp, Address(initial_sp, arg_offset));
__ str(tmp, Address(SP, stack_offset + wordSize));
}
} else if (r_1->is_Register()) {
if (!r_2->is_valid()) {
__ ldr(r_1->as_Register(), Address(initial_sp, arg_offset));
} else {
__ ldr(r_1->as_Register(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
__ ldr(r_2->as_Register(), Address(initial_sp, arg_offset));
}
} else if (r_1->is_FloatRegister()) {
#ifdef __SOFTFP__
ShouldNotReachHere();
#endif // __SOFTFP__
if (!r_2->is_valid()) {
__ flds(r_1->as_FloatRegister(), Address(initial_sp, arg_offset));
} else {
__ fldd(r_1->as_FloatRegister(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
}
} else {
assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
}
}
// restore Rmethod (scratched for initial_sp)
__ ldr(Rmethod, callee_target_addr);
__ ldr(PC, Address(Rmethod, Method::from_compiled_offset()));
}
static void gen_c2i_adapter(MacroAssembler *masm,
int total_args_passed, int comp_args_on_stack,
const BasicType *sig_bt, const VMRegPair *regs,
Label& skip_fixup) {
// TODO: ARM - May be can use stm to deoptimize arguments
const Register tmp = Rtemp;
patch_callers_callsite(masm);
__ bind(skip_fixup);
__ mov(Rsender_sp, SP); // not yet saved
int extraspace = total_args_passed * Interpreter::stackElementSize;
if (extraspace) {
__ sub_slow(SP, SP, extraspace);
}
for (int i = 0; i < total_args_passed; i++) {
if (sig_bt[i] == T_VOID) {
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
continue;
}
int stack_offset = (total_args_passed - 1 - i) * Interpreter::stackElementSize;
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (r_1->is_stack()) {
int arg_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
if (!r_2->is_valid()) {
__ ldr(tmp, Address(SP, arg_offset));
__ str(tmp, Address(SP, stack_offset));
} else {
__ ldr(tmp, Address(SP, arg_offset));
__ str(tmp, Address(SP, stack_offset - Interpreter::stackElementSize));
__ ldr(tmp, Address(SP, arg_offset + wordSize));
__ str(tmp, Address(SP, stack_offset));
}
} else if (r_1->is_Register()) {
if (!r_2->is_valid()) {
__ str(r_1->as_Register(), Address(SP, stack_offset));
} else {
__ str(r_1->as_Register(), Address(SP, stack_offset - Interpreter::stackElementSize));
__ str(r_2->as_Register(), Address(SP, stack_offset));
}
} else if (r_1->is_FloatRegister()) {
#ifdef __SOFTFP__
ShouldNotReachHere();
#endif // __SOFTFP__
if (!r_2->is_valid()) {
__ fsts(r_1->as_FloatRegister(), Address(SP, stack_offset));
} else {
__ fstd(r_1->as_FloatRegister(), Address(SP, stack_offset - Interpreter::stackElementSize));
}
} else {
assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
}
}
__ ldr(PC, Address(Rmethod, Method::interpreter_entry_offset()));
}
AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
int total_args_passed,
int comp_args_on_stack,
const BasicType *sig_bt,
const VMRegPair *regs,
AdapterFingerPrint* fingerprint) {
address i2c_entry = __ pc();
gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
address c2i_unverified_entry = __ pc();
Label skip_fixup;
const Register receiver = R0;
const Register holder_klass = Rtemp; // XXX should be OK for C2 but not 100% sure
const Register receiver_klass = R4;
__ load_klass(receiver_klass, receiver);
__ ldr(holder_klass, Address(Ricklass, CompiledICHolder::holder_klass_offset()));
__ ldr(Rmethod, Address(Ricklass, CompiledICHolder::holder_metadata_offset()));
__ cmp(receiver_klass, holder_klass);
__ ldr(Rtemp, Address(Rmethod, Method::code_offset()), eq);
__ cmp(Rtemp, 0, eq);
__ b(skip_fixup, eq);
__ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
address c2i_entry = __ pc();
gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
__ flush();
return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
}
static int reg2offset_in(VMReg r) {
// Account for saved FP and LR
return r->reg2stack() * VMRegImpl::stack_slot_size + 2*wordSize;
}
static int reg2offset_out(VMReg r) {
return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
}
static void verify_oop_args(MacroAssembler* masm,
const methodHandle& method,
const BasicType* sig_bt,
const VMRegPair* regs) {
Register temp_reg = Rmethod; // not part of any compiled calling seq
if (VerifyOops) {
for (int i = 0; i < method->size_of_parameters(); i++) {
if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
VMReg r = regs[i].first();
assert(r->is_valid(), "bad oop arg");
if (r->is_stack()) {
__ ldr(temp_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
__ verify_oop(temp_reg);
} else {
__ verify_oop(r->as_Register());
}
}
}
}
}
static void gen_special_dispatch(MacroAssembler* masm,
const methodHandle& method,
const BasicType* sig_bt,
const VMRegPair* regs) {
verify_oop_args(masm, method, sig_bt, regs);
vmIntrinsics::ID iid = method->intrinsic_id();
// Now write the args into the outgoing interpreter space
bool has_receiver = false;
Register receiver_reg = noreg;
int member_arg_pos = -1;
Register member_reg = noreg;
int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
if (ref_kind != 0) {
member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
member_reg = Rmethod; // known to be free at this point
has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
} else if (iid == vmIntrinsics::_invokeBasic) {
has_receiver = true;
} else {
fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid));
}
if (member_reg != noreg) {
// Load the member_arg into register, if necessary.
SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
VMReg r = regs[member_arg_pos].first();
if (r->is_stack()) {
__ ldr(member_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
} else {
// no data motion is needed
member_reg = r->as_Register();
}
}
if (has_receiver) {
// Make sure the receiver is loaded into a register.
assert(method->size_of_parameters() > 0, "oob");
assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
VMReg r = regs[0].first();
assert(r->is_valid(), "bad receiver arg");
if (r->is_stack()) {
// Porting note: This assumes that compiled calling conventions always
// pass the receiver oop in a register. If this is not true on some
// platform, pick a temp and load the receiver from stack.
assert(false, "receiver always in a register");
receiver_reg = j_rarg0; // known to be free at this point
__ ldr(receiver_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
} else {
// no data motion is needed
receiver_reg = r->as_Register();
}
}
// Figure out which address we are really jumping to:
MethodHandles::generate_method_handle_dispatch(masm, iid,
receiver_reg, member_reg, /*for_compiler_entry:*/ true);
}
// ---------------------------------------------------------------------------
// Generate a native wrapper for a given method. The method takes arguments
// in the Java compiled code convention, marshals them to the native
// convention (handlizes oops, etc), transitions to native, makes the call,
// returns to java state (possibly blocking), unhandlizes any result and
// returns.
nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
const methodHandle& method,
int compile_id,
BasicType* in_sig_bt,
VMRegPair* in_regs,
BasicType ret_type,
address critical_entry) {
if (method->is_method_handle_intrinsic()) {
vmIntrinsics::ID iid = method->intrinsic_id();
intptr_t start = (intptr_t)__ pc();
int vep_offset = ((intptr_t)__ pc()) - start;
gen_special_dispatch(masm,
method,
in_sig_bt,
in_regs);
int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
__ flush();
int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
return nmethod::new_native_nmethod(method,
compile_id,
masm->code(),
vep_offset,
frame_complete,
stack_slots / VMRegImpl::slots_per_word,
in_ByteSize(-1),
in_ByteSize(-1),
(OopMapSet*)NULL);
}
// Arguments for JNI method include JNIEnv and Class if static
// Usage of Rtemp should be OK since scratched by native call
bool is_static = method->is_static();
const int total_in_args = method->size_of_parameters();
int total_c_args = total_in_args + 1;
if (is_static) {
total_c_args++;
}
BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
int argc = 0;
out_sig_bt[argc++] = T_ADDRESS;
if (is_static) {
out_sig_bt[argc++] = T_OBJECT;
}
int i;
for (i = 0; i < total_in_args; i++) {
out_sig_bt[argc++] = in_sig_bt[i];
}
int out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
// Since object arguments need to be wrapped, we must preserve space
// for those object arguments which come in registers (GPR_PARAMS maximum)
// plus one more slot for Klass handle (for static methods)
int oop_handle_offset = stack_slots;
stack_slots += (GPR_PARAMS + 1) * VMRegImpl::slots_per_word;
// Plus a lock if needed
int lock_slot_offset = 0;
if (method->is_synchronized()) {
lock_slot_offset = stack_slots;
assert(sizeof(BasicLock) == wordSize, "adjust this code");
stack_slots += VMRegImpl::slots_per_word;
}
// Space to save return address and FP
stack_slots += 2 * VMRegImpl::slots_per_word;
// Calculate the final stack size taking account of alignment
stack_slots = align_up(stack_slots, StackAlignmentInBytes / VMRegImpl::stack_slot_size);
int stack_size = stack_slots * VMRegImpl::stack_slot_size;
int lock_slot_fp_offset = stack_size - 2 * wordSize -
lock_slot_offset * VMRegImpl::stack_slot_size;
// Unverified entry point
address start = __ pc();
// Inline cache check, same as in C1_MacroAssembler::inline_cache_check()
const Register receiver = R0; // see receiverOpr()
__ load_klass(Rtemp, receiver);
__ cmp(Rtemp, Ricklass);
Label verified;
__ b(verified, eq); // jump over alignment no-ops too
__ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, Rtemp);
__ align(CodeEntryAlignment);
// Verified entry point
__ bind(verified);
int vep_offset = __ pc() - start;
if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
// Object.hashCode, System.identityHashCode can pull the hashCode from the header word
// instead of doing a full VM transition once it's been computed.
Label slow_case;
const Register obj_reg = R0;
// Unlike for Object.hashCode, System.identityHashCode is static method and
// gets object as argument instead of the receiver.
if (method->intrinsic_id() == vmIntrinsics::_identityHashCode) {
assert(method->is_static(), "method should be static");
// return 0 for null reference input, return val = R0 = obj_reg = 0
__ cmp(obj_reg, 0);
__ bx(LR, eq);
}
__ ldr(Rtemp, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
assert(markWord::unlocked_value == 1, "adjust this code");
__ tbz(Rtemp, exact_log2(markWord::unlocked_value), slow_case);
if (UseBiasedLocking) {
assert(is_power_of_2(markWord::biased_lock_bit_in_place), "adjust this code");
__ tbnz(Rtemp, exact_log2(markWord::biased_lock_bit_in_place), slow_case);
}
__ bics(Rtemp, Rtemp, ~markWord::hash_mask_in_place);
__ mov(R0, AsmOperand(Rtemp, lsr, markWord::hash_shift), ne);
__ bx(LR, ne);
__ bind(slow_case);
}
// Bang stack pages
__ arm_stack_overflow_check(stack_size, Rtemp);
// Setup frame linkage
__ raw_push(FP, LR);
__ mov(FP, SP);
__ sub_slow(SP, SP, stack_size - 2*wordSize);
int frame_complete = __ pc() - start;
OopMapSet* oop_maps = new OopMapSet();
OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
const int extra_args = is_static ? 2 : 1;
int receiver_offset = -1;
int fp_regs_in_arguments = 0;
for (i = total_in_args; --i >= 0; ) {
switch (in_sig_bt[i]) {
case T_ARRAY:
case T_OBJECT: {
VMReg src = in_regs[i].first();
VMReg dst = out_regs[i + extra_args].first();
if (src->is_stack()) {
assert(dst->is_stack(), "must be");
assert(i != 0, "Incoming receiver is always in a register");
__ ldr(Rtemp, Address(FP, reg2offset_in(src)));
__ cmp(Rtemp, 0);
__ add(Rtemp, FP, reg2offset_in(src), ne);
__ str(Rtemp, Address(SP, reg2offset_out(dst)));
int offset_in_older_frame = src->reg2stack() + SharedRuntime::out_preserve_stack_slots();
map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
} else {
int offset = oop_handle_offset * VMRegImpl::stack_slot_size;
__ str(src->as_Register(), Address(SP, offset));
map->set_oop(VMRegImpl::stack2reg(oop_handle_offset));
if ((i == 0) && (!is_static)) {
receiver_offset = offset;
}
oop_handle_offset += VMRegImpl::slots_per_word;
if (dst->is_stack()) {
__ movs(Rtemp, src->as_Register());
__ add(Rtemp, SP, offset, ne);
__ str(Rtemp, Address(SP, reg2offset_out(dst)));
} else {
__ movs(dst->as_Register(), src->as_Register());
__ add(dst->as_Register(), SP, offset, ne);
}
}
}
case T_VOID:
break;
#ifdef __SOFTFP__
case T_DOUBLE:
#endif
case T_LONG: {
VMReg src_1 = in_regs[i].first();
VMReg src_2 = in_regs[i].second();
VMReg dst_1 = out_regs[i + extra_args].first();
VMReg dst_2 = out_regs[i + extra_args].second();
#if (ALIGN_WIDE_ARGUMENTS == 0)
// C convention can mix a register and a stack slot for a
// 64-bits native argument.
// Note: following code should work independently of whether
// the Java calling convention follows C convention or whether
// it aligns 64-bit values.
if (dst_2->is_Register()) {
if (src_1->as_Register() != dst_1->as_Register()) {
assert(src_1->as_Register() != dst_2->as_Register() &&
src_2->as_Register() != dst_2->as_Register(), "must be");
__ mov(dst_2->as_Register(), src_2->as_Register());
__ mov(dst_1->as_Register(), src_1->as_Register());
} else {
assert(src_2->as_Register() == dst_2->as_Register(), "must be");
}
} else if (src_2->is_Register()) {
if (dst_1->is_Register()) {
// dst mixes a register and a stack slot
assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
assert(src_1->as_Register() != dst_1->as_Register(), "must be");
__ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
__ mov(dst_1->as_Register(), src_1->as_Register());
} else {
// registers to stack slots
assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
__ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
__ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
}
} else if (src_1->is_Register()) {
if (dst_1->is_Register()) {
// src and dst must be R3 + stack slot
assert(dst_1->as_Register() == src_1->as_Register(), "must be");
__ ldr(Rtemp, Address(FP, reg2offset_in(src_2)));
__ str(Rtemp, Address(SP, reg2offset_out(dst_2)));
} else {
// <R3,stack> -> <stack,stack>
assert(dst_2->is_stack() && src_2->is_stack(), "must be");
__ ldr(LR, Address(FP, reg2offset_in(src_2)));
__ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
__ str(LR, Address(SP, reg2offset_out(dst_2)));
}
} else {
assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
__ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
__ ldr(LR, Address(FP, reg2offset_in(src_2)));
__ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
__ str(LR, Address(SP, reg2offset_out(dst_2)));
}
#else // ALIGN_WIDE_ARGUMENTS
if (src_1->is_stack()) {
assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
__ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
__ ldr(LR, Address(FP, reg2offset_in(src_2)));
__ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
__ str(LR, Address(SP, reg2offset_out(dst_2)));
} else if (dst_1->is_stack()) {
assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");