/
sharedRuntime_ppc.cpp
3442 lines (2937 loc) · 124 KB
/
sharedRuntime_ppc.cpp
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/*
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "code/debugInfoRec.hpp"
#include "code/icBuffer.hpp"
#include "code/vtableStubs.hpp"
#include "frame_ppc.hpp"
#include "gc/shared/gcLocker.hpp"
#include "interpreter/interpreter.hpp"
#include "interpreter/interp_masm.hpp"
#include "memory/resourceArea.hpp"
#include "oops/compiledICHolder.hpp"
#include "oops/klass.inline.hpp"
#include "prims/methodHandles.hpp"
#include "runtime/jniHandles.hpp"
#include "runtime/safepointMechanism.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/vframeArray.hpp"
#include "utilities/align.hpp"
#include "vmreg_ppc.inline.hpp"
#ifdef COMPILER1
#include "c1/c1_Runtime1.hpp"
#endif
#ifdef COMPILER2
#include "opto/ad.hpp"
#include "opto/runtime.hpp"
#endif
#include <alloca.h>
#define __ masm->
#ifdef PRODUCT
#define BLOCK_COMMENT(str) // nothing
#else
#define BLOCK_COMMENT(str) __ block_comment(str)
#endif
#define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
class RegisterSaver {
// Used for saving volatile registers.
public:
// Support different return pc locations.
enum ReturnPCLocation {
return_pc_is_lr,
return_pc_is_pre_saved,
return_pc_is_thread_saved_exception_pc
};
static OopMap* push_frame_reg_args_and_save_live_registers(MacroAssembler* masm,
int* out_frame_size_in_bytes,
bool generate_oop_map,
int return_pc_adjustment,
ReturnPCLocation return_pc_location,
bool save_vectors = false);
static void restore_live_registers_and_pop_frame(MacroAssembler* masm,
int frame_size_in_bytes,
bool restore_ctr,
bool save_vectors = false);
static void push_frame_and_save_argument_registers(MacroAssembler* masm,
Register r_temp,
int frame_size,
int total_args,
const VMRegPair *regs, const VMRegPair *regs2 = NULL);
static void restore_argument_registers_and_pop_frame(MacroAssembler*masm,
int frame_size,
int total_args,
const VMRegPair *regs, const VMRegPair *regs2 = NULL);
// During deoptimization only the result registers need to be restored
// all the other values have already been extracted.
static void restore_result_registers(MacroAssembler* masm, int frame_size_in_bytes);
// Constants and data structures:
typedef enum {
int_reg,
float_reg,
special_reg,
vs_reg
} RegisterType;
typedef enum {
reg_size = 8,
half_reg_size = reg_size / 2,
vs_reg_size = 16
} RegisterConstants;
typedef struct {
RegisterType reg_type;
int reg_num;
VMReg vmreg;
} LiveRegType;
};
#define RegisterSaver_LiveIntReg(regname) \
{ RegisterSaver::int_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveFloatReg(regname) \
{ RegisterSaver::float_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveSpecialReg(regname) \
{ RegisterSaver::special_reg, regname->encoding(), regname->as_VMReg() }
#define RegisterSaver_LiveVSReg(regname) \
{ RegisterSaver::vs_reg, regname->encoding(), regname->as_VMReg() }
static const RegisterSaver::LiveRegType RegisterSaver_LiveRegs[] = {
// Live registers which get spilled to the stack. Register
// positions in this array correspond directly to the stack layout.
//
// live special registers:
//
RegisterSaver_LiveSpecialReg(SR_CTR),
//
// live float registers:
//
RegisterSaver_LiveFloatReg( F0 ),
RegisterSaver_LiveFloatReg( F1 ),
RegisterSaver_LiveFloatReg( F2 ),
RegisterSaver_LiveFloatReg( F3 ),
RegisterSaver_LiveFloatReg( F4 ),
RegisterSaver_LiveFloatReg( F5 ),
RegisterSaver_LiveFloatReg( F6 ),
RegisterSaver_LiveFloatReg( F7 ),
RegisterSaver_LiveFloatReg( F8 ),
RegisterSaver_LiveFloatReg( F9 ),
RegisterSaver_LiveFloatReg( F10 ),
RegisterSaver_LiveFloatReg( F11 ),
RegisterSaver_LiveFloatReg( F12 ),
RegisterSaver_LiveFloatReg( F13 ),
RegisterSaver_LiveFloatReg( F14 ),
RegisterSaver_LiveFloatReg( F15 ),
RegisterSaver_LiveFloatReg( F16 ),
RegisterSaver_LiveFloatReg( F17 ),
RegisterSaver_LiveFloatReg( F18 ),
RegisterSaver_LiveFloatReg( F19 ),
RegisterSaver_LiveFloatReg( F20 ),
RegisterSaver_LiveFloatReg( F21 ),
RegisterSaver_LiveFloatReg( F22 ),
RegisterSaver_LiveFloatReg( F23 ),
RegisterSaver_LiveFloatReg( F24 ),
RegisterSaver_LiveFloatReg( F25 ),
RegisterSaver_LiveFloatReg( F26 ),
RegisterSaver_LiveFloatReg( F27 ),
RegisterSaver_LiveFloatReg( F28 ),
RegisterSaver_LiveFloatReg( F29 ),
RegisterSaver_LiveFloatReg( F30 ),
RegisterSaver_LiveFloatReg( F31 ),
//
// live integer registers:
//
RegisterSaver_LiveIntReg( R0 ),
//RegisterSaver_LiveIntReg( R1 ), // stack pointer
RegisterSaver_LiveIntReg( R2 ),
RegisterSaver_LiveIntReg( R3 ),
RegisterSaver_LiveIntReg( R4 ),
RegisterSaver_LiveIntReg( R5 ),
RegisterSaver_LiveIntReg( R6 ),
RegisterSaver_LiveIntReg( R7 ),
RegisterSaver_LiveIntReg( R8 ),
RegisterSaver_LiveIntReg( R9 ),
RegisterSaver_LiveIntReg( R10 ),
RegisterSaver_LiveIntReg( R11 ),
RegisterSaver_LiveIntReg( R12 ),
//RegisterSaver_LiveIntReg( R13 ), // system thread id
RegisterSaver_LiveIntReg( R14 ),
RegisterSaver_LiveIntReg( R15 ),
RegisterSaver_LiveIntReg( R16 ),
RegisterSaver_LiveIntReg( R17 ),
RegisterSaver_LiveIntReg( R18 ),
RegisterSaver_LiveIntReg( R19 ),
RegisterSaver_LiveIntReg( R20 ),
RegisterSaver_LiveIntReg( R21 ),
RegisterSaver_LiveIntReg( R22 ),
RegisterSaver_LiveIntReg( R23 ),
RegisterSaver_LiveIntReg( R24 ),
RegisterSaver_LiveIntReg( R25 ),
RegisterSaver_LiveIntReg( R26 ),
RegisterSaver_LiveIntReg( R27 ),
RegisterSaver_LiveIntReg( R28 ),
RegisterSaver_LiveIntReg( R29 ),
RegisterSaver_LiveIntReg( R30 ),
RegisterSaver_LiveIntReg( R31 ) // must be the last register (see save/restore functions below)
};
static const RegisterSaver::LiveRegType RegisterSaver_LiveVSRegs[] = {
//
// live vector scalar registers (optional, only these ones are used by C2):
//
RegisterSaver_LiveVSReg( VSR32 ),
RegisterSaver_LiveVSReg( VSR33 ),
RegisterSaver_LiveVSReg( VSR34 ),
RegisterSaver_LiveVSReg( VSR35 ),
RegisterSaver_LiveVSReg( VSR36 ),
RegisterSaver_LiveVSReg( VSR37 ),
RegisterSaver_LiveVSReg( VSR38 ),
RegisterSaver_LiveVSReg( VSR39 ),
RegisterSaver_LiveVSReg( VSR40 ),
RegisterSaver_LiveVSReg( VSR41 ),
RegisterSaver_LiveVSReg( VSR42 ),
RegisterSaver_LiveVSReg( VSR43 ),
RegisterSaver_LiveVSReg( VSR44 ),
RegisterSaver_LiveVSReg( VSR45 ),
RegisterSaver_LiveVSReg( VSR46 ),
RegisterSaver_LiveVSReg( VSR47 ),
RegisterSaver_LiveVSReg( VSR48 ),
RegisterSaver_LiveVSReg( VSR49 ),
RegisterSaver_LiveVSReg( VSR50 ),
RegisterSaver_LiveVSReg( VSR51 )
};
OopMap* RegisterSaver::push_frame_reg_args_and_save_live_registers(MacroAssembler* masm,
int* out_frame_size_in_bytes,
bool generate_oop_map,
int return_pc_adjustment,
ReturnPCLocation return_pc_location,
bool save_vectors) {
// Push an abi_reg_args-frame and store all registers which may be live.
// If requested, create an OopMap: Record volatile registers as
// callee-save values in an OopMap so their save locations will be
// propagated to the RegisterMap of the caller frame during
// StackFrameStream construction (needed for deoptimization; see
// compiledVFrame::create_stack_value).
// If return_pc_adjustment != 0 adjust the return pc by return_pc_adjustment.
// Updated return pc is returned in R31 (if not return_pc_is_pre_saved).
// calcualte frame size
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) /
sizeof(RegisterSaver::LiveRegType))
: 0;
const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size;
const int frame_size_in_bytes = align_up(register_save_size, frame::alignment_in_bytes)
+ frame::abi_reg_args_size;
*out_frame_size_in_bytes = frame_size_in_bytes;
const int frame_size_in_slots = frame_size_in_bytes / sizeof(jint);
const int register_save_offset = frame_size_in_bytes - register_save_size;
// OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words.
OopMap* map = generate_oop_map ? new OopMap(frame_size_in_slots, 0) : NULL;
BLOCK_COMMENT("push_frame_reg_args_and_save_live_registers {");
// push a new frame
__ push_frame(frame_size_in_bytes, noreg);
// Save some registers in the last (non-vector) slots of the new frame so we
// can use them as scratch regs or to determine the return pc.
__ std(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP);
__ std(R30, frame_size_in_bytes - 2*reg_size - vsregstosave_num * vs_reg_size, R1_SP);
// save the flags
// Do the save_LR_CR by hand and adjust the return pc if requested.
__ mfcr(R30);
__ std(R30, frame_size_in_bytes + _abi0(cr), R1_SP);
switch (return_pc_location) {
case return_pc_is_lr: __ mflr(R31); break;
case return_pc_is_pre_saved: assert(return_pc_adjustment == 0, "unsupported"); break;
case return_pc_is_thread_saved_exception_pc: __ ld(R31, thread_(saved_exception_pc)); break;
default: ShouldNotReachHere();
}
if (return_pc_location != return_pc_is_pre_saved) {
if (return_pc_adjustment != 0) {
__ addi(R31, R31, return_pc_adjustment);
}
__ std(R31, frame_size_in_bytes + _abi0(lr), R1_SP);
}
// save all registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (reg_num < 30) { // We spilled R30-31 right at the beginning.
__ std(as_Register(reg_num), offset, R1_SP);
}
break;
}
case RegisterSaver::float_reg: {
__ stfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
if (reg_num == SR_CTR_SpecialRegisterEnumValue) {
__ mfctr(R30);
__ std(R30, offset, R1_SP);
} else {
Unimplemented();
}
break;
}
default:
ShouldNotReachHere();
}
if (generate_oop_map) {
map->set_callee_saved(VMRegImpl::stack2reg(offset>>2),
RegisterSaver_LiveRegs[i].vmreg);
map->set_callee_saved(VMRegImpl::stack2reg((offset + half_reg_size)>>2),
RegisterSaver_LiveRegs[i].vmreg->next());
}
offset += reg_size;
}
for (int i = 0; i < vsregstosave_num; i++) {
int reg_num = RegisterSaver_LiveVSRegs[i].reg_num;
int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
__ li(R30, offset);
__ stxvd2x(as_VectorSRegister(reg_num), R30, R1_SP);
if (generate_oop_map) {
map->set_callee_saved(VMRegImpl::stack2reg(offset>>2),
RegisterSaver_LiveVSRegs[i].vmreg);
}
offset += vs_reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
BLOCK_COMMENT("} push_frame_reg_args_and_save_live_registers");
// And we're done.
return map;
}
// Pop the current frame and restore all the registers that we
// saved.
void RegisterSaver::restore_live_registers_and_pop_frame(MacroAssembler* masm,
int frame_size_in_bytes,
bool restore_ctr,
bool save_vectors) {
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int vsregstosave_num = save_vectors ? (sizeof(RegisterSaver_LiveVSRegs) /
sizeof(RegisterSaver::LiveRegType))
: 0;
const int register_save_size = regstosave_num * reg_size + vsregstosave_num * vs_reg_size;
const int register_save_offset = frame_size_in_bytes - register_save_size;
BLOCK_COMMENT("restore_live_registers_and_pop_frame {");
// restore all registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (reg_num != 31) // R31 restored at the end, it's the tmp reg!
__ ld(as_Register(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::float_reg: {
__ lfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
if (reg_num == SR_CTR_SpecialRegisterEnumValue) {
if (restore_ctr) { // Nothing to do here if ctr already contains the next address.
__ ld(R31, offset, R1_SP);
__ mtctr(R31);
}
} else {
Unimplemented();
}
break;
}
default:
ShouldNotReachHere();
}
offset += reg_size;
}
for (int i = 0; i < vsregstosave_num; i++) {
int reg_num = RegisterSaver_LiveVSRegs[i].reg_num;
int reg_type = RegisterSaver_LiveVSRegs[i].reg_type;
__ li(R31, offset);
__ lxvd2x(as_VectorSRegister(reg_num), R31, R1_SP);
offset += vs_reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
// restore link and the flags
__ ld(R31, frame_size_in_bytes + _abi0(lr), R1_SP);
__ mtlr(R31);
__ ld(R31, frame_size_in_bytes + _abi0(cr), R1_SP);
__ mtcr(R31);
// restore scratch register's value
__ ld(R31, frame_size_in_bytes - reg_size - vsregstosave_num * vs_reg_size, R1_SP);
// pop the frame
__ addi(R1_SP, R1_SP, frame_size_in_bytes);
BLOCK_COMMENT("} restore_live_registers_and_pop_frame");
}
void RegisterSaver::push_frame_and_save_argument_registers(MacroAssembler* masm, Register r_temp,
int frame_size,int total_args, const VMRegPair *regs,
const VMRegPair *regs2) {
__ push_frame(frame_size, r_temp);
int st_off = frame_size - wordSize;
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "");
continue;
}
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ std(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ stfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
if (regs2 != NULL) {
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs2[i].first();
VMReg r_2 = regs2[i].second();
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "");
continue;
}
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ std(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ stfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
}
}
void RegisterSaver::restore_argument_registers_and_pop_frame(MacroAssembler*masm, int frame_size,
int total_args, const VMRegPair *regs,
const VMRegPair *regs2) {
int st_off = frame_size - wordSize;
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ ld(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ lfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
if (regs2 != NULL)
for (int i = 0; i < total_args; i++) {
VMReg r_1 = regs2[i].first();
VMReg r_2 = regs2[i].second();
if (r_1->is_Register()) {
Register r = r_1->as_Register();
__ ld(r, st_off, R1_SP);
st_off -= wordSize;
} else if (r_1->is_FloatRegister()) {
FloatRegister f = r_1->as_FloatRegister();
__ lfd(f, st_off, R1_SP);
st_off -= wordSize;
}
}
__ pop_frame();
}
// Restore the registers that might be holding a result.
void RegisterSaver::restore_result_registers(MacroAssembler* masm, int frame_size_in_bytes) {
const int regstosave_num = sizeof(RegisterSaver_LiveRegs) /
sizeof(RegisterSaver::LiveRegType);
const int register_save_size = regstosave_num * reg_size; // VS registers not relevant here.
const int register_save_offset = frame_size_in_bytes - register_save_size;
// restore all result registers (ints and floats)
int offset = register_save_offset;
for (int i = 0; i < regstosave_num; i++) {
int reg_num = RegisterSaver_LiveRegs[i].reg_num;
int reg_type = RegisterSaver_LiveRegs[i].reg_type;
switch (reg_type) {
case RegisterSaver::int_reg: {
if (as_Register(reg_num)==R3_RET) // int result_reg
__ ld(as_Register(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::float_reg: {
if (as_FloatRegister(reg_num)==F1_RET) // float result_reg
__ lfd(as_FloatRegister(reg_num), offset, R1_SP);
break;
}
case RegisterSaver::special_reg: {
// Special registers don't hold a result.
break;
}
default:
ShouldNotReachHere();
}
offset += reg_size;
}
assert(offset == frame_size_in_bytes, "consistency check");
}
// Is vector's size (in bytes) bigger than a size saved by default?
bool SharedRuntime::is_wide_vector(int size) {
// Note, MaxVectorSize == 8/16 on PPC64.
assert(size <= (SuperwordUseVSX ? 16 : 8), "%d bytes vectors are not supported", size);
return size > 8;
}
size_t SharedRuntime::trampoline_size() {
return Assembler::load_const_size + 8;
}
void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {
Register Rtemp = R12;
__ load_const(Rtemp, destination);
__ mtctr(Rtemp);
__ bctr();
}
static int reg2slot(VMReg r) {
return r->reg2stack() + SharedRuntime::out_preserve_stack_slots();
}
static int reg2offset(VMReg r) {
return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
}
// ---------------------------------------------------------------------------
// Read the array of BasicTypes from a signature, and compute where the
// arguments should go. Values in the VMRegPair regs array refer to 4-byte
// quantities. Values less than VMRegImpl::stack0 are registers, those above
// refer to 4-byte stack slots. All stack slots are based off of the stack pointer
// as framesizes are fixed.
// VMRegImpl::stack0 refers to the first slot 0(sp).
// and VMRegImpl::stack0+1 refers to the memory word 4-bytes higher. Register
// up to RegisterImpl::number_of_registers) are the 64-bit
// integer registers.
// Note: the INPUTS in sig_bt are in units of Java argument words, which are
// either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
// units regardless of build. Of course for i486 there is no 64 bit build
// The Java calling convention is a "shifted" version of the C ABI.
// By skipping the first C ABI register we can call non-static jni methods
// with small numbers of arguments without having to shuffle the arguments
// at all. Since we control the java ABI we ought to at least get some
// advantage out of it.
const VMReg java_iarg_reg[8] = {
R3->as_VMReg(),
R4->as_VMReg(),
R5->as_VMReg(),
R6->as_VMReg(),
R7->as_VMReg(),
R8->as_VMReg(),
R9->as_VMReg(),
R10->as_VMReg()
};
const VMReg java_farg_reg[13] = {
F1->as_VMReg(),
F2->as_VMReg(),
F3->as_VMReg(),
F4->as_VMReg(),
F5->as_VMReg(),
F6->as_VMReg(),
F7->as_VMReg(),
F8->as_VMReg(),
F9->as_VMReg(),
F10->as_VMReg(),
F11->as_VMReg(),
F12->as_VMReg(),
F13->as_VMReg()
};
const int num_java_iarg_registers = sizeof(java_iarg_reg) / sizeof(java_iarg_reg[0]);
const int num_java_farg_registers = sizeof(java_farg_reg) / sizeof(java_farg_reg[0]);
int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
int total_args_passed) {
// C2c calling conventions for compiled-compiled calls.
// Put 8 ints/longs into registers _AND_ 13 float/doubles into
// registers _AND_ put the rest on the stack.
const int inc_stk_for_intfloat = 1; // 1 slots for ints and floats
const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles
int i;
VMReg reg;
int stk = 0;
int ireg = 0;
int freg = 0;
// We put the first 8 arguments into registers and the rest on the
// stack, float arguments are already in their argument registers
// due to c2c calling conventions (see calling_convention).
for (int i = 0; i < total_args_passed; ++i) {
switch(sig_bt[i]) {
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
if (ireg < num_java_iarg_registers) {
// Put int/ptr in register
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put int/ptr on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (ireg < num_java_iarg_registers) {
// Put long in register.
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put long on stack. They must be aligned to 2 slots.
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
if (ireg < num_java_iarg_registers) {
// Put ptr in register.
reg = java_iarg_reg[ireg];
++ireg;
} else {
// Put ptr on stack. Objects must be aligned to 2 slots too,
// because "64-bit pointers record oop-ishness on 2 aligned
// adjacent registers." (see OopFlow::build_oop_map).
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_FLOAT:
if (freg < num_java_farg_registers) {
// Put float in register.
reg = java_farg_reg[freg];
++freg;
} else {
// Put float on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (freg < num_java_farg_registers) {
// Put double in register.
reg = java_farg_reg[freg];
++freg;
} else {
// Put double on stack. They must be aligned to 2 slots.
if (stk & 0x1) ++stk;
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_VOID:
// Do not count halves.
regs[i].set_bad();
break;
default:
ShouldNotReachHere();
}
}
return align_up(stk, 2);
}
#if defined(COMPILER1) || defined(COMPILER2)
// Calling convention for calling C code.
int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
VMRegPair *regs2,
int total_args_passed) {
// Calling conventions for C runtime calls and calls to JNI native methods.
//
// PPC64 convention: Hoist the first 8 int/ptr/long's in the first 8
// int regs, leaving int regs undefined if the arg is flt/dbl. Hoist
// the first 13 flt/dbl's in the first 13 fp regs but additionally
// copy flt/dbl to the stack if they are beyond the 8th argument.
const VMReg iarg_reg[8] = {
R3->as_VMReg(),
R4->as_VMReg(),
R5->as_VMReg(),
R6->as_VMReg(),
R7->as_VMReg(),
R8->as_VMReg(),
R9->as_VMReg(),
R10->as_VMReg()
};
const VMReg farg_reg[13] = {
F1->as_VMReg(),
F2->as_VMReg(),
F3->as_VMReg(),
F4->as_VMReg(),
F5->as_VMReg(),
F6->as_VMReg(),
F7->as_VMReg(),
F8->as_VMReg(),
F9->as_VMReg(),
F10->as_VMReg(),
F11->as_VMReg(),
F12->as_VMReg(),
F13->as_VMReg()
};
// Check calling conventions consistency.
assert(sizeof(iarg_reg) / sizeof(iarg_reg[0]) == Argument::n_int_register_parameters_c &&
sizeof(farg_reg) / sizeof(farg_reg[0]) == Argument::n_float_register_parameters_c,
"consistency");
// `Stk' counts stack slots. Due to alignment, 32 bit values occupy
// 2 such slots, like 64 bit values do.
const int inc_stk_for_intfloat = 2; // 2 slots for ints and floats
const int inc_stk_for_longdouble = 2; // 2 slots for longs and doubles
int i;
VMReg reg;
// Leave room for C-compatible ABI_REG_ARGS.
int stk = (frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size;
int arg = 0;
int freg = 0;
// Avoid passing C arguments in the wrong stack slots.
#if defined(ABI_ELFv2)
assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_size == 96,
"passing C arguments in wrong stack slots");
#else
assert((SharedRuntime::out_preserve_stack_slots() + stk) * VMRegImpl::stack_slot_size == 112,
"passing C arguments in wrong stack slots");
#endif
// We fill-out regs AND regs2 if an argument must be passed in a
// register AND in a stack slot. If regs2 is NULL in such a
// situation, we bail-out with a fatal error.
for (int i = 0; i < total_args_passed; ++i, ++arg) {
// Initialize regs2 to BAD.
if (regs2 != NULL) regs2[i].set_bad();
switch(sig_bt[i]) {
//
// If arguments 0-7 are integers, they are passed in integer registers.
// Argument i is placed in iarg_reg[i].
//
case T_BOOLEAN:
case T_CHAR:
case T_BYTE:
case T_SHORT:
case T_INT:
// We must cast ints to longs and use full 64 bit stack slots
// here. Thus fall through, handle as long.
case T_LONG:
case T_OBJECT:
case T_ARRAY:
case T_ADDRESS:
case T_METADATA:
// Oops are already boxed if required (JNI).
if (arg < Argument::n_int_register_parameters_c) {
reg = iarg_reg[arg];
} else {
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
//
// Floats are treated differently from int regs: The first 13 float arguments
// are passed in registers (not the float args among the first 13 args).
// Thus argument i is NOT passed in farg_reg[i] if it is float. It is passed
// in farg_reg[j] if argument i is the j-th float argument of this call.
//
case T_FLOAT:
#if defined(LINUX)
// Linux uses ELF ABI. Both original ELF and ELFv2 ABIs have float
// in the least significant word of an argument slot.
#if defined(VM_LITTLE_ENDIAN)
#define FLOAT_WORD_OFFSET_IN_SLOT 0
#else
#define FLOAT_WORD_OFFSET_IN_SLOT 1
#endif
#elif defined(AIX)
// Although AIX runs on big endian CPU, float is in the most
// significant word of an argument slot.
#define FLOAT_WORD_OFFSET_IN_SLOT 0
#else
#error "unknown OS"
#endif
if (freg < Argument::n_float_register_parameters_c) {
// Put float in register ...
reg = farg_reg[freg];
++freg;
// Argument i for i > 8 is placed on the stack even if it's
// placed in a register (if it's a float arg). Aix disassembly
// shows that xlC places these float args on the stack AND in
// a register. This is not documented, but we follow this
// convention, too.
if (arg >= Argument::n_regs_not_on_stack_c) {
// ... and on the stack.
guarantee(regs2 != NULL, "must pass float in register and stack slot");
VMReg reg2 = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT);
regs2[i].set1(reg2);
stk += inc_stk_for_intfloat;
}
} else {
// Put float on stack.
reg = VMRegImpl::stack2reg(stk + FLOAT_WORD_OFFSET_IN_SLOT);
stk += inc_stk_for_intfloat;
}
regs[i].set1(reg);
break;
case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "expecting half");
if (freg < Argument::n_float_register_parameters_c) {
// Put double in register ...
reg = farg_reg[freg];
++freg;
// Argument i for i > 8 is placed on the stack even if it's
// placed in a register (if it's a double arg). Aix disassembly
// shows that xlC places these float args on the stack AND in
// a register. This is not documented, but we follow this
// convention, too.
if (arg >= Argument::n_regs_not_on_stack_c) {
// ... and on the stack.
guarantee(regs2 != NULL, "must pass float in register and stack slot");
VMReg reg2 = VMRegImpl::stack2reg(stk);
regs2[i].set2(reg2);
stk += inc_stk_for_longdouble;
}
} else {
// Put double on stack.
reg = VMRegImpl::stack2reg(stk);
stk += inc_stk_for_longdouble;
}
regs[i].set2(reg);
break;
case T_VOID:
// Do not count halves.
regs[i].set_bad();
--arg;
break;
default:
ShouldNotReachHere();
}
}
return align_up(stk, 2);
}
#endif // COMPILER2
static address gen_c2i_adapter(MacroAssembler *masm,
int total_args_passed,
int comp_args_on_stack,
const BasicType *sig_bt,
const VMRegPair *regs,
Label& call_interpreter,
const Register& ientry) {
address c2i_entrypoint;
const Register sender_SP = R21_sender_SP; // == R21_tmp1
const Register code = R22_tmp2;
//const Register ientry = R23_tmp3;
const Register value_regs[] = { R24_tmp4, R25_tmp5, R26_tmp6 };
const int num_value_regs = sizeof(value_regs) / sizeof(Register);
int value_regs_index = 0;
const Register return_pc = R27_tmp7;
const Register tmp = R28_tmp8;
assert_different_registers(sender_SP, code, ientry, return_pc, tmp);
// Adapter needs TOP_IJAVA_FRAME_ABI.
const int adapter_size = frame::top_ijava_frame_abi_size +
align_up(total_args_passed * wordSize, frame::alignment_in_bytes);
// regular (verified) c2i entry point
c2i_entrypoint = __ pc();
// Does compiled code exists? If yes, patch the caller's callsite.
__ ld(code, method_(code));
__ cmpdi(CCR0, code, 0);
__ ld(ientry, method_(interpreter_entry)); // preloaded
__ beq(CCR0, call_interpreter);
// Patch caller's callsite, method_(code) was not NULL which means that
// compiled code exists.
__ mflr(return_pc);
__ std(return_pc, _abi0(lr), R1_SP);
RegisterSaver::push_frame_and_save_argument_registers(masm, tmp, adapter_size, total_args_passed, regs);
__ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), R19_method, return_pc);
RegisterSaver::restore_argument_registers_and_pop_frame(masm, adapter_size, total_args_passed, regs);
__ ld(return_pc, _abi0(lr), R1_SP);
__ ld(ientry, method_(interpreter_entry)); // preloaded
__ mtlr(return_pc);
// Call the interpreter.
__ BIND(call_interpreter);
__ mtctr(ientry);
// Get a copy of the current SP for loading caller's arguments.
__ mr(sender_SP, R1_SP);
// Add space for the adapter.
__ resize_frame(-adapter_size, R12_scratch2);
int st_off = adapter_size - wordSize;
// Write the args into the outgoing interpreter space.
for (int i = 0; i < total_args_passed; i++) {
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second();
if (!r_1->is_valid()) {
assert(!r_2->is_valid(), "");
continue;
}
if (r_1->is_stack()) {
Register tmp_reg = value_regs[value_regs_index];