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assembler_x86.hpp
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assembler_x86.hpp
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/*
* Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#ifndef CPU_X86_ASSEMBLER_X86_HPP
#define CPU_X86_ASSEMBLER_X86_HPP
#include "asm/register.hpp"
#include "runtime/vm_version.hpp"
#include "utilities/powerOfTwo.hpp"
class BiasedLockingCounters;
// Contains all the definitions needed for x86 assembly code generation.
// Calling convention
class Argument {
public:
enum {
#ifdef _LP64
#ifdef _WIN64
n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
#else
n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
#endif // _WIN64
n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
#else
n_register_parameters = 0 // 0 registers used to pass arguments
#endif // _LP64
};
};
#ifdef _LP64
// Symbolically name the register arguments used by the c calling convention.
// Windows is different from linux/solaris. So much for standards...
#ifdef _WIN64
REGISTER_DECLARATION(Register, c_rarg0, rcx);
REGISTER_DECLARATION(Register, c_rarg1, rdx);
REGISTER_DECLARATION(Register, c_rarg2, r8);
REGISTER_DECLARATION(Register, c_rarg3, r9);
REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
#else
REGISTER_DECLARATION(Register, c_rarg0, rdi);
REGISTER_DECLARATION(Register, c_rarg1, rsi);
REGISTER_DECLARATION(Register, c_rarg2, rdx);
REGISTER_DECLARATION(Register, c_rarg3, rcx);
REGISTER_DECLARATION(Register, c_rarg4, r8);
REGISTER_DECLARATION(Register, c_rarg5, r9);
REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
#endif // _WIN64
// Symbolically name the register arguments used by the Java calling convention.
// We have control over the convention for java so we can do what we please.
// What pleases us is to offset the java calling convention so that when
// we call a suitable jni method the arguments are lined up and we don't
// have to do little shuffling. A suitable jni method is non-static and a
// small number of arguments (two fewer args on windows)
//
// |-------------------------------------------------------|
// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
// |-------------------------------------------------------|
// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
// | rdi rsi rdx rcx r8 r9 | solaris/linux
// |-------------------------------------------------------|
// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
// |-------------------------------------------------------|
REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
// Windows runs out of register args here
#ifdef _WIN64
REGISTER_DECLARATION(Register, j_rarg3, rdi);
REGISTER_DECLARATION(Register, j_rarg4, rsi);
#else
REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
#endif /* _WIN64 */
REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
#else
// rscratch1 will apear in 32bit code that is dead but of course must compile
// Using noreg ensures if the dead code is incorrectly live and executed it
// will cause an assertion failure
#define rscratch1 noreg
#define rscratch2 noreg
#endif // _LP64
// JSR 292
// On x86, the SP does not have to be saved when invoking method handle intrinsics
// or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
// Address is an abstraction used to represent a memory location
// using any of the amd64 addressing modes with one object.
//
// Note: A register location is represented via a Register, not
// via an address for efficiency & simplicity reasons.
class ArrayAddress;
class Address {
public:
enum ScaleFactor {
no_scale = -1,
times_1 = 0,
times_2 = 1,
times_4 = 2,
times_8 = 3,
times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
};
static ScaleFactor times(int size) {
assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
if (size == 8) return times_8;
if (size == 4) return times_4;
if (size == 2) return times_2;
return times_1;
}
static int scale_size(ScaleFactor scale) {
assert(scale != no_scale, "");
assert(((1 << (int)times_1) == 1 &&
(1 << (int)times_2) == 2 &&
(1 << (int)times_4) == 4 &&
(1 << (int)times_8) == 8), "");
return (1 << (int)scale);
}
private:
Register _base;
Register _index;
XMMRegister _xmmindex;
ScaleFactor _scale;
int _disp;
bool _isxmmindex;
RelocationHolder _rspec;
// Easily misused constructors make them private
// %%% can we make these go away?
NOT_LP64(Address(address loc, RelocationHolder spec);)
Address(int disp, address loc, relocInfo::relocType rtype);
Address(int disp, address loc, RelocationHolder spec);
public:
int disp() { return _disp; }
// creation
Address()
: _base(noreg),
_index(noreg),
_xmmindex(xnoreg),
_scale(no_scale),
_disp(0),
_isxmmindex(false){
}
// No default displacement otherwise Register can be implicitly
// converted to 0(Register) which is quite a different animal.
Address(Register base, int disp)
: _base(base),
_index(noreg),
_xmmindex(xnoreg),
_scale(no_scale),
_disp(disp),
_isxmmindex(false){
}
Address(Register base, Register index, ScaleFactor scale, int disp = 0)
: _base (base),
_index(index),
_xmmindex(xnoreg),
_scale(scale),
_disp (disp),
_isxmmindex(false) {
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
: _base (base),
_index(index.register_or_noreg()),
_xmmindex(xnoreg),
_scale(scale),
_disp (disp + (index.constant_or_zero() * scale_size(scale))),
_isxmmindex(false){
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
: _base (base),
_index(noreg),
_xmmindex(index),
_scale(scale),
_disp(disp),
_isxmmindex(true) {
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address plus_disp(int disp) const {
Address a = (*this);
a._disp += disp;
return a;
}
Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
Address a = (*this);
a._disp += disp.constant_or_zero() * scale_size(scale);
if (disp.is_register()) {
assert(!a.index()->is_valid(), "competing indexes");
a._index = disp.as_register();
a._scale = scale;
}
return a;
}
bool is_same_address(Address a) const {
// disregard _rspec
return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
}
// The following two overloads are used in connection with the
// ByteSize type (see sizes.hpp). They simplify the use of
// ByteSize'd arguments in assembly code. Note that their equivalent
// for the optimized build are the member functions with int disp
// argument since ByteSize is mapped to an int type in that case.
//
// Note: DO NOT introduce similar overloaded functions for WordSize
// arguments as in the optimized mode, both ByteSize and WordSize
// are mapped to the same type and thus the compiler cannot make a
// distinction anymore (=> compiler errors).
#ifdef ASSERT
Address(Register base, ByteSize disp)
: _base(base),
_index(noreg),
_xmmindex(xnoreg),
_scale(no_scale),
_disp(in_bytes(disp)),
_isxmmindex(false){
}
Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
: _base(base),
_index(index),
_xmmindex(xnoreg),
_scale(scale),
_disp(in_bytes(disp)),
_isxmmindex(false){
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
: _base (base),
_index(index.register_or_noreg()),
_xmmindex(xnoreg),
_scale(scale),
_disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
_isxmmindex(false) {
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
#endif // ASSERT
// accessors
bool uses(Register reg) const { return _base == reg || _index == reg; }
Register base() const { return _base; }
Register index() const { return _index; }
XMMRegister xmmindex() const { return _xmmindex; }
ScaleFactor scale() const { return _scale; }
int disp() const { return _disp; }
bool isxmmindex() const { return _isxmmindex; }
// Convert the raw encoding form into the form expected by the constructor for
// Address. An index of 4 (rsp) corresponds to having no index, so convert
// that to noreg for the Address constructor.
static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
static Address make_array(ArrayAddress);
private:
bool base_needs_rex() const {
return _base->is_valid() && _base->encoding() >= 8;
}
bool index_needs_rex() const {
return _index->is_valid() &&_index->encoding() >= 8;
}
bool xmmindex_needs_rex() const {
return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
}
relocInfo::relocType reloc() const { return _rspec.type(); }
friend class Assembler;
friend class MacroAssembler;
friend class LIR_Assembler; // base/index/scale/disp
};
//
// AddressLiteral has been split out from Address because operands of this type
// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
// the few instructions that need to deal with address literals are unique and the
// MacroAssembler does not have to implement every instruction in the Assembler
// in order to search for address literals that may need special handling depending
// on the instruction and the platform. As small step on the way to merging i486/amd64
// directories.
//
class AddressLiteral {
friend class ArrayAddress;
RelocationHolder _rspec;
// Typically we use AddressLiterals we want to use their rval
// However in some situations we want the lval (effect address) of the item.
// We provide a special factory for making those lvals.
bool _is_lval;
// If the target is far we'll need to load the ea of this to
// a register to reach it. Otherwise if near we can do rip
// relative addressing.
address _target;
protected:
// creation
AddressLiteral()
: _is_lval(false),
_target(NULL)
{}
public:
AddressLiteral(address target, relocInfo::relocType rtype);
AddressLiteral(address target, RelocationHolder const& rspec)
: _rspec(rspec),
_is_lval(false),
_target(target)
{}
AddressLiteral addr() {
AddressLiteral ret = *this;
ret._is_lval = true;
return ret;
}
private:
address target() { return _target; }
bool is_lval() { return _is_lval; }
relocInfo::relocType reloc() const { return _rspec.type(); }
const RelocationHolder& rspec() const { return _rspec; }
friend class Assembler;
friend class MacroAssembler;
friend class Address;
friend class LIR_Assembler;
};
// Convience classes
class RuntimeAddress: public AddressLiteral {
public:
RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
};
class ExternalAddress: public AddressLiteral {
private:
static relocInfo::relocType reloc_for_target(address target) {
// Sometimes ExternalAddress is used for values which aren't
// exactly addresses, like the card table base.
// external_word_type can't be used for values in the first page
// so just skip the reloc in that case.
return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
}
public:
ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
};
class InternalAddress: public AddressLiteral {
public:
InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
};
// x86 can do array addressing as a single operation since disp can be an absolute
// address amd64 can't. We create a class that expresses the concept but does extra
// magic on amd64 to get the final result
class ArrayAddress {
private:
AddressLiteral _base;
Address _index;
public:
ArrayAddress() {};
ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
AddressLiteral base() { return _base; }
Address index() { return _index; }
};
class InstructionAttr;
// 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
// See fxsave and xsave(EVEX enabled) documentation for layout
const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
// is what you get. The Assembler is generating code into a CodeBuffer.
class Assembler : public AbstractAssembler {
friend class AbstractAssembler; // for the non-virtual hack
friend class LIR_Assembler; // as_Address()
friend class StubGenerator;
public:
enum Condition { // The x86 condition codes used for conditional jumps/moves.
zero = 0x4,
notZero = 0x5,
equal = 0x4,
notEqual = 0x5,
less = 0xc,
lessEqual = 0xe,
greater = 0xf,
greaterEqual = 0xd,
below = 0x2,
belowEqual = 0x6,
above = 0x7,
aboveEqual = 0x3,
overflow = 0x0,
noOverflow = 0x1,
carrySet = 0x2,
carryClear = 0x3,
negative = 0x8,
positive = 0x9,
parity = 0xa,
noParity = 0xb
};
enum Prefix {
// segment overrides
CS_segment = 0x2e,
SS_segment = 0x36,
DS_segment = 0x3e,
ES_segment = 0x26,
FS_segment = 0x64,
GS_segment = 0x65,
REX = 0x40,
REX_B = 0x41,
REX_X = 0x42,
REX_XB = 0x43,
REX_R = 0x44,
REX_RB = 0x45,
REX_RX = 0x46,
REX_RXB = 0x47,
REX_W = 0x48,
REX_WB = 0x49,
REX_WX = 0x4A,
REX_WXB = 0x4B,
REX_WR = 0x4C,
REX_WRB = 0x4D,
REX_WRX = 0x4E,
REX_WRXB = 0x4F,
VEX_3bytes = 0xC4,
VEX_2bytes = 0xC5,
EVEX_4bytes = 0x62,
Prefix_EMPTY = 0x0
};
enum VexPrefix {
VEX_B = 0x20,
VEX_X = 0x40,
VEX_R = 0x80,
VEX_W = 0x80
};
enum ExexPrefix {
EVEX_F = 0x04,
EVEX_V = 0x08,
EVEX_Rb = 0x10,
EVEX_X = 0x40,
EVEX_Z = 0x80
};
enum VexSimdPrefix {
VEX_SIMD_NONE = 0x0,
VEX_SIMD_66 = 0x1,
VEX_SIMD_F3 = 0x2,
VEX_SIMD_F2 = 0x3
};
enum VexOpcode {
VEX_OPCODE_NONE = 0x0,
VEX_OPCODE_0F = 0x1,
VEX_OPCODE_0F_38 = 0x2,
VEX_OPCODE_0F_3A = 0x3,
VEX_OPCODE_MASK = 0x1F
};
enum AvxVectorLen {
AVX_128bit = 0x0,
AVX_256bit = 0x1,
AVX_512bit = 0x2,
AVX_NoVec = 0x4
};
enum EvexTupleType {
EVEX_FV = 0,
EVEX_HV = 4,
EVEX_FVM = 6,
EVEX_T1S = 7,
EVEX_T1F = 11,
EVEX_T2 = 13,
EVEX_T4 = 15,
EVEX_T8 = 17,
EVEX_HVM = 18,
EVEX_QVM = 19,
EVEX_OVM = 20,
EVEX_M128 = 21,
EVEX_DUP = 22,
EVEX_ETUP = 23
};
enum EvexInputSizeInBits {
EVEX_8bit = 0,
EVEX_16bit = 1,
EVEX_32bit = 2,
EVEX_64bit = 3,
EVEX_NObit = 4
};
enum WhichOperand {
// input to locate_operand, and format code for relocations
imm_operand = 0, // embedded 32-bit|64-bit immediate operand
disp32_operand = 1, // embedded 32-bit displacement or address
call32_operand = 2, // embedded 32-bit self-relative displacement
#ifndef _LP64
_WhichOperand_limit = 3
#else
narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
_WhichOperand_limit = 4
#endif
};
enum ComparisonPredicate {
eq = 0,
lt = 1,
le = 2,
_false = 3,
neq = 4,
nlt = 5,
nle = 6,
_true = 7
};
//---< calculate length of instruction >---
// As instruction size can't be found out easily on x86/x64,
// we just use '4' for len and maxlen.
// instruction must start at passed address
static unsigned int instr_len(unsigned char *instr) { return 4; }
//---< longest instructions >---
// Max instruction length is not specified in architecture documentation.
// We could use a "safe enough" estimate (15), but just default to
// instruction length guess from above.
static unsigned int instr_maxlen() { return 4; }
// NOTE: The general philopsophy of the declarations here is that 64bit versions
// of instructions are freely declared without the need for wrapping them an ifdef.
// (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
// In the .cpp file the implementations are wrapped so that they are dropped out
// of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
// to the size it was prior to merging up the 32bit and 64bit assemblers.
//
// This does mean you'll get a linker/runtime error if you use a 64bit only instruction
// in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
private:
bool _legacy_mode_bw;
bool _legacy_mode_dq;
bool _legacy_mode_vl;
bool _legacy_mode_vlbw;
NOT_LP64(bool _is_managed;)
class InstructionAttr *_attributes;
// 64bit prefixes
int prefix_and_encode(int reg_enc, bool byteinst = false);
int prefixq_and_encode(int reg_enc);
int prefix_and_encode(int dst_enc, int src_enc) {
return prefix_and_encode(dst_enc, false, src_enc, false);
}
int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
int prefixq_and_encode(int dst_enc, int src_enc);
void prefix(Register reg);
void prefix(Register dst, Register src, Prefix p);
void prefix(Register dst, Address adr, Prefix p);
void prefix(Address adr);
void prefixq(Address adr);
void prefix(Address adr, Register reg, bool byteinst = false);
void prefix(Address adr, XMMRegister reg);
void prefixq(Address adr, Register reg);
void prefixq(Address adr, XMMRegister reg);
void prefetch_prefix(Address src);
void rex_prefix(Address adr, XMMRegister xreg,
VexSimdPrefix pre, VexOpcode opc, bool rex_w);
int rex_prefix_and_encode(int dst_enc, int src_enc,
VexSimdPrefix pre, VexOpcode opc, bool rex_w);
void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
int nds_enc, VexSimdPrefix pre, VexOpcode opc);
void vex_prefix(Address adr, int nds_enc, int xreg_enc,
VexSimdPrefix pre, VexOpcode opc,
InstructionAttr *attributes);
int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
VexSimdPrefix pre, VexOpcode opc,
InstructionAttr *attributes);
void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
VexOpcode opc, InstructionAttr *attributes);
int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
VexOpcode opc, InstructionAttr *attributes);
// Helper functions for groups of instructions
void emit_arith_b(int op1, int op2, Register dst, int imm8);
void emit_arith(int op1, int op2, Register dst, int32_t imm32);
// Force generation of a 4 byte immediate value even if it fits into 8bit
void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
void emit_arith(int op1, int op2, Register dst, Register src);
bool emit_compressed_disp_byte(int &disp);
void emit_operand(Register reg,
Register base, Register index, Address::ScaleFactor scale,
int disp,
RelocationHolder const& rspec,
int rip_relative_correction = 0);
void emit_operand(XMMRegister reg, Register base, XMMRegister index,
Address::ScaleFactor scale,
int disp, RelocationHolder const& rspec);
void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
// operands that only take the original 32bit registers
void emit_operand32(Register reg, Address adr);
void emit_operand(XMMRegister reg,
Register base, Register index, Address::ScaleFactor scale,
int disp,
RelocationHolder const& rspec);
void emit_operand(XMMRegister reg, Address adr);
void emit_operand(MMXRegister reg, Address adr);
// workaround gcc (3.2.1-7) bug
void emit_operand(Address adr, MMXRegister reg);
// Immediate-to-memory forms
void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
void emit_farith(int b1, int b2, int i);
protected:
#ifdef ASSERT
void check_relocation(RelocationHolder const& rspec, int format);
#endif
void emit_data(jint data, relocInfo::relocType rtype, int format);
void emit_data(jint data, RelocationHolder const& rspec, int format);
void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
// These are all easily abused and hence protected
// 32BIT ONLY SECTION
#ifndef _LP64
// Make these disappear in 64bit mode since they would never be correct
void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
#else
// 64BIT ONLY SECTION
void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
#endif // _LP64
// These are unique in that we are ensured by the caller that the 32bit
// relative in these instructions will always be able to reach the potentially
// 64bit address described by entry. Since they can take a 64bit address they
// don't have the 32 suffix like the other instructions in this class.
void call_literal(address entry, RelocationHolder const& rspec);
void jmp_literal(address entry, RelocationHolder const& rspec);
// Avoid using directly section
// Instructions in this section are actually usable by anyone without danger
// of failure but have performance issues that are addressed my enhanced
// instructions which will do the proper thing base on the particular cpu.
// We protect them because we don't trust you...
// Don't use next inc() and dec() methods directly. INC & DEC instructions
// could cause a partial flag stall since they don't set CF flag.
// Use MacroAssembler::decrement() & MacroAssembler::increment() methods
// which call inc() & dec() or add() & sub() in accordance with
// the product flag UseIncDec value.
void decl(Register dst);
void decl(Address dst);
void decq(Register dst);
void decq(Address dst);
void incl(Register dst);
void incl(Address dst);
void incq(Register dst);
void incq(Address dst);
// New cpus require use of movsd and movss to avoid partial register stall
// when loading from memory. But for old Opteron use movlpd instead of movsd.
// The selection is done in MacroAssembler::movdbl() and movflt().
// Move Scalar Single-Precision Floating-Point Values
void movss(XMMRegister dst, Address src);
void movss(XMMRegister dst, XMMRegister src);
void movss(Address dst, XMMRegister src);
// Move Scalar Double-Precision Floating-Point Values
void movsd(XMMRegister dst, Address src);
void movsd(XMMRegister dst, XMMRegister src);
void movsd(Address dst, XMMRegister src);
void movlpd(XMMRegister dst, Address src);
// New cpus require use of movaps and movapd to avoid partial register stall
// when moving between registers.
void movaps(XMMRegister dst, XMMRegister src);
void movapd(XMMRegister dst, XMMRegister src);
// End avoid using directly
// Instruction prefixes
void prefix(Prefix p);
public:
// Creation
Assembler(CodeBuffer* code) : AbstractAssembler(code) {
init_attributes();
}
// Decoding
static address locate_operand(address inst, WhichOperand which);
static address locate_next_instruction(address inst);
// Utilities
static bool is_polling_page_far() NOT_LP64({ return false;});
static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
int cur_tuple_type, int in_size_in_bits, int cur_encoding);
// Generic instructions
// Does 32bit or 64bit as needed for the platform. In some sense these
// belong in macro assembler but there is no need for both varieties to exist
void init_attributes(void) {
_legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
_legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
_legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
_legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
NOT_LP64(_is_managed = false;)
_attributes = NULL;
}
void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
void clear_attributes(void) { _attributes = NULL; }
void set_managed(void) { NOT_LP64(_is_managed = true;) }
void clear_managed(void) { NOT_LP64(_is_managed = false;) }
bool is_managed(void) {
NOT_LP64(return _is_managed;)
LP64_ONLY(return false;) }
void lea(Register dst, Address src);
void mov(Register dst, Register src);
#ifdef _LP64
// support caching the result of some routines
// must be called before pusha(), popa(), vzeroupper() - checked with asserts
static void precompute_instructions();
void pusha_uncached();
void popa_uncached();
#endif
void vzeroupper_uncached();
void pusha();
void popa();
void pushf();
void popf();
void push(int32_t imm32);
void push(Register src);
void pop(Register dst);
// These are dummies to prevent surprise implicit conversions to Register
void push(void* v);
void pop(void* v);
// These do register sized moves/scans
void rep_mov();
void rep_stos();
void rep_stosb();
void repne_scan();
#ifdef _LP64
void repne_scanl();
#endif
// Vanilla instructions in lexical order
void adcl(Address dst, int32_t imm32);
void adcl(Address dst, Register src);
void adcl(Register dst, int32_t imm32);
void adcl(Register dst, Address src);
void adcl(Register dst, Register src);
void adcq(Register dst, int32_t imm32);
void adcq(Register dst, Address src);
void adcq(Register dst, Register src);
void addb(Address dst, int imm8);
void addw(Address dst, int imm16);
void addl(Address dst, int32_t imm32);
void addl(Address dst, Register src);
void addl(Register dst, int32_t imm32);
void addl(Register dst, Address src);
void addl(Register dst, Register src);
void addq(Address dst, int32_t imm32);
void addq(Address dst, Register src);
void addq(Register dst, int32_t imm32);
void addq(Register dst, Address src);
void addq(Register dst, Register src);
#ifdef _LP64
//Add Unsigned Integers with Carry Flag
void adcxq(Register dst, Register src);
//Add Unsigned Integers with Overflow Flag
void adoxq(Register dst, Register src);
#endif
void addr_nop_4();
void addr_nop_5();
void addr_nop_7();
void addr_nop_8();
// Add Scalar Double-Precision Floating-Point Values
void addsd(XMMRegister dst, Address src);
void addsd(XMMRegister dst, XMMRegister src);
// Add Scalar Single-Precision Floating-Point Values
void addss(XMMRegister dst, Address src);
void addss(XMMRegister dst, XMMRegister src);
// AES instructions
void aesdec(XMMRegister dst, Address src);
void aesdec(XMMRegister dst, XMMRegister src);
void aesdeclast(XMMRegister dst, Address src);
void aesdeclast(XMMRegister dst, XMMRegister src);
void aesenc(XMMRegister dst, Address src);
void aesenc(XMMRegister dst, XMMRegister src);
void aesenclast(XMMRegister dst, Address src);
void aesenclast(XMMRegister dst, XMMRegister src);
// Vector AES instructions
void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void andl(Address dst, int32_t imm32);
void andl(Register dst, int32_t imm32);
void andl(Register dst, Address src);
void andl(Register dst, Register src);
void andq(Address dst, int32_t imm32);
void andq(Register dst, int32_t imm32);
void andq(Register dst, Address src);
void andq(Register dst, Register src);
// BMI instructions
void andnl(Register dst, Register src1, Register src2);