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c1_LIRAssembler_aarch64.cpp
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c1_LIRAssembler_aarch64.cpp
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/*
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/macroAssembler.inline.hpp"
#include "asm/assembler.hpp"
#include "c1/c1_CodeStubs.hpp"
#include "c1/c1_Compilation.hpp"
#include "c1/c1_LIRAssembler.hpp"
#include "c1/c1_MacroAssembler.hpp"
#include "c1/c1_Runtime1.hpp"
#include "c1/c1_ValueStack.hpp"
#include "ci/ciArrayKlass.hpp"
#include "ci/ciInstance.hpp"
#include "code/compiledIC.hpp"
#include "gc/shared/collectedHeap.hpp"
#include "gc/shared/gc_globals.hpp"
#include "nativeInst_aarch64.hpp"
#include "oops/objArrayKlass.hpp"
#include "runtime/frame.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "utilities/powerOfTwo.hpp"
#include "vmreg_aarch64.inline.hpp"
#ifndef PRODUCT
#define COMMENT(x) do { __ block_comment(x); } while (0)
#else
#define COMMENT(x)
#endif
NEEDS_CLEANUP // remove this definitions ?
const Register IC_Klass = rscratch2; // where the IC klass is cached
const Register SYNC_header = r0; // synchronization header
const Register SHIFT_count = r0; // where count for shift operations must be
#define __ _masm->
static void select_different_registers(Register preserve,
Register extra,
Register &tmp1,
Register &tmp2) {
if (tmp1 == preserve) {
assert_different_registers(tmp1, tmp2, extra);
tmp1 = extra;
} else if (tmp2 == preserve) {
assert_different_registers(tmp1, tmp2, extra);
tmp2 = extra;
}
assert_different_registers(preserve, tmp1, tmp2);
}
static void select_different_registers(Register preserve,
Register extra,
Register &tmp1,
Register &tmp2,
Register &tmp3) {
if (tmp1 == preserve) {
assert_different_registers(tmp1, tmp2, tmp3, extra);
tmp1 = extra;
} else if (tmp2 == preserve) {
assert_different_registers(tmp1, tmp2, tmp3, extra);
tmp2 = extra;
} else if (tmp3 == preserve) {
assert_different_registers(tmp1, tmp2, tmp3, extra);
tmp3 = extra;
}
assert_different_registers(preserve, tmp1, tmp2, tmp3);
}
bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
LIR_Opr LIR_Assembler::receiverOpr() {
return FrameMap::receiver_opr;
}
LIR_Opr LIR_Assembler::osrBufferPointer() {
return FrameMap::as_pointer_opr(receiverOpr()->as_register());
}
//--------------fpu register translations-----------------------
address LIR_Assembler::float_constant(float f) {
address const_addr = __ float_constant(f);
if (const_addr == NULL) {
bailout("const section overflow");
return __ code()->consts()->start();
} else {
return const_addr;
}
}
address LIR_Assembler::double_constant(double d) {
address const_addr = __ double_constant(d);
if (const_addr == NULL) {
bailout("const section overflow");
return __ code()->consts()->start();
} else {
return const_addr;
}
}
address LIR_Assembler::int_constant(jlong n) {
address const_addr = __ long_constant(n);
if (const_addr == NULL) {
bailout("const section overflow");
return __ code()->consts()->start();
} else {
return const_addr;
}
}
void LIR_Assembler::breakpoint() { Unimplemented(); }
void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
//-------------------------------------------
static Register as_reg(LIR_Opr op) {
return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
}
static jlong as_long(LIR_Opr data) {
jlong result;
switch (data->type()) {
case T_INT:
result = (data->as_jint());
break;
case T_LONG:
result = (data->as_jlong());
break;
default:
ShouldNotReachHere();
result = 0; // unreachable
}
return result;
}
Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
Register base = addr->base()->as_pointer_register();
LIR_Opr opr = addr->index();
if (opr->is_cpu_register()) {
Register index;
if (opr->is_single_cpu())
index = opr->as_register();
else
index = opr->as_register_lo();
assert(addr->disp() == 0, "must be");
switch(opr->type()) {
case T_INT:
return Address(base, index, Address::sxtw(addr->scale()));
case T_LONG:
return Address(base, index, Address::lsl(addr->scale()));
default:
ShouldNotReachHere();
}
} else {
assert(addr->scale() == 0,
"expected for immediate operand, was: %d", addr->scale());
ptrdiff_t offset = ptrdiff_t(addr->disp());
// NOTE: Does not handle any 16 byte vector access.
const uint type_size = type2aelembytes(addr->type(), true);
return __ legitimize_address(Address(base, offset), type_size, tmp);
}
return Address();
}
Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
ShouldNotReachHere();
return Address();
}
Address LIR_Assembler::as_Address(LIR_Address* addr) {
return as_Address(addr, rscratch1);
}
Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
return as_Address(addr, rscratch1); // Ouch
// FIXME: This needs to be much more clever. See x86.
}
// Ensure a valid Address (base + offset) to a stack-slot. If stack access is
// not encodable as a base + (immediate) offset, generate an explicit address
// calculation to hold the address in a temporary register.
Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
precond(size == 4 || size == 8);
Address addr = frame_map()->address_for_slot(index, adjust);
precond(addr.getMode() == Address::base_plus_offset);
precond(addr.base() == sp);
precond(addr.offset() > 0);
uint mask = size - 1;
assert((addr.offset() & mask) == 0, "scaled offsets only");
return __ legitimize_address(addr, size, tmp);
}
void LIR_Assembler::osr_entry() {
offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
BlockBegin* osr_entry = compilation()->hir()->osr_entry();
ValueStack* entry_state = osr_entry->state();
int number_of_locks = entry_state->locks_size();
// we jump here if osr happens with the interpreter
// state set up to continue at the beginning of the
// loop that triggered osr - in particular, we have
// the following registers setup:
//
// r2: osr buffer
//
// build frame
ciMethod* m = compilation()->method();
__ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes(), compilation()->max_monitors());
// OSR buffer is
//
// locals[nlocals-1..0]
// monitors[0..number_of_locks]
//
// locals is a direct copy of the interpreter frame so in the osr buffer
// so first slot in the local array is the last local from the interpreter
// and last slot is local[0] (receiver) from the interpreter
//
// Similarly with locks. The first lock slot in the osr buffer is the nth lock
// from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
// in the interpreter frame (the method lock if a sync method)
// Initialize monitors in the compiled activation.
// r2: pointer to osr buffer
//
// All other registers are dead at this point and the locals will be
// copied into place by code emitted in the IR.
Register OSR_buf = osrBufferPointer()->as_pointer_register();
{ assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
int monitor_offset = BytesPerWord * method()->max_locals() +
(2 * BytesPerWord) * (number_of_locks - 1);
// SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
// the OSR buffer using 2 word entries: first the lock and then
// the oop.
for (int i = 0; i < number_of_locks; i++) {
int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
#ifdef ASSERT
// verify the interpreter's monitor has a non-null object
{
Label L;
__ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
__ cbnz(rscratch1, L);
__ stop("locked object is NULL");
__ bind(L);
}
#endif
__ ldp(r19, r20, Address(OSR_buf, slot_offset));
__ str(r19, frame_map()->address_for_monitor_lock(i));
__ str(r20, frame_map()->address_for_monitor_object(i));
}
}
}
// inline cache check; done before the frame is built.
int LIR_Assembler::check_icache() {
Register receiver = FrameMap::receiver_opr->as_register();
Register ic_klass = IC_Klass;
int start_offset = __ offset();
__ inline_cache_check(receiver, ic_klass);
// if icache check fails, then jump to runtime routine
// Note: RECEIVER must still contain the receiver!
Label dont;
__ br(Assembler::EQ, dont);
__ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
// We align the verified entry point unless the method body
// (including its inline cache check) will fit in a single 64-byte
// icache line.
if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
// force alignment after the cache check.
__ align(CodeEntryAlignment);
}
__ bind(dont);
return start_offset;
}
void LIR_Assembler::clinit_barrier(ciMethod* method) {
assert(VM_Version::supports_fast_class_init_checks(), "sanity");
assert(!method->holder()->is_not_initialized(), "initialization should have been started");
Label L_skip_barrier;
__ mov_metadata(rscratch2, method->holder()->constant_encoding());
__ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
__ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
__ bind(L_skip_barrier);
}
void LIR_Assembler::jobject2reg(jobject o, Register reg) {
if (o == NULL) {
__ mov(reg, zr);
} else {
__ movoop(reg, o);
}
}
void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
address target = NULL;
relocInfo::relocType reloc_type = relocInfo::none;
switch (patching_id(info)) {
case PatchingStub::access_field_id:
target = Runtime1::entry_for(Runtime1::access_field_patching_id);
reloc_type = relocInfo::section_word_type;
break;
case PatchingStub::load_klass_id:
target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
reloc_type = relocInfo::metadata_type;
break;
case PatchingStub::load_mirror_id:
target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
reloc_type = relocInfo::oop_type;
break;
case PatchingStub::load_appendix_id:
target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
reloc_type = relocInfo::oop_type;
break;
default: ShouldNotReachHere();
}
__ far_call(RuntimeAddress(target));
add_call_info_here(info);
}
void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
deoptimize_trap(info);
}
// This specifies the rsp decrement needed to build the frame
int LIR_Assembler::initial_frame_size_in_bytes() const {
// if rounding, must let FrameMap know!
return in_bytes(frame_map()->framesize_in_bytes());
}
int LIR_Assembler::emit_exception_handler() {
// generate code for exception handler
address handler_base = __ start_a_stub(exception_handler_size());
if (handler_base == NULL) {
// not enough space left for the handler
bailout("exception handler overflow");
return -1;
}
int offset = code_offset();
// the exception oop and pc are in r0, and r3
// no other registers need to be preserved, so invalidate them
__ invalidate_registers(false, true, true, false, true, true);
// check that there is really an exception
__ verify_not_null_oop(r0);
// search an exception handler (r0: exception oop, r3: throwing pc)
__ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
__ should_not_reach_here();
guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
// Emit the code to remove the frame from the stack in the exception
// unwind path.
int LIR_Assembler::emit_unwind_handler() {
#ifndef PRODUCT
if (CommentedAssembly) {
_masm->block_comment("Unwind handler");
}
#endif
int offset = code_offset();
// Fetch the exception from TLS and clear out exception related thread state
__ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
__ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
__ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
__ bind(_unwind_handler_entry);
__ verify_not_null_oop(r0);
if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
__ mov(r19, r0); // Preserve the exception
}
// Perform needed unlocking
MonitorExitStub* stub = NULL;
if (method()->is_synchronized()) {
monitor_address(0, FrameMap::r0_opr);
stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
if (UseHeavyMonitors) {
__ b(*stub->entry());
} else {
__ unlock_object(r5, r4, r0, *stub->entry());
}
__ bind(*stub->continuation());
}
if (compilation()->env()->dtrace_method_probes()) {
__ mov(c_rarg0, rthread);
__ mov_metadata(c_rarg1, method()->constant_encoding());
__ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
}
if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
__ mov(r0, r19); // Restore the exception
}
// remove the activation and dispatch to the unwind handler
__ block_comment("remove_frame and dispatch to the unwind handler");
__ remove_frame(initial_frame_size_in_bytes());
__ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
// Emit the slow path assembly
if (stub != NULL) {
stub->emit_code(this);
}
return offset;
}
int LIR_Assembler::emit_deopt_handler() {
// generate code for exception handler
address handler_base = __ start_a_stub(deopt_handler_size());
if (handler_base == NULL) {
// not enough space left for the handler
bailout("deopt handler overflow");
return -1;
}
int offset = code_offset();
__ adr(lr, pc());
__ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
__ end_a_stub();
return offset;
}
void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
_masm->code_section()->relocate(adr, relocInfo::poll_type);
int pc_offset = code_offset();
flush_debug_info(pc_offset);
info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
if (info->exception_handlers() != NULL) {
compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
}
}
void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
// Pop the stack before the safepoint code
__ remove_frame(initial_frame_size_in_bytes());
if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
__ reserved_stack_check();
}
code_stub->set_safepoint_offset(__ offset());
__ relocate(relocInfo::poll_return_type);
__ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
__ ret(lr);
}
int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
guarantee(info != NULL, "Shouldn't be NULL");
__ get_polling_page(rscratch1, relocInfo::poll_type);
add_debug_info_for_branch(info); // This isn't just debug info:
// it's the oop map
__ read_polling_page(rscratch1, relocInfo::poll_type);
return __ offset();
}
void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
if (from_reg == r31_sp)
from_reg = sp;
if (to_reg == r31_sp)
to_reg = sp;
__ mov(to_reg, from_reg);
}
void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
assert(src->is_constant(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
LIR_Const* c = src->as_constant_ptr();
switch (c->type()) {
case T_INT: {
assert(patch_code == lir_patch_none, "no patching handled here");
__ movw(dest->as_register(), c->as_jint());
break;
}
case T_ADDRESS: {
assert(patch_code == lir_patch_none, "no patching handled here");
__ mov(dest->as_register(), c->as_jint());
break;
}
case T_LONG: {
assert(patch_code == lir_patch_none, "no patching handled here");
__ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
break;
}
case T_OBJECT: {
if (patch_code == lir_patch_none) {
jobject2reg(c->as_jobject(), dest->as_register());
} else {
jobject2reg_with_patching(dest->as_register(), info);
}
break;
}
case T_METADATA: {
if (patch_code != lir_patch_none) {
klass2reg_with_patching(dest->as_register(), info);
} else {
__ mov_metadata(dest->as_register(), c->as_metadata());
}
break;
}
case T_FLOAT: {
if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
__ fmovs(dest->as_float_reg(), (c->as_jfloat()));
} else {
__ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
__ ldrs(dest->as_float_reg(), Address(rscratch1));
}
break;
}
case T_DOUBLE: {
if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
__ fmovd(dest->as_double_reg(), (c->as_jdouble()));
} else {
__ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
__ ldrd(dest->as_double_reg(), Address(rscratch1));
}
break;
}
default:
ShouldNotReachHere();
}
}
void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
LIR_Const* c = src->as_constant_ptr();
switch (c->type()) {
case T_OBJECT:
{
if (! c->as_jobject())
__ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
else {
const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
}
}
break;
case T_ADDRESS:
{
const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
}
case T_INT:
case T_FLOAT:
{
Register reg = zr;
if (c->as_jint_bits() == 0)
__ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
else {
__ movw(rscratch1, c->as_jint_bits());
__ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
}
}
break;
case T_LONG:
case T_DOUBLE:
{
Register reg = zr;
if (c->as_jlong_bits() == 0)
__ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
lo_word_offset_in_bytes));
else {
__ mov(rscratch1, (intptr_t)c->as_jlong_bits());
__ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
lo_word_offset_in_bytes));
}
}
break;
default:
ShouldNotReachHere();
}
}
void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
assert(src->is_constant(), "should not call otherwise");
LIR_Const* c = src->as_constant_ptr();
LIR_Address* to_addr = dest->as_address_ptr();
void (Assembler::* insn)(Register Rt, const Address &adr);
switch (type) {
case T_ADDRESS:
assert(c->as_jint() == 0, "should be");
insn = &Assembler::str;
break;
case T_LONG:
assert(c->as_jlong() == 0, "should be");
insn = &Assembler::str;
break;
case T_INT:
assert(c->as_jint() == 0, "should be");
insn = &Assembler::strw;
break;
case T_OBJECT:
case T_ARRAY:
assert(c->as_jobject() == 0, "should be");
if (UseCompressedOops && !wide) {
insn = &Assembler::strw;
} else {
insn = &Assembler::str;
}
break;
case T_CHAR:
case T_SHORT:
assert(c->as_jint() == 0, "should be");
insn = &Assembler::strh;
break;
case T_BOOLEAN:
case T_BYTE:
assert(c->as_jint() == 0, "should be");
insn = &Assembler::strb;
break;
default:
ShouldNotReachHere();
insn = &Assembler::str; // unreachable
}
if (info) add_debug_info_for_null_check_here(info);
(_masm->*insn)(zr, as_Address(to_addr, rscratch1));
}
void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
assert(src->is_register(), "should not call otherwise");
assert(dest->is_register(), "should not call otherwise");
// move between cpu-registers
if (dest->is_single_cpu()) {
if (src->type() == T_LONG) {
// Can do LONG -> OBJECT
move_regs(src->as_register_lo(), dest->as_register());
return;
}
assert(src->is_single_cpu(), "must match");
if (src->type() == T_OBJECT) {
__ verify_oop(src->as_register());
}
move_regs(src->as_register(), dest->as_register());
} else if (dest->is_double_cpu()) {
if (is_reference_type(src->type())) {
// Surprising to me but we can see move of a long to t_object
__ verify_oop(src->as_register());
move_regs(src->as_register(), dest->as_register_lo());
return;
}
assert(src->is_double_cpu(), "must match");
Register f_lo = src->as_register_lo();
Register f_hi = src->as_register_hi();
Register t_lo = dest->as_register_lo();
Register t_hi = dest->as_register_hi();
assert(f_hi == f_lo, "must be same");
assert(t_hi == t_lo, "must be same");
move_regs(f_lo, t_lo);
} else if (dest->is_single_fpu()) {
__ fmovs(dest->as_float_reg(), src->as_float_reg());
} else if (dest->is_double_fpu()) {
__ fmovd(dest->as_double_reg(), src->as_double_reg());
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
precond(src->is_register() && dest->is_stack());
uint const c_sz32 = sizeof(uint32_t);
uint const c_sz64 = sizeof(uint64_t);
if (src->is_single_cpu()) {
int index = dest->single_stack_ix();
if (is_reference_type(type)) {
__ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
__ verify_oop(src->as_register());
} else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
__ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
} else {
__ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
}
} else if (src->is_double_cpu()) {
int index = dest->double_stack_ix();
Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
__ str(src->as_register_lo(), dest_addr_LO);
} else if (src->is_single_fpu()) {
int index = dest->single_stack_ix();
__ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
} else if (src->is_double_fpu()) {
int index = dest->double_stack_ix();
__ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
LIR_Address* to_addr = dest->as_address_ptr();
PatchingStub* patch = NULL;
Register compressed_src = rscratch1;
if (patch_code != lir_patch_none) {
deoptimize_trap(info);
return;
}
if (is_reference_type(type)) {
__ verify_oop(src->as_register());
if (UseCompressedOops && !wide) {
__ encode_heap_oop(compressed_src, src->as_register());
} else {
compressed_src = src->as_register();
}
}
int null_check_here = code_offset();
switch (type) {
case T_FLOAT: {
__ strs(src->as_float_reg(), as_Address(to_addr));
break;
}
case T_DOUBLE: {
__ strd(src->as_double_reg(), as_Address(to_addr));
break;
}
case T_ARRAY: // fall through
case T_OBJECT: // fall through
if (UseCompressedOops && !wide) {
__ strw(compressed_src, as_Address(to_addr, rscratch2));
} else {
__ str(compressed_src, as_Address(to_addr));
}
break;
case T_METADATA:
// We get here to store a method pointer to the stack to pass to
// a dtrace runtime call. This can't work on 64 bit with
// compressed klass ptrs: T_METADATA can be a compressed klass
// ptr or a 64 bit method pointer.
ShouldNotReachHere();
__ str(src->as_register(), as_Address(to_addr));
break;
case T_ADDRESS:
__ str(src->as_register(), as_Address(to_addr));
break;
case T_INT:
__ strw(src->as_register(), as_Address(to_addr));
break;
case T_LONG: {
__ str(src->as_register_lo(), as_Address_lo(to_addr));
break;
}
case T_BYTE: // fall through
case T_BOOLEAN: {
__ strb(src->as_register(), as_Address(to_addr));
break;
}
case T_CHAR: // fall through
case T_SHORT:
__ strh(src->as_register(), as_Address(to_addr));
break;
default:
ShouldNotReachHere();
}
if (info != NULL) {
add_debug_info_for_null_check(null_check_here, info);
}
}
void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
precond(src->is_stack() && dest->is_register());
uint const c_sz32 = sizeof(uint32_t);
uint const c_sz64 = sizeof(uint64_t);
if (dest->is_single_cpu()) {
int index = src->single_stack_ix();
if (is_reference_type(type)) {
__ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
__ verify_oop(dest->as_register());
} else if (type == T_METADATA || type == T_ADDRESS) {
__ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
} else {
__ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
}
} else if (dest->is_double_cpu()) {
int index = src->double_stack_ix();
Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
__ ldr(dest->as_register_lo(), src_addr_LO);
} else if (dest->is_single_fpu()) {
int index = src->single_stack_ix();
__ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
} else if (dest->is_double_fpu()) {
int index = src->double_stack_ix();
__ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
} else {
ShouldNotReachHere();
}
}
void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
address target = NULL;
relocInfo::relocType reloc_type = relocInfo::none;
switch (patching_id(info)) {
case PatchingStub::access_field_id:
target = Runtime1::entry_for(Runtime1::access_field_patching_id);
reloc_type = relocInfo::section_word_type;
break;
case PatchingStub::load_klass_id:
target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
reloc_type = relocInfo::metadata_type;
break;
case PatchingStub::load_mirror_id:
target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
reloc_type = relocInfo::oop_type;
break;
case PatchingStub::load_appendix_id:
target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
reloc_type = relocInfo::oop_type;
break;
default: ShouldNotReachHere();
}
__ far_call(RuntimeAddress(target));
add_call_info_here(info);
}
void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
LIR_Opr temp;
if (type == T_LONG || type == T_DOUBLE)
temp = FrameMap::rscratch1_long_opr;
else
temp = FrameMap::rscratch1_opr;
stack2reg(src, temp, src->type());
reg2stack(temp, dest, dest->type(), false);
}
void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
LIR_Address* addr = src->as_address_ptr();
LIR_Address* from_addr = src->as_address_ptr();
if (addr->base()->type() == T_OBJECT) {
__ verify_oop(addr->base()->as_pointer_register());
}
if (patch_code != lir_patch_none) {
deoptimize_trap(info);
return;
}
if (info != NULL) {
add_debug_info_for_null_check_here(info);
}
int null_check_here = code_offset();
switch (type) {
case T_FLOAT: {
__ ldrs(dest->as_float_reg(), as_Address(from_addr));
break;
}
case T_DOUBLE: {
__ ldrd(dest->as_double_reg(), as_Address(from_addr));
break;
}
case T_ARRAY: // fall through
case T_OBJECT: // fall through
if (UseCompressedOops && !wide) {
__ ldrw(dest->as_register(), as_Address(from_addr));
} else {
__ ldr(dest->as_register(), as_Address(from_addr));
}
break;
case T_METADATA:
// We get here to store a method pointer to the stack to pass to
// a dtrace runtime call. This can't work on 64 bit with
// compressed klass ptrs: T_METADATA can be a compressed klass
// ptr or a 64 bit method pointer.
ShouldNotReachHere();
__ ldr(dest->as_register(), as_Address(from_addr));
break;
case T_ADDRESS:
__ ldr(dest->as_register(), as_Address(from_addr));
break;
case T_INT:
__ ldrw(dest->as_register(), as_Address(from_addr));
break;
case T_LONG: {
__ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
break;
}
case T_BYTE:
__ ldrsb(dest->as_register(), as_Address(from_addr));
break;
case T_BOOLEAN: {
__ ldrb(dest->as_register(), as_Address(from_addr));
break;
}
case T_CHAR:
__ ldrh(dest->as_register(), as_Address(from_addr));
break;
case T_SHORT: