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aarch64_sve.ad
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aarch64_sve.ad
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//
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
//
// This file is automatically generated by running "m4 aarch64_sve_ad.m4". Do not edit ----
// AArch64 SVE Architecture Description File
// 4 bit signed offset -- for predicated load/store
operand vmemA_immIOffset4()
%{
predicate(Address::offset_ok_for_sve_immed(n->get_int(), 4,
Matcher::scalable_vector_reg_size(T_BYTE)));
match(ConI);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
operand vmemA_immLOffset4()
%{
predicate(Address::offset_ok_for_sve_immed(n->get_long(), 4,
Matcher::scalable_vector_reg_size(T_BYTE)));
match(ConL);
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}
operand vmemA_indOffI4(iRegP reg, vmemA_immIOffset4 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP reg off);
op_cost(0);
format %{ "[$reg, $off, MUL VL]" %}
interface(MEMORY_INTER) %{
base($reg);
index(0xffffffff);
scale(0x0);
disp($off);
%}
%}
operand vmemA_indOffL4(iRegP reg, vmemA_immLOffset4 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
match(AddP reg off);
op_cost(0);
format %{ "[$reg, $off, MUL VL]" %}
interface(MEMORY_INTER) %{
base($reg);
index(0xffffffff);
scale(0x0);
disp($off);
%}
%}
opclass vmemA(indirect, vmemA_indOffI4, vmemA_indOffL4);
source_hpp %{
bool op_sve_supported(int opcode);
%}
source %{
static inline BasicType vector_element_basic_type(const MachNode* n) {
const TypeVect* vt = n->bottom_type()->is_vect();
return vt->element_basic_type();
}
static inline BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
int def_idx = use->operand_index(opnd);
Node* def = use->in(def_idx);
const TypeVect* vt = def->bottom_type()->is_vect();
return vt->element_basic_type();
}
static inline uint vector_length(const MachNode* n) {
const TypeVect* vt = n->bottom_type()->is_vect();
return vt->length();
}
static inline uint vector_length(const MachNode* use, const MachOper* opnd) {
int def_idx = use->operand_index(opnd);
Node* def = use->in(def_idx);
const TypeVect* vt = def->bottom_type()->is_vect();
return vt->length();
}
static inline uint vector_length_in_bytes(const MachNode* n) {
const TypeVect* vt = n->bottom_type()->is_vect();
return vt->length_in_bytes();
}
static inline uint vector_length_in_bytes(const MachNode* use, MachOper* opnd) {
uint def_idx = use->operand_index(opnd);
Node* def = use->in(def_idx);
const TypeVect* vt = def->bottom_type()->is_vect();
return vt->length_in_bytes();
}
static Assembler::SIMD_RegVariant elemBytes_to_regVariant(int esize) {
switch(esize) {
case 1:
return Assembler::B;
case 2:
return Assembler::H;
case 4:
return Assembler::S;
case 8:
return Assembler::D;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
return Assembler::INVALID;
}
static Assembler::SIMD_RegVariant elemType_to_regVariant(BasicType bt) {
return elemBytes_to_regVariant(type2aelembytes(bt));
}
typedef void (C2_MacroAssembler::* sve_mem_insn_predicate)(FloatRegister Rt, Assembler::SIMD_RegVariant T,
PRegister Pg, const Address &adr);
// Predicated load/store, with optional ptrue to all elements of given predicate register.
static void loadStoreA_predicate(C2_MacroAssembler masm, bool is_store, FloatRegister reg,
PRegister pg, BasicType mem_elem_bt,
Assembler::SIMD_RegVariant vector_elem_size,
int opcode, Register base, int index, int size, int disp) {
sve_mem_insn_predicate insn;
int esize = type2aelembytes(mem_elem_bt);
if (index == -1) {
assert(size == 0, "unsupported address mode: scale size = %d", size);
switch(esize) {
case 1:
insn = is_store ? &C2_MacroAssembler::sve_st1b : &C2_MacroAssembler::sve_ld1b;
break;
case 2:
insn = is_store ? &C2_MacroAssembler::sve_st1h : &C2_MacroAssembler::sve_ld1h;
break;
case 4:
insn = is_store ? &C2_MacroAssembler::sve_st1w : &C2_MacroAssembler::sve_ld1w;
break;
case 8:
insn = is_store ? &C2_MacroAssembler::sve_st1d : &C2_MacroAssembler::sve_ld1d;
break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
(masm.*insn)(reg, vector_elem_size, pg, Address(base, disp / Matcher::scalable_vector_reg_size(T_BYTE)));
} else {
assert(false, "unimplemented");
ShouldNotReachHere();
}
}
static void sve_compare(C2_MacroAssembler masm, PRegister pd, BasicType bt,
PRegister pg, FloatRegister zn, FloatRegister zm, int cond) {
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
if (bt == T_FLOAT || bt == T_DOUBLE) {
switch (cond) {
case BoolTest::eq: masm.sve_fcmeq(pd, size, pg, zn, zm); break;
case BoolTest::ne: masm.sve_fcmne(pd, size, pg, zn, zm); break;
case BoolTest::ge: masm.sve_fcmge(pd, size, pg, zn, zm); break;
case BoolTest::gt: masm.sve_fcmgt(pd, size, pg, zn, zm); break;
case BoolTest::le: masm.sve_fcmge(pd, size, pg, zm, zn); break;
case BoolTest::lt: masm.sve_fcmgt(pd, size, pg, zm, zn); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
} else {
switch (cond) {
case BoolTest::eq: masm.sve_cmpeq(pd, size, pg, zn, zm); break;
case BoolTest::ne: masm.sve_cmpne(pd, size, pg, zn, zm); break;
case BoolTest::ge: masm.sve_cmpge(pd, size, pg, zn, zm); break;
case BoolTest::gt: masm.sve_cmpgt(pd, size, pg, zn, zm); break;
case BoolTest::le: masm.sve_cmpge(pd, size, pg, zm, zn); break;
case BoolTest::lt: masm.sve_cmpgt(pd, size, pg, zm, zn); break;
default:
assert(false, "unsupported");
ShouldNotReachHere();
}
}
}
bool op_sve_supported(int opcode) {
switch (opcode) {
case Op_MulAddVS2VI:
// No multiply reduction instructions
case Op_MulReductionVD:
case Op_MulReductionVF:
case Op_MulReductionVI:
case Op_MulReductionVL:
// Others
case Op_Extract:
case Op_ExtractB:
case Op_ExtractC:
case Op_ExtractD:
case Op_ExtractF:
case Op_ExtractI:
case Op_ExtractL:
case Op_ExtractS:
case Op_ExtractUB:
// Vector API specific
case Op_LoadVectorGather:
case Op_StoreVectorScatter:
case Op_VectorCastD2X:
case Op_VectorCastF2X:
case Op_VectorInsert:
case Op_VectorLoadConst:
case Op_VectorLoadShuffle:
case Op_VectorRearrange:
case Op_VectorTest:
return false;
default:
return true;
}
}
%}
definitions %{
int_def SVE_COST (200, 200);
%}
// All SVE instructions
// vector load/store
// Unpredicated vector load/store
instruct loadV(vReg dst, vmemA mem) %{
predicate(UseSVE > 0 && n->as_LoadVector()->memory_size() >= 16 &&
n->as_LoadVector()->memory_size() == MaxVectorSize);
match(Set dst (LoadVector mem));
ins_cost(SVE_COST);
format %{ "sve_ldr $dst, $mem\t # vector (sve)" %}
ins_encode %{
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
BasicType bt = vector_element_basic_type(this);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), false, dst_reg, ptrue,
bt, elemType_to_regVariant(bt), $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
%}
instruct storeV(vReg src, vmemA mem) %{
predicate(UseSVE > 0 && n->as_StoreVector()->memory_size() >= 16 &&
n->as_StoreVector()->memory_size() == MaxVectorSize);
match(Set mem (StoreVector mem src));
ins_cost(SVE_COST);
format %{ "sve_str $mem, $src\t # vector (sve)" %}
ins_encode %{
FloatRegister src_reg = as_FloatRegister($src$$reg);
BasicType bt = vector_element_basic_type(this, $src);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), true, src_reg, ptrue,
bt, elemType_to_regVariant(bt), $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
%}
// Predicated vector load/store, based on the vector length of the node.
// Only load/store values in the range of the memory_size. This is needed
// when the memory_size is lower than the hardware supported max vector size.
// And this might happen for Vector API mask vector load/store.
instruct loadV_partial(vReg dst, vmemA mem, pRegGov pTmp, iRegINoSp tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->as_LoadVector()->length() >= MaxVectorSize / 8 &&
n->as_LoadVector()->memory_size() != MaxVectorSize);
match(Set dst (LoadVector mem));
effect(TEMP pTmp, TEMP tmp, KILL cr);
ins_cost(2 * SVE_COST);
format %{ "mov $tmp, vector_length\n\t"
"sve_whilelo $pTmp, zr, $tmp\n\t"
"sve_ldr $dst, $pTmp, $mem\t # load vector mask" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
__ mov(as_Register($tmp$$reg), vector_length(this));
__ sve_whilelo(as_PRegister($pTmp$$reg), size,
zr, as_Register($tmp$$reg));
FloatRegister dst_reg = as_FloatRegister($dst$$reg);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), false, dst_reg,
as_PRegister($pTmp$$reg), bt, size, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
%}
instruct storeV_partial(vReg src, vmemA mem, pRegGov pTmp, iRegINoSp tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->as_StoreVector()->length() >= MaxVectorSize / 8 &&
n->as_StoreVector()->memory_size() != MaxVectorSize);
match(Set mem (StoreVector mem src));
effect(TEMP pTmp, TEMP tmp, KILL cr);
ins_cost(2 * SVE_COST);
format %{ "mov $tmp, vector_length\n\t"
"sve_whilelo $pTmp, zr, $tmp\n\t"
"sve_str $src, $pTmp, $mem\t # store vector mask" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this, $src);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
__ mov(as_Register($tmp$$reg), vector_length(this, $src));
__ sve_whilelo(as_PRegister($pTmp$$reg), size,
zr, as_Register($tmp$$reg));
FloatRegister src_reg = as_FloatRegister($src$$reg);
loadStoreA_predicate(C2_MacroAssembler(&cbuf), true, src_reg,
as_PRegister($pTmp$$reg), bt, size, $mem->opcode(),
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
%}
ins_pipe(pipe_slow);
%}
// vector reinterpret
instruct reinterpret(vReg dst) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16 &&
n->as_Vector()->length_in_bytes() ==
n->in(1)->bottom_type()->is_vect()->length_in_bytes()); // src == dst
match(Set dst (VectorReinterpret dst));
ins_cost(0);
format %{ " # reinterpret $dst" %}
ins_encode %{
// empty
%}
ins_pipe(pipe_class_empty);
%}
instruct reinterpretResize(vReg dst, vReg src, iRegINoSp tmp, pRegGov pTmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && n->in(1)->bottom_type()->is_vect()->length_in_bytes() >= 16 &&
n->as_Vector()->length_in_bytes() >= 16 &&
n->as_Vector()->length_in_bytes() !=
n->in(1)->bottom_type()->is_vect()->length_in_bytes()); // src != dst
match(Set dst (VectorReinterpret src));
effect(TEMP_DEF dst, TEMP pTmp, TEMP tmp, KILL cr);
ins_cost(3 * SVE_COST);
format %{ " # reinterpretResize $dst,$src\t" %}
ins_encode %{
uint length_in_bytes_src = vector_length_in_bytes(this, $src);
uint length_in_bytes_dst = vector_length_in_bytes(this);
uint length_in_bytes_resize = length_in_bytes_src < length_in_bytes_dst ?
length_in_bytes_src : length_in_bytes_dst;
__ mov(as_Register($tmp$$reg), length_in_bytes_resize);
__ sve_whilelo(as_PRegister($pTmp$$reg), __ B,
zr, as_Register($tmp$$reg));
__ sve_dup(as_FloatRegister($dst$$reg), __ B, 0);
__ sve_sel(as_FloatRegister($dst$$reg), __ B, as_PRegister($pTmp$$reg),
as_FloatRegister($src$$reg), as_FloatRegister($dst$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector abs
instruct vabsB(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16 &&
n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
match(Set dst (AbsVB src));
ins_cost(SVE_COST);
format %{ "sve_abs $dst, $src\t# vector (sve) (B)" %}
ins_encode %{
__ sve_abs(as_FloatRegister($dst$$reg), __ B,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vabsS(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8 &&
n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
match(Set dst (AbsVS src));
ins_cost(SVE_COST);
format %{ "sve_abs $dst, $src\t# vector (sve) (H)" %}
ins_encode %{
__ sve_abs(as_FloatRegister($dst$$reg), __ H,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vabsI(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4 &&
n->bottom_type()->is_vect()->element_basic_type() == T_INT);
match(Set dst (AbsVI src));
ins_cost(SVE_COST);
format %{ "sve_abs $dst, $src\t# vector (sve) (S)" %}
ins_encode %{
__ sve_abs(as_FloatRegister($dst$$reg), __ S,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vabsL(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2 &&
n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
match(Set dst (AbsVL src));
ins_cost(SVE_COST);
format %{ "sve_abs $dst, $src\t# vector (sve) (D)" %}
ins_encode %{
__ sve_abs(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vabsF(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4 &&
n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
match(Set dst (AbsVF src));
ins_cost(SVE_COST);
format %{ "sve_fabs $dst, $src\t# vector (sve) (S)" %}
ins_encode %{
__ sve_fabs(as_FloatRegister($dst$$reg), __ S,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vabsD(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2 &&
n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
match(Set dst (AbsVD src));
ins_cost(SVE_COST);
format %{ "sve_fabs $dst, $src\t# vector (sve) (D)" %}
ins_encode %{
__ sve_fabs(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector add
instruct vaddB(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
match(Set dst (AddVB src1 src2));
ins_cost(SVE_COST);
format %{ "sve_add $dst, $src1, $src2\t # vector (sve) (B)" %}
ins_encode %{
__ sve_add(as_FloatRegister($dst$$reg), __ B,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vaddS(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
match(Set dst (AddVS src1 src2));
ins_cost(SVE_COST);
format %{ "sve_add $dst, $src1, $src2\t # vector (sve) (H)" %}
ins_encode %{
__ sve_add(as_FloatRegister($dst$$reg), __ H,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vaddI(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst (AddVI src1 src2));
ins_cost(SVE_COST);
format %{ "sve_add $dst, $src1, $src2\t # vector (sve) (S)" %}
ins_encode %{
__ sve_add(as_FloatRegister($dst$$reg), __ S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vaddL(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst (AddVL src1 src2));
ins_cost(SVE_COST);
format %{ "sve_add $dst, $src1, $src2\t # vector (sve) (D)" %}
ins_encode %{
__ sve_add(as_FloatRegister($dst$$reg), __ D,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vaddF(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst (AddVF src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fadd $dst, $src1, $src2\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fadd(as_FloatRegister($dst$$reg), __ S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vaddD(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst (AddVD src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fadd $dst, $src1, $src2\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fadd(as_FloatRegister($dst$$reg), __ D,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector and
instruct vand(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (AndV src1 src2));
ins_cost(SVE_COST);
format %{ "sve_and $dst, $src1, $src2\t# vector (sve)" %}
ins_encode %{
__ sve_and(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector or
instruct vor(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (OrV src1 src2));
ins_cost(SVE_COST);
format %{ "sve_orr $dst, $src1, $src2\t# vector (sve)" %}
ins_encode %{
__ sve_orr(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector xor
instruct vxor(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (XorV src1 src2));
ins_cost(SVE_COST);
format %{ "sve_eor $dst, $src1, $src2\t# vector (sve)" %}
ins_encode %{
__ sve_eor(as_FloatRegister($dst$$reg),
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector float div
instruct vdivF(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (DivVF dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fdiv $dst_src1, $dst_src1, $src2\t# vector (sve) (S)" %}
ins_encode %{
__ sve_fdiv(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vdivD(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (DivVD dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fdiv $dst_src1, $dst_src1, $src2\t# vector (sve) (D)" %}
ins_encode %{
__ sve_fdiv(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector min/max
instruct vmin(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst_src1 (MinV dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_min $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
if (is_floating_point_type(bt)) {
__ sve_fmin(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
} else {
assert(is_integral_type(bt), "Unsupported type");
__ sve_smin(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
}
%}
ins_pipe(pipe_slow);
%}
instruct vmax(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst_src1 (MaxV dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_max $dst_src1, $dst_src1, $src2\t # vector (sve)" %}
ins_encode %{
BasicType bt = vector_element_basic_type(this);
Assembler::SIMD_RegVariant size = elemType_to_regVariant(bt);
if (is_floating_point_type(bt)) {
__ sve_fmax(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
} else {
assert(is_integral_type(bt), "Unsupported type");
__ sve_smax(as_FloatRegister($dst_src1$$reg), size,
ptrue, as_FloatRegister($src2$$reg));
}
%}
ins_pipe(pipe_slow);
%}
// vector fmla
// dst_src1 = dst_src1 + src2 * src3
instruct vfmlaF(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (FmaVF dst_src1 (Binary src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_fmla $dst_src1, $src2, $src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fmla(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 + src2 * src3
instruct vfmlaD(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (FmaVD dst_src1 (Binary src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_fmla $dst_src1, $src2, $src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fmla(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector fmls
// dst_src1 = dst_src1 + -src2 * src3
// dst_src1 = dst_src1 + src2 * -src3
instruct vfmlsF(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (FmaVF dst_src1 (Binary (NegVF src2) src3)));
match(Set dst_src1 (FmaVF dst_src1 (Binary src2 (NegVF src3))));
ins_cost(SVE_COST);
format %{ "sve_fmls $dst_src1, $src2, $src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fmls(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 + -src2 * src3
// dst_src1 = dst_src1 + src2 * -src3
instruct vfmlsD(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (FmaVD dst_src1 (Binary (NegVD src2) src3)));
match(Set dst_src1 (FmaVD dst_src1 (Binary src2 (NegVD src3))));
ins_cost(SVE_COST);
format %{ "sve_fmls $dst_src1, $src2, $src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fmls(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector fnmla
// dst_src1 = -dst_src1 + -src2 * src3
// dst_src1 = -dst_src1 + src2 * -src3
instruct vfnmlaF(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary (NegVF src2) src3)));
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 (NegVF src3))));
ins_cost(SVE_COST);
format %{ "sve_fnmla $dst_src1, $src2, $src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fnmla(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = -dst_src1 + -src2 * src3
// dst_src1 = -dst_src1 + src2 * -src3
instruct vfnmlaD(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary (NegVD src2) src3)));
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 (NegVD src3))));
ins_cost(SVE_COST);
format %{ "sve_fnmla $dst_src1, $src2, $src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fnmla(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector fnmls
// dst_src1 = -dst_src1 + src2 * src3
instruct vfnmlsF(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (FmaVF (NegVF dst_src1) (Binary src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_fnmls $dst_src1, $src2, $src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fnmls(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = -dst_src1 + src2 * src3
instruct vfnmlsD(vReg dst_src1, vReg src2, vReg src3) %{
predicate(UseFMA && UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (FmaVD (NegVD dst_src1) (Binary src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_fnmls $dst_src1, $src2, $src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fnmls(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector mla
// dst_src1 = dst_src1 + src2 * src3
instruct vmlaB(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
match(Set dst_src1 (AddVB dst_src1 (MulVB src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mla $dst_src1, src2, src3\t # vector (sve) (B)" %}
ins_encode %{
__ sve_mla(as_FloatRegister($dst_src1$$reg), __ B,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 + src2 * src3
instruct vmlaS(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
match(Set dst_src1 (AddVS dst_src1 (MulVS src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mla $dst_src1, src2, src3\t # vector (sve) (H)" %}
ins_encode %{
__ sve_mla(as_FloatRegister($dst_src1$$reg), __ H,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 + src2 * src3
instruct vmlaI(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (AddVI dst_src1 (MulVI src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mla $dst_src1, src2, src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_mla(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 + src2 * src3
instruct vmlaL(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (AddVL dst_src1 (MulVL src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mla $dst_src1, src2, src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_mla(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector mls
// dst_src1 = dst_src1 - src2 * src3
instruct vmlsB(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
match(Set dst_src1 (SubVB dst_src1 (MulVB src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mls $dst_src1, src2, src3\t # vector (sve) (B)" %}
ins_encode %{
__ sve_mls(as_FloatRegister($dst_src1$$reg), __ B,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 - src2 * src3
instruct vmlsS(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
match(Set dst_src1 (SubVS dst_src1 (MulVS src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mls $dst_src1, src2, src3\t # vector (sve) (H)" %}
ins_encode %{
__ sve_mls(as_FloatRegister($dst_src1$$reg), __ H,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 - src2 * src3
instruct vmlsI(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (SubVI dst_src1 (MulVI src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mls $dst_src1, src2, src3\t # vector (sve) (S)" %}
ins_encode %{
__ sve_mls(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// dst_src1 = dst_src1 - src2 * src3
instruct vmlsL(vReg dst_src1, vReg src2, vReg src3)
%{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (SubVL dst_src1 (MulVL src2 src3)));
ins_cost(SVE_COST);
format %{ "sve_mls $dst_src1, src2, src3\t # vector (sve) (D)" %}
ins_encode %{
__ sve_mls(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg), as_FloatRegister($src3$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector mul
instruct vmulB(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
match(Set dst_src1 (MulVB dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_mul $dst_src1, $dst_src1, $src2\t # vector (sve) (B)" %}
ins_encode %{
__ sve_mul(as_FloatRegister($dst_src1$$reg), __ B,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vmulS(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 8);
match(Set dst_src1 (MulVS dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_mul $dst_src1, $dst_src1, $src2\t # vector (sve) (H)" %}
ins_encode %{
__ sve_mul(as_FloatRegister($dst_src1$$reg), __ H,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vmulI(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst_src1 (MulVI dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_mul $dst_src1, $dst_src1, $src2\t # vector (sve) (S)" %}
ins_encode %{
__ sve_mul(as_FloatRegister($dst_src1$$reg), __ S,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vmulL(vReg dst_src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst_src1 (MulVL dst_src1 src2));
ins_cost(SVE_COST);
format %{ "sve_mul $dst_src1, $dst_src1, $src2\t # vector (sve) (D)" %}
ins_encode %{
__ sve_mul(as_FloatRegister($dst_src1$$reg), __ D,
ptrue, as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vmulF(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst (MulVF src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fmul $dst, $src1, $src2\t # vector (sve) (S)" %}
ins_encode %{
__ sve_fmul(as_FloatRegister($dst$$reg), __ S,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vmulD(vReg dst, vReg src1, vReg src2) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 2);
match(Set dst (MulVD src1 src2));
ins_cost(SVE_COST);
format %{ "sve_fmul $dst, $src1, $src2\t # vector (sve) (D)" %}
ins_encode %{
__ sve_fmul(as_FloatRegister($dst$$reg), __ D,
as_FloatRegister($src1$$reg),
as_FloatRegister($src2$$reg));
%}
ins_pipe(pipe_slow);
%}
// vector fneg
instruct vnegF(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (NegVF src));
ins_cost(SVE_COST);
format %{ "sve_fneg $dst, $src\t# vector (sve) (S)" %}
ins_encode %{
__ sve_fneg(as_FloatRegister($dst$$reg), __ S,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
instruct vnegD(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length_in_bytes() >= 16);
match(Set dst (NegVD src));
ins_cost(SVE_COST);
format %{ "sve_fneg $dst, $src\t# vector (sve) (D)" %}
ins_encode %{
__ sve_fneg(as_FloatRegister($dst$$reg), __ D,
ptrue, as_FloatRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}
// popcount vector
instruct vpopcountI(vReg dst, vReg src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst (PopCountVI src));
format %{ "sve_cnt $dst, $src\t# vector (sve) (S)\n\t" %}