Skip to content
Permalink
Browse files

or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>
  • Loading branch information...
stekern
stekern committed Oct 25, 2012
1 parent 385ffbf commit bd5b48dc114fc7e4362a68fcb6c574c22fc6d7ad
Showing with 15 additions and 7 deletions.
  1. +2 −1 rtl/verilog/or1200_dc_fsm.v
  2. +13 −6 rtl/verilog/or1200_ic_fsm.v
@@ -312,7 +312,8 @@ module or1200_dc_fsm
// LSU straight off external data bus. In
// this was is also used for cache inhibit
// loads.
assign first_miss_ack = load_miss_ack | load_inhibit_ack;
// first_hit_ack takes precedence over first_miss_ack
assign first_miss_ack = ~first_hit_ack & (load_miss_ack | load_inhibit_ack);

// ACK cache hit on load
assign load_hit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
@@ -122,14 +122,18 @@ reg last_eval_miss; // JPB
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;

//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
// Asserted when a cache hit occurs and the first word is ready/valid
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval &
!tagcomp_miss & !cache_inhibit;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;

// Asserted when a cache miss occurs, but the first word of the new
// cache line is ready (on the bus)
// Cache hits overpower bus data
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid &
~first_hit_ack;

// Asserted when a cache occurs, but there was a bus error with handling
// the old line or fetching the new line
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;

//
@@ -175,6 +179,9 @@ reg last_eval_miss; // JPB

if (hitmiss_eval)
saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];

// Check for stopped cache loads
// instruction cache turned-off
if ((!ic_en) ||
// fetch aborted (usually caused by IMMU)
(hitmiss_eval & !icqmem_cycstb_i) ||

0 comments on commit bd5b48d

Please sign in to comment.
You can’t perform that action at this time.