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ChangeLog
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ChangeLog
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2014-05-04 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* cpu/common/abstract.c:
(set_mem32) Clear atomic reserve on write to atomic address.
(set_mem16) Likewise.
(set_mem8) Likewise.
* cpu/common/execute.h <cpu_state>: Add loadlock_active and
loadlock_address members.
* cpu/or1k/except.c (except_handle): Clear atomic reserve on
exceptions.
* cpu/or32/insnset.c:
(l_swa): New function.
(l_lwa): Likewise.
* cpu/or32/or32.c <or1ksim_or32_opcodes>: Add l.lwa and l.swa
instructions.
* cpu/or32/simpl32-defs.h: Add l_swa and l_lwa declarations.
* cuc/load.c <conv>: Add l.lwa and l.swa instructions.
2013-04-22 Peter Gavin <pgavin@gmail.com>
* cpu/or32/insnset.c: (l_div) check for 0x80000000 / 0xffffffff,
and treat it like division by zero (set OV flag, do not write to
destination register). The C standard specifies that this
operation is undefined, and will typically raise an exception,
aborting the simulator, just like divide by zero. So this change
not only changes the ISA, but fixes a bug in the simulator.
2013-04-10 Peter Gavin <pgavin@gmail.com>
* cpu/or32/or32.c: (insn_extract) make sure the new extracted bit
is unsigned, otherwise the result may become negative and will be
sign-extended when cast to a 64-bit integer. This fixes the bug
on 64-bit systems where "<invalid>" would be printed in traces for
valid instructions
2013-04-04 Peter Gavin <pgavin@gmail.com>
* cpu/or32/insnset.c: change implementations of l_add, l_addc,
l_sub, l_mul, l_mulu, l_div, and l_divu to match current
architecture manual revision (1.0-rev0):
- add AECR/AESR support. Only used when AECSRP bit in CPUCFGR is
set, otherwise exception is raised when OVE and OV are both set
- l_mac and l_msb use full 32x32-bit to 64-bit multiply
- l_mac and l_msb set OV bit if add stage overflows, which may
cause exception
- l_mul does not touch CY flag
- l_div, l_divu now set OV bit for DBZ
2013-04-03 Peter Gavin <pgavin@gmail.com>
* cpu-config.c: (cpu_cfgr) improve checks on configuration, ensure
that OB32S is always set, and that unsupported features are
unset. Print a warning whenever configuration is changed from
whatever was specified in the file
2013-04-03 Peter Gavin <pgavin@gmail.com>
* cpu/or1k/spr-defs.h, cpu/or1k/spr-dump.c: add some new SPRs from
newest version of architecture manual (v1.0-rev0)
2013-07-28 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* tick/tick.c (spr_write_ttmr): Do not disable counter when in
continous mode and timer value mathes the timer period.
2013-01-30 Jeremy Bennett <jeremy.bennett@embecosm.com>
* README.md: Updated to explain about the or1k variant.
2012-11-08 Peter Gavin <pgavin@gmail.com>
* config.h.in: regenerated
* configure: ditto
* doc/or1ksim.info: ditto
* doc/version.texi: ditto
2012-11-08 Peter Gavin <pgavin@gmail.com>
* doc/or1ksim.info: add docs for or1knd (no delay slot mode)
2012-11-08 Peter Gavin <pgavin@gmail.com>
* doc/or1ksim.texi: s/or32/or1k/
2012-11-08 Peter Gavin <pgavin@gmail.com>
* configure.ac: check for target=or1knd-* and define OR32_NODELAY
* sim-config.c:
(init_defconfig) if OR32_NODELAY is defined, use 0x420 as default
CPUCFGR value
2012-10-28 Peter Gavin <pgavin@gmail.com>
autoreconf, update docs
* */Makefile.in: regenerated
* aclocal.m4: ditto
* configure: ditto
* doc/or1ksim.info: ditto
* doc/version.m4: ditto
2012-10-28 Peter Gavin <pgavin@gmail.com>
add or1knd (no-delay slot) target
* sim-nd.cfg: new file: configuration for no-delay target.
essentially a copy of sim.cfg.
* Makefile.am:
(DISTCHECK_CONFIGURE_FLAGS) use $(target_alias) instead of or1k-elf
(EXTRA_DIST) add sim-nd.cfg
* config.sub: add or1knd target
* config.guess: ditto
* configure.ac: ditto
* cpu/or1k/spr-defs.h:
(SPR_CPUCFGR_ND) no-delay slot flag
* cpu-config.c:
(cpu_cfgr) allow SPR_CPUCFGR_ND bit to be set in the argument
* cpu/or32/insnset.c:
(l_j) check if ND bit is set; if so, don't use delay slot. this is
done by setting pcnext directly, and *not* setting next_delay_insn
or cpu_state.pc_delay, which are ignored altogether in nodelay mode.
(l_jal) ditto
(l_jr) ditto
(l_jalr) ditto
(l_bf) ditto
(l_bnf) ditto
2012-04-27 Peter Gavin <pgavin@gmail.com>
* Makefile.am: s,or32,or1k,
* config.guess: ditto
* config.sub: ditto
* configure.ac: ditto
2012-04-27 Peter Gavin <pgavin@gmail.com>
* configure: Regenerated.
* configure.ac: Updated version.
2012-04-07 Jeremy Bennett <jeremy.bennett@embecosm.com>
* MAINTAINERS: Added.
* configure: Regenerated.
* configure.ac: Updated version.
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
2011-08-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
2011-08-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version. Turned off -Werror (workaround
for Bug 64). Fixed custom tests for strndup, strcasecmp and
isblank (Bug 65).
2001-07-08 Olof Kindren <olof@opencores.org>
* configure.ac: Added AM_SILENT_RULES for nicer builds
* configure: Regenerated.
2011-06-12 Julius Baxter <julius@opencores.org>
* cpu/or1k/spr-defs.h: <SPR_TTCR_CNT>: Change back to 0xffffffff
* tick/tick.c: <cycles_start>: renamed cycle_count_at_tick_start.
<tick_count>: Renamed tick_counting.
(sched_timer_job): Various comments to detail what is going on.
<match_time>: Renamed match_ttmr.
<ttcr_period>: Renamed match_ttcr.
<match_ttcr>: Is now TTCR value masked with TTMR_TP.
<cycles_until_except>: Added, being used to calculate cycles until next
exception instead of match_time.
2011-06-10 Julius Baxter <julius@opencores.org>
* cpu/or1k/spr-defs.h: <SPR_TTCR_CNT>: Change to 0x0fffffff
2011-06-06 Julius Baxter <julius@opencores.org>
* Makefile.in: Regenerated.
* cpu/or32/insnset.c: (mfspr): Made move-from-SPR in user mode work when
SR[SUMRA] bit set.
* cpu/common/abstract.c: Added PCU header to includes.
(eval_mem32): Added call to PCU event count function.
Moved debug breakpoint check to after exception triggers.
(eval_mem16): Ditto.
(eval_mem8): Ditto.
(set_mem32): Ditto.
(set_mem16): Ditto.
(set_mem8): Ditto.
(eval_insn): Added call to PCU event count function.
* configure.ac: Added newly added pcu/ path to appropriate places.
* cache/dcache-model.c: Added PCU header to includes.
(dc_simulate_read): Added call to PCU event count function.
* cache/icache-model.c: Added PCU header to includes.
(ic_simulate_read): Added call to PCU event count function.
* pcu/Makefile.in: Generated and added.
* pcu/pcu.c: Added.
* pcu/Makefile.am: Added.
* pcu/pcu.h: Added.
* mmu/dmmu.c: Added PCU header to includes.
(dmmu_translate): Added call to PCU event count function on miss.
Cleared away unused code surrounded by "#if 0".
* mmu/immu.c: Added PCU header to includes.
(immu_translate): Added call to PCU event count function on miss.
Cleared away unused code surrounded by "#if 0".
* configure: Regenerated.
* Makefile.am: <SUBDIRS>: Added pcu.
<libor1ksys_la_LIBADD>: Added pcu/libpcu.la.
* sim-config.c: Added PCU header to includes.
(init_defconfig): Initialise pcu config struct.
(reg_config_secs): Add call to pcu section setup function.
* sim-config.h: <struct config>: Added pcu config struct.
* doc/or1ksim.texi: Added information on pcu configuration.
2011-06-04 Julius Baxter <julius@opencores.org>
* cpu/or32/rec-i386.h: Removed.
* cpu/or32/op-2t.h: Removed.
* cpu/or32/rec-i386.h: Removed.
* cpu/or32/op-2t.h: Removed.
* cpu/or32/op-mftspr-op.h: Removed.
* cpu/or32/op-i386.h: Removed.
* cpu/or32/op.c: Removed.
* cpu/or32/sched-i386.h: Removed.
* cpu/or32/dyn32-defs.h: Removed.
* cpu/or32/op-support.c: Removed.
* cpu/or32/op-lwhb-op.h: Removed.
* cpu/or32/op-comp-op.h: Removed.
* cpu/or32/op-support.h: Removed.
* cpu/or32/op-swhb-op.h: Removed.
* cpu/or32/dyn-rec.c: Removed.
* cpu/or32/op-arith-op.h: Removed.
* cpu/or32/op-1t.h: Removed.
* cpu/or32/dyn-rec.h: Removed.
* cpu/or32/op-3t.h: Removed.
* cpu/or32/op-ff1-op.h: Removed.
* cpu/or32/op-t-reg-mov-op.h: Removed.
* cpu/or32/dyngen-i386.c: Removed.
* cpu/or32/def-op-t.h: Removed.
* cpu/or32/op-1t-op.h: Removed.
* cpu/or32/op-2t-op.h: Removed.
* cpu/or32/op-3t-op.h: Removed.
* cpu/or32/common-i386.h: Removed.
* cpu/or32/op-extend-op.h: Removed.
* cpu/or32/dyngen.c: Removed.
* cpu/or32/dyngen-elf.c: Removed.
* cpu/or32/dyngen.h: Removed.
* cpu/or32/i386-regs.h: Removed.
* cpu/or32/op-mac-op.h: Removed.
* cpu/dlx: Removed.
* cpu/dlx/Makefile.in: Removed.
* cpu/dlx/arch.h: Removed.
* cpu/dlx/execute.c: Removed.
* cpu/dlx/Makefile.am: Removed.
* cpu/dlx/.cvsignore: Removed.
* cpu/or16: Removed.
* cpu/or16/.cvsignore: Removed.
* cpu/or32/or32.c: Remove dynamic execution-dependent
sections.
* cpu/or32/execute.c: Ditto.
* cpu/or32/Makefile.am: Ditto.
* cpu/common/abstract.c: Ditto.
* cpu/common/execute.h: Ditto.
* cpu/or1k/sprs.c: Ditto.
* cpu/or1k/opcode/or32.h: Ditto.
* cpu/or1k/except.c: Ditto.
* sim-cmd.c: Ditto.
* configure.ac: Remove dynamic-execution options.
Remove DLX option.
* configure: Regenerated.
* doc/or1ksim.texi <Configuring the Build>: Removed dynamic execution
option information.
2011-05-09 Julius Baxter <julius.baxter@orsoc.se>
* configure: Regenerated.
* configure.ac: Added TUN/TAP header to AC_CHECK_HEADERS
* peripheral/eth.c: Added ifdef HAVE_LINUX_IF_TUN_H around TUN/TAP
code and includes.
* cpu/or1k/spr-defs.h: Fixed page number mask for MMU TLB registers.
Added TLBEIR definition.
Added definitions for SPR_TTMR_TP and SPR_TTCR_CNT. Removed definitions
of SPR_TTMR_PERIOD and SPR_TTMR_CR_PERIOD.
Added PICPR_IPRIO definition.
* testsuite/test-code-or1k/uos/tick.c: Replace SPR_TTMR_PERIOD with
SPR_TTMR_TP and SPR_TTCR_PERIOD with SPR_TTCR_CNT.
* tick/tick.c: Ditto.
* cpu/or1k/spr-dump.c: Ditto.
* testsuite/test-code-or1k/tick/tick.c: Ditto.
Fix continuous timer test.
Remove spurious interrupt test. Believed to be an artifact of incorrect
TTMR/TTCR defines.
* testsuite/or1ksim.tests/tick.exp: Remove spurious interrupt test.
2011-04-28 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version
* debug/debug-unit.c (set_stall_state): Clearing stall state also
clears halted state.
2011-04-08 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version 0.5.1rc1.
2011-03-29 Jonas Bonn <jonas@southpole.se>
* cpu/or1k/sprs.c (mtspr): Setting PICMR always sets the bottom
two bits if we have non-maskable interrupts.
2011-03-27 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version 0.5.0rc3.
2011-03-26 Jeremy Bennett <jeremy.bennett@embecosm.com>
* peripheral/eth.c (eth_open_tap_if): If fail to open the TAP,
then also report the tap device name.
2011-02-24 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
2011-02-22 Giuseppe Scrivano <gscrivano@gnu.org>
* sim-cmd.c (handle_sim_command) [HAVE_LIBREADLINE]: Exit
immediately if no text is read.
2011-01-27 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* cpu/or32/insnset.c <l_nop>: Added behavior for NOP_RANDOM and
NOP_OR1KSIM. Removed default behavior.
* cpu/or1k/spr-defs.h: Added definition of NOP_RANDOM and
NOP_OR1KSIM. Removed definitions of NOP_REPORT_FIRST and
NOP_REPORT_LAST.
* doc/or1ksim.texi <l.nop Opcode Support>: Document l.nop 10 and
l.nop 11.
* libtoplevel.c (or1ksim_init): Replaced srand () by
init_randomness ().
* peripheral/memory.c (mem_reset): Do not allow general reset of
random number generator.
* sim_config.c (parse_args): Change use of rand () to random ().
* toplevel.c (main): Replaced srand () by init_randomness ().
* toplevel-profile.c (main): Replaced srand () by init_randomness ().
* toplevel-support.c (init_randomness): Created.
* toplevel-support.h <init_randomness>: Added.
2011-01-05 Jeremy Bennett <jeremy@jeremybennett.com>
* cpu/common/abstract.c (diassemble_instr): Added instruction
as third parameter. No longer look up in memory.
* cpu/common/abstract.h <diassemble_instr>: Updated prototype.
* cpu/or32/execute.c (trace_instr): Pass instruction as third
parameter to dissassemble_instr. Clearer message when we can't get
a physical address.
2011-01-05 Jeremy Bennett <jeremy@jeremybennett.com>
* cpu/common/abstract.c (diassemble_instr): Start each line with a
flag indicating if user or supervisor mode.
* doc/or1ksim.texi: Updated with new trace flags and explaining
trace ouptut in more detail.
2011-01-05 Jeremy Bennett <jeremy@jeremybennett.com>
* cpu/common/abstract.c (diassemble_instr): Control output of
physical/virtual address with --trace-physical and --trace-virtual
flags.
* sim-config.c (parse_args): Add --trace-physical and
--trace-virtual flags.
* sim-config.h <runtime.sim>: Add trace_phy and trace_virt flags.
2011-01-05 Jeremy Bennett <jeremy@jeremybennett.com>
* cpu/common/abstract.c (diassemble_instr): Added virtual address
as second parameter, used for trace O/P.
* cpu/common/abstract.h <diassemble_instr>: Updated prototype.
* cpu/or32/execute.c (trace_instr): Pass virtual as well as
physical address to disassemble_instr.
2011-01-05 Jeremy Bennett <jeremy@jeremybennett.com>
* configure: Regenerated.
* configure.ac: Updated version.
* cpu/or1k/spr-defs.h: Added definition of NOP_TRACE_ON and
NOP_TRACE_OFF.
* cpu/or32/insnset.c <l_nop>: Added behavior for NOP_TRACE_ON and
NOP_TRACE_OFF
* doc/or1ksim.texi: New section documenting l.nop opcodes.
2011-01-04 Julius Baxter <julius@opencores.org>
* cpu/or32/or32.c: <trace_dest_spr>: Added.
(or1ksim_disassemble_trace_index): Added dumping of SPR content when
disassembling l.mtspr instruction.
* cpu/common/abstract.c:
(disassemble_instr): Added tracing of SPR contents after l.mtspr insn.
* cpu/or1k/opcode/or32.h: (trace_dest_spr): Added extern definition.
2010-12-27 Julius Baxter <julius@opencores.org>
* peripheral/eth.c: <RTX_RESCHED_PERIOD>: Changed to 10000.
(eth_write32): Additional debug output, when enabled.
2010-12-18 Jeremy Bennett <jeremy@jeremybennett.com>
* peripheral/eth.c (eth_write320): Setting ETH_INT_MASK has no
impact on interrupt processing.
* configure: Regenerated.
* configure.ac: Updated version.
2010-12-15 Jeremy Bennett <jeremy@jeremybennett.com>
* peripheral/eth.c <RTX_RESCHED_PERIOD>: Added.
(eth_controller_tx_clock, eth_controller_rx_clock): Reschedule for
RTX_RESCHED_PERIOD.
(eth_controller_tx_clock): dummy_crc parameter controls whether
CRC is added.
(eth_ignore_tap_packet): Deleted.
(eth_ignore_tap_packets): Added (based on eth_ignore_tap_packet).
(eth_reset): I/O opening moved into eth_open_if.
(eth_open_if, eth_open_file_if, eth_open_tap_if): Created.
(eth_regname): Created.
(eth_read32, eth_write32): Unified debug printing.
(eth_dummy_crc): Created.
(eth_sec_start): Initialize dummy_crc.
(reg_ethernet_sec): Add dummy_crc parameter.
* doc/or1ksim.texi: Updated Ethernet configuration section for
dummy_crc.
2010-12-15 Jeremy Bennett <jeremy@jeremybennett.com>
* configure: Regenerated.
* configure.ac: Updated version.
* peripheral/eth.c <mac_broadcast>: Defined to ff:ff:ff:ff:ff:ff.
<struct eth_device>: loopback_offset removed. State reduced to
just BD indices, buffers removed.
(eth_read_rx_file, eth_skip_rx_file, eth_rx_next_packet): Deleted.
(eth_write_file_packet, eth_write_tap_packet, eth_write_packet)
(eth_blush_bd): Created.
(eth_controller_tx_clock): Completely rewritten.
(eth_read_file_packet, eth_read_tap_packet, eth_read_packet)
(eth_fill_bd, eth_ignore_packet): Created.
(eth_controller_rx_clock): Completely rewritten.
(eth_read32, eth_write32): Rewritten for new data structures.
2010-12-09 Julius Baxter <julius@opencores.org>
* doc/or1ksim.texi: changed references to or32-uclinux-* to or32-elf-*.
Added section on using SIGUSR1 signal to control trace dumping.
* peripheral/eth.c: Change scheduling of TX and RX from 10 cycles to 1
when idling.
* toplevel.c: Added SIGUSR1 handler hook.
* toplevel-support.c: <toggle_trace>: New function to toggle the trace
execution control variable.
* toplevel-support.h: <toggle_trace>: Add function prototype.
2010-12-08 Jeremy Bennett <jeremy@jeremybennett.com>
* configure: Regenerated.
* configure.ac: Updated version.
* doc/or1ksim.texi: Updated Ethernet configuration section. Added
new section on configurating TUN/TAP.
2010-12-01 Julius Baxter <julius@opencores.org>
* peripheral/eth.c: <define ETH_DEBUG>: controlling debug printouts.
<struct eth_device>: Added int_line_stat to hold status of IRQ line.
(eth_controller_tx_clock, eth_controller_rx_clock): Add setting of
interrupts dependent on line state, added setting of INT_SOURCE reg.
regardless of INT_MASK bits or line state.
2010-11-30 Julius Baxter <julius@opencores.org>
* cpu/or1k/sprs.c: Clarify commenting on PIC_PICSR register.
* peripheral/eth.c: Many changes.
2010-11-26 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* peripheral/eth.c: Now uses TUN/TAP tunnelling. ETH_PHY
conditional compilation removed throughout.
<struct eth_device>: Redundant fields removed. New fields added.
(eth_controller_tx_clock): Use write to TAP instead of sendto
socket.
(eth_controller_rx_clock): Use read from TAP instead of recv from
socket.
(eth_reset): Socket initialization replaced by opening TAP.
(eth_rtx_type): Now string parameter. Currently "FILE" or "TAP"
permitted.
(eth_tap_dev): Created.
(eth_sock_if): Deleted.
(eth_sec_start, eth_sec_end, reg_ethernet_sec): Updated to add
tap_dev.
* peripheral/etch.h: ETH_PHY conditional compilation removed
throughout.
2010-11-25 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* cpu/or1k/sprs.c (mtspr): Setting PICMR considers NMI usage.
* doc/or1ksim.texi <Interrupt Configuration>: Documented the PIC
use_nmi config.
* libtoplevel.c (or1ksim_interrupt): Does not clear interrupts
immediately.
* NEWS: Updated regarding PIC configuration.
* pic/pic.c (pic_reset): Reference to PICPR
removed. Initialization considers NMI use.
(report_interrupt): NMI now handled through PICMR, rather than
directly in the code.
(pic_use_nmi): Created.
(pic_reg_sec): Added "use_nmi" option.
* sim-config.c (init_defconfig): config.pic.use_nmi initialized.
* sim-config.h <config.pic>: New entry use_nmi added.
2010-11-24 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* doc/or1ksim.texi: More clarification of interrupt behavior when
edge or level triggered.
* pic/pic.c (report_interrupt): Improved warning when interrupt is
reported while previous one is pending.
(clear_interrupt): Now works for both level and edge triggered
interrupts.
2010-11-22 Julius Baxter <julius@opencores.org>
* cpu/common/execute.h <cpu_state>: removed pic_lines variable.
* cpu/or1k/sprs.c: Added comment clarifying PICSR behavior.
* pic/pic.c: Removed use of pic_lines variable, added commenting
clarifying behavior.
<clear_interrupt>: only clear PICSR when level triggered.
* doc/or1ksim.texi (Interrupt Configuration): Added clarification of
interrupt behavior when edge or level triggered.
2010-11-22 Julius Baxter <julius@opencores.org>
* peripheral/eth.c (eth_miim_trans): comment out debug printf()s
* cpu/or32/generate.c (generate_body): Add except_handle call to all
generated illegal instruction cases.
2010-11-22 Jeremy Bennett <jeremy.bennett@embecosm.com>
* peripheral/eth.c (eth-reset): PF_PACKET renamed AF_PACKET.
2010-11-19 Julius Baxter <julius@opencores.org>
* peripheral/eth.c: Added new variable phy_addr to device struct and
ability to set it in config script section. <eth_miim_trans>: function
to emulate MIIM transactions, mainly PHYID regs at the moment.
* peripheral/eth.h: Added MIIM bus defines.
* doc/or1ksim.texi: Added information in eth sectin for phy_addr value
2010-11-11 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* doc/or1ksim.texi: Added information about --trace option
* NEWS: Updated.
2010-10-27 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* cpu/common/abstract.c (disassemble_instr): Initialize store_val
and store_addr to avoid any compiler warnings.
* cpu/or32/or32.c (or1ksim_disassemble_trace_index): Sign extend
trace_store_imm.
2010-10-06 Jeremy Bennett <jeremy.bennett@embecosm.com>
* cpu/or32/or32.c <trace_dest_reg, trace_store_addr_reg>: New globals.
<trace_store_imm, trace_store_val_reg, trace_store_width>: New
globals.
(or1ksim_disassemble_trace_index): Result now void, passes back all
info via globals (yuk, but consistent with what exists). Handles
store addresses.
* cpu/or32/execute.c (trace_instr): Simplified.
* cpu/common/abstract.c (disassemble_instr): Result now void, all
reg info printed here. Handles store addresses.
* cpu/common/abstract.h <disassemble_instr>: Change return type.
* cpu/or1k/opcode/or32.h <trace_dest_reg, trace_store_addr_reg>:
New globals marked extern.
<trace_store_imm, trace_store_val_reg, trace_store_width>: New
globals marked extern.
<or1ksim_disassemble_trace_index>: Change return type.
2010-10-06 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Updated version.
* cpu/or32/or32.c (or1ksim_disassemble_trace_index): Added.
* cpu/or32/execute.c (trace_instr): Added.
(exec_main): Call trace_instr rather than dumpreg if tracing.
* cpu/common/abstract.c (disassemble_instr): Added.
* cpu/common/execute.h <trace_instr>: Added.
* cpu/common/abstract.h <diassemble_instr>: Added.
* cpu/or1k/opcode/or32.h <or1ksim_disassemble_trace_index>: Added.
* libtoplevel.c (or1ksim_run): Call trace_instr rather than
dumpreg if tracing.
2010-10-02 Julius Baxter <julius@opencores.org>
* peripheral/memory.c: Added support for exitnops memory fill option
* doc/or1ksim.texi: Added information about exitnops option
2010-10-02 Jeremy Bennett <jeremy.bennett@embecosm.com>
* Release 0.5.0rc2.
2010-10-02 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Fixed DEJAGNU to always be set, with no user override.
2010-10-02 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.
2010-09-30 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure.ac: Minor tidy ups.
* configure: Regenerated.
2010-09-24 Julius Baxter <julius.baxter@orsoc.se>
* debug/rsp-server.c: Added rsp_query handler entries for new packets
seen with gdb-7.2.
2010-09-20 Jeremy Bennett <jeremy.bennett@embecosm.com>
* cpu/or32/execute.c (exec_main): Dump regs if tracing enabled.
* doc/or1ksim.texi <Usage>: Document -t/--trace.
<Simulator Library>: or1ksim_write_mem second argument is now
const.
* libtoplevel.c (or1ksim_run): Dump regs if tracing enabled.
(or1ksim_write_mem): Second argument is now const.
* or1ksim.h <or1ksim_write_mem>: Second argument is now const.
* sim-config.c (parse_args): New option -t/--trace.
* toplevel.c (main): Remove setting of runtim.sim.hush.
2010-09-07 Jeremy Bennett <jeremy.bennett@embecosm.com>
* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
2010-09-06 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
2010-08-08 Julius Baxter <julius.baxter@orsoc.se>
* cpu/or32/or32.c: Fix compile warning about chars indexing arrays
* cpu/or32/generate.c: Fix compile warning about chars indexing arrays
* sim-cmd.c: Fix compile warning about chars indexing arrays
* peripheral/eth.h: Removed define for MSG_WAITALL under Cygwin
2010-08-06 Julius Baxter <julius.baxter@orsoc.se>
* cpu/or1k/spr-defs.h <SPR_VR_RES>: Fixed value (Thanks to Jonas Bonn)
2010-08-04 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions.
2010-08-03 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or32/execute.c: Remove include of gdbcomm.h.
(exec_main): Remove two tests for config.debug.gdb_enabled.
* cpu/or32/insnset.c <l_nop>: Change test for
config.debug.gdb_enabled to config.debug.enabled for NOP_EXIT
case.
* debug/debug-unit.c (debug_gdb_enabled, debug_server_port):
Deleted.
(debug_rsp_enabled): Remove test for gdb_enabled.
(reg_debug_sec): Remove gdb_enabled and server_port parameters.
* debug/Makefile.am: Remove gdbcomm.c and gdbcomm.h.
* sim-cmd.c: Remove include of gdbcomm.h.
(initialize_readline): Remove conditional setting of
rl_event_hook.
(check_gdbcomm): Deleted.
(handle_sim_command): Remove check of gdb_enabled.
* sim-config.c (init_defconfig): Remove setting of
config.debug.gdb_enabled and config.debug.server_port.
(parse_args): Use --srv and --nosrv to set/clear RSP debugging.
* sim-config.h <struct config>: Removed debug.gdb_enabled and
debug.server_port.
* toplevel-support.c: Remove include of gdbcomm.h.
(sim_init): Remove two tests for gdb_enabled.
2010-08-03 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
2010-08-03 Julius Baxter <julius.baxter@orsoc.se>
* softfloat: Directory for softfloat, software emulation of 32-bit FPU.
* softfloat/Makefile.am: Created.
* softfloat/Makefile.in: Regenerated.
* softfloat/README: Created.
* softfloat/host.h: Created.
* softfloat/milieu.h: Created.
* softfloat/softfloat-macros: Created.
* softfloat/softfloat-specialize: Created.
* softfloat/softfloat.c: Created.
* softfloat/softfloat.h: Created.
* configure: Regenerated.
* configure.ac: Added softfloat path to appropriate places
* Makefile.am: Added softfloat path and library to appropriate places
* Makefile.in: Regenerated.
* cpu/or32/execute-fp.h: deleted
* cpu/or32/execute.c: Updated with FPU flag and rounding mode functions
* cpu/or32/insnset.c: FP insns. now call softfloat functions for ops.
* cpu/or1k/spr-defs.h: Add timer disabled bit
2010-08-01 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
2010-07-30 Julius Baxter <julius.baxter@orsoc.se>
* cpu/or32/execute-fp.h: Added for inclusion by generated execute code
* cpu/or32/execute.c: Added floating point support functions
* cpu/or32/simpl32-defs.h: removed duplicate l_invalid() defn.
* cpu/or32/insnset.c: Add calls to floating point support funcs.
* cpu/or32/generate.c: Added ability to configure includes for execgen
* cpu/or1k/sprs.c: Added FPCSR returning 0 when no hardfloat
* cpu/or1k/spr-defs.h: Added FP group and FPCSR addr and bits defines
* testsuite/test-code-or1k/support/spr-defs.h: ditto
2010-06-31 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* config/dcache-model.c (reg_dc_sec): Upper case enumeration
elements.
* config/icache-model.c (reg_ic_sec): Upper case enumeration
elements.
* cpu/or1k/spr-defs.h <System control and status group>: Add
SPR_GPR_BASE.
* debug/debug-unit.c (reg_debug_sec): Upper case enumeration
elements.
* sim-config.h <enum param_t>: Upper case enumeration elements.
* doc/or1ksim.texi: Delete reference to using include files.
* cuc/cuc.c (reg_cuc_sec): Upper case enumeration elements.
* or1ksim.h <or1ksim_read_mem, or1ksim_write_mem>: Argument order
changed.
<or1ksim_read_reg, or1ksim_write_reg>: Argument as value, not
buffer.
<or1ksim_read_spr, or1ksim_write_spr, or1ksim_set_stall_state>:
Added.
* NEWS: Updated with new features.
* peripheral/gpio.c (reg_gpio_sec): Upper case enumeration
elements.
* peripheral/mc.c (reg_mc_sec): Upper case enumeration elements.
* peripheral/generic.c (reg_generic_sec): Upper case enumeration
elements.
* peripheral/eth.c (reg_eth_sec): Upper case enumeration
elements.
* peripheral/kbd.c (reg_kbd_sec): Upper case enumeration
elements.
* peripheral/fb.c (reg_fb_sec): Upper case enumeration elements.
* peripheral/dma.c (reg_dma_sec): Upper case enumeration
elements.
* peripheral/ata.c (reg_ata_sec): Upper case enumeration
elements.
* peripheral/memory.c (reg_memory_sec): Upper case enumeration
elements.
* peripheral/vga.c (reg_vga_sec): Upper case enumeration
elements.
* peripheral/uart.c (reg_uart_sec): Upper case enumeration
elements.
* mmu/dmmu.c (reg_dmmu_sec): Upper case enumeration elements.
* mmu/immu.c (reg_immu_sec): Upper case enumeration elements.
* vapi/vapi.c (reg_vapi_sec): Upper case enumeration elements.
* bpb/branch-predict.c (reg_bpb_sec): Upper case enumeration
elements.
* cpu-config.c (reg_cpu_sec): Upper case enumeration elements.
* libtoplevel.c: Include debug-unit.h, spr-defs.h and sprs.h
headers.
(or1ksim_step): Deleted.
(or1ksim_read_mem, or1ksim_write_mem): Argument order
changed.
(or1ksim_read_reg, or1ksim_write_reg): Argument as value, not
buffer. Mapped to SPR read/write calls.
(or1ksim_read_spr, or1ksim_write_spr, or1ksim_set_stall_state):
Created.
* pic/pic.c (reg_pic_sec): Upper case enumeration elements.
* pm/pm.c (reg_pm_sec): Upper case enumeration elements.
* sim-config.c <cur_sections>: Global variable deleted and
replaced by local arguments.
<section_master_list>: Renamed from sections.
<read_script_file>: Forward declaration deleted.
(lookup_section, lookup_param): Created.
(set_config_param): Renamed from switch_param. Simplified - no
preceding blanks and string and word representations are
identical.
(next_word, next_lexeme): Created.
(read_script_file): Also search ~/.or1ksim. Use new functions to
get lexemes and to lookup sections and parameters.
(alloc_memory_block): Created.
(parse_args): New arguments -q/--quiet, --report-memory-errors,
-m/--memory. No use of sim.cfg as default config file.
(reg_sim_sec): Upper case enumeration elements.
(set_config): Use new section and parameter lookup functions.
2010-06-31 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/common/abstract.c (setsim_mem32, setsim_mem16, setsim_mem8)
(evalsim_mem32, evalsim_mem16, evalsim_mem8): Only report out of
memory writes if --report-memory-errors is set.
(set_direct32, set_direct16, set_direct8, eval_direct32)
(eval_direct16, eval_direct8): Report memory errors to standard
error.
* cpu/common/parse.c (readfile_elf, identifyfile, loadcode): Use
PRINTFQ for informative messages.
* cpu/or1k/opcode/or32.h <build_automata>: Function declaration
now takes argument.
* cpu/or32/generate.c (main): build_automata takes argument.
* cpu/or32/insnset.c <l_nop>: all output from NOP_EXIT is via
PRINTFQ.
* cpu/or32/or32.c (build_automata). Takes an argument. Only prints
informative output if argument is zero.
* libtoplevel.c (or1ksim_init): Changed syntax to use full
argument vector.
* or1ksim.h <or1ksim_init>: Changed prototype.
* pic/pic.c (pic_reset): Reset message uses PRINTFQ.
* sim-config.c (parse_args): Added new args -q/--quiet and
--report-memory-errors.
* sim-config.h <struct config>: New fields sim.quiet and
sim.report_mem_errs.
* toplevel-support.c (sim_init): Identification message is printed
using PRINTFQ, call to build_automata takes parameter.
2010-07-17 Julius Baxter <julius.baxter@orsoc.se>
* sim-config.c: Adding binary execution trace support
* sim-config.h: Adding binary execution trace options to config struct
* toplevel.c: do_stats variable now set when binary insn. trace enabled
* toplevel-support.c: Added file handling for binary execution trace
* cpu/or32/execute.c: Adding binary execution dump function
* cpu/common/execute.h: Adding proptoype for binary dump function
2010-06-31 Jeremy Bennett <jeremy.bennett@embecosm.com>
* argtable2/argtable2.c (arg_print_formatted): Cast argument to
* configure: Regenerated.
* configure.ac: Version changed to current date.
isspace to int (x2).
* debug/rsp-server.c (rsp_remove_matchpoint)
(rsp_insert_matchpoint): Don't cast pointer to enum. Invalidate
instruction cache before writing.
(rsp_write_mem, rsp_write_mem_bin): Invalidate caches before writing.
* NEWS: Updated for new version
2010-06-29 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or32/insnset.c <l_nop>: On exit, mark cpu as halted if this
is library.
* libtoplevel.c: Add definitions of GDB register numbers.
(or1ksim_init): Initailize config.sim.is_library.
(or1ksim_run): Distinguish between halting and hitting breakpoint,
return if stalled/halted after cpu_cock ().
(or1ksim_step, or1ksim_read_mem, or1ksim_write_mem)
(or1ksim_read_reg, or1ksim_write_reg): New functions.
* NEWS: Updated for new version
* sim-config.c (init_defconfig): Initialize config.sim.is_library.
* sim-config.h <struct config>: Added field sim.is_library.
<struct runtime>: Added field cpu.halted.
2010-06-22 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to 0.4.0.
* NEWS: Updated for 0.4.0.
2010-06-16 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to 0.4.0rc2. New conditional to
allow l.xori to have unsigned immediate operand.
* cpu/or32/or32.c <or32_opcodes>: l.xori optionally uses unsigned
immediate.
* doc/or1ksim.texi: Updated with enable-unsigned-xori config
option.
* NEWS: Updated with new bugs fixed.
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date. enable-arith-flag
and enable-ov-flag config options removed.
* cpu/or32/insnset.c <l_mfspr, l_mtspr>: Use bitwise OR, not
addition to calculate SPR address.
<l_and, l_or, l_sll, l_sra, l_srl, l_xor>: Do not now affect CY and OV
flags.
<l_sub>: Sets OV and CY flags correctly, and triggers Range
Exception if required.
* doc/or1ksim.texi: Updated to remove enable-arith-flag and
enable-ov-flag config options.
* NEWS: Updated with new bugs fixed.
2010-06-14 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.