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ib_mlx5dv_md.c
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ib_mlx5dv_md.c
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/**
* Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2019. ALL RIGHTS RESERVED.
*
* See file LICENSE for terms.
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include <uct/ib/mlx5/ib_mlx5.h>
#include <ucs/arch/bitops.h>
#include <ucs/profile/profile.h>
#include <ucs/sys/ptr_arith.h>
#include <ucs/time/time.h>
/* max log value to store in uint8_t */
#define UCT_IB_MLX5_MD_MAX_DCI_CHANNELS 8
#define UCT_IB_MLX5_MD_UMEM_ACCESS \
(IBV_ACCESS_LOCAL_WRITE | IBV_ACCESS_REMOTE_READ | IBV_ACCESS_REMOTE_WRITE)
static uint32_t uct_ib_mlx5_flush_rkey_make()
{
return ((getpid() & 0xff) << 8) | UCT_IB_MD_INVALID_FLUSH_RKEY;
}
#if HAVE_DEVX
static const char uct_ib_mkey_token[] = "uct_ib_mkey_token";
typedef struct uct_ib_mlx5_dbrec_page {
uct_ib_mlx5_devx_umem_t mem;
} uct_ib_mlx5_dbrec_page_t;
static size_t uct_ib_mlx5_calc_mkey_inlen(int list_size)
{
return UCT_IB_MLX5DV_ST_SZ_BYTES(create_mkey_in) +
UCT_IB_MLX5DV_ST_SZ_BYTES(klm) * list_size;
}
static ucs_status_t uct_ib_mlx5_alloc_mkey_inbox(int list_size, char **in_p)
{
size_t inlen;
char *in;
inlen = uct_ib_mlx5_calc_mkey_inlen(list_size);
in = ucs_calloc(1, inlen, "mkey mailbox");
if (in == NULL) {
return UCS_ERR_NO_MEMORY;
}
*in_p = in;
return UCS_OK;
}
static ucs_status_t
uct_ib_mlx5_devx_reg_ksm(uct_ib_mlx5_md_t *md, uint64_t address, size_t length,
int atomic, uint32_t mkey_index, const char *reason,
int list_size, size_t entity_size, char *in,
struct mlx5dv_devx_obj **mr_p, uint32_t *mkey)
{
char out[UCT_IB_MLX5DV_ST_SZ_BYTES(create_mkey_out)] = {};
struct mlx5dv_devx_obj *mr;
void *mkc;
UCT_IB_MLX5DV_SET(create_mkey_in, in, opcode, UCT_IB_MLX5_CMD_OP_CREATE_MKEY);
UCT_IB_MLX5DV_SET(create_mkey_in, in, input_mkey_index, mkey_index);
mkc = UCT_IB_MLX5DV_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
UCT_IB_MLX5DV_SET(mkc, mkc, access_mode_1_0, UCT_IB_MLX5_MKC_ACCESS_MODE_KSM);
UCT_IB_MLX5DV_SET(mkc, mkc, a, !!atomic);
UCT_IB_MLX5DV_SET(mkc, mkc, rw, 1);
UCT_IB_MLX5DV_SET(mkc, mkc, rr, 1);
UCT_IB_MLX5DV_SET(mkc, mkc, lw, 1);
UCT_IB_MLX5DV_SET(mkc, mkc, lr, 1);
UCT_IB_MLX5DV_SET(mkc, mkc, pd, uct_ib_mlx5_devx_md_get_pdn(md));
UCT_IB_MLX5DV_SET(mkc, mkc, translations_octword_size, list_size);
UCT_IB_MLX5DV_SET(mkc, mkc, log_entity_size, ucs_ilog2(entity_size));
UCT_IB_MLX5DV_SET(mkc, mkc, qpn, 0xffffff);
UCT_IB_MLX5DV_SET(mkc, mkc, mkey_7_0, md->mkey_tag);
UCT_IB_MLX5DV_SET64(mkc, mkc, start_addr, address);
UCT_IB_MLX5DV_SET64(mkc, mkc, len, length);
UCT_IB_MLX5DV_SET(create_mkey_in, in, translations_octword_actual_size, list_size);
mr = UCS_PROFILE_NAMED_CALL_ALWAYS("devx_create_mkey",
mlx5dv_devx_obj_create,
md->super.dev.ibv_context, in,
uct_ib_mlx5_calc_mkey_inlen(list_size),
out, sizeof(out));
if (mr == NULL) {
ucs_debug("%s: mlx5dv_devx_obj_create(CREATE_MKEY, mode=KSM, "
"start_addr=0x%lx length=%zu) failed, syndrome 0x%x: %m",
uct_ib_device_name(&md->super.dev), address, length,
UCT_IB_MLX5DV_GET(create_mkey_out, out, syndrome));
return UCS_ERR_UNSUPPORTED;
}
*mr_p = mr;
*mkey = (UCT_IB_MLX5DV_GET(create_mkey_out, out, mkey_index) << 8) |
md->mkey_tag;
if (reason != NULL) {
ucs_trace("%s: registered KSM%s for %s %lx..%lx with %d entries of %zu "
"bytes, mkey=0x%x mr=%p",
uct_ib_device_name(&md->super.dev), atomic ? " atomic" : "",
reason, address, address + length, list_size, entity_size,
*mkey, mr);
}
return UCS_OK;
}
static void uct_ib_mlx5_devx_ksm_log(uct_ib_mlx5_md_t *md, void *address,
size_t length, uint64_t iova, int atomic,
int mt, uint32_t mkey_index,
const char *reason, ucs_status_t status)
{
ucs_assert(reason != NULL);
ucs_debug("%s: KSM%s %s memory registration status \"%s\" "
"range %p..%p iova 0x%" PRIx64 "%s mkey_index 0x%x",
uct_ib_device_name(&md->super.dev), mt ? "-mt" : "", reason,
ucs_status_string(status), address,
UCS_PTR_BYTE_OFFSET(address, length), iova,
atomic ? " atomic" : "", mkey_index);
}
static void uct_ib_mlx5_devx_ksm_list_log(uct_ib_mlx5_md_t *md, void *address,
size_t length, uint64_t iova, int mt,
const char *reason)
{
ucs_trace("%s: init KSM%s list %s address %p length %zu iova 0x%" PRIx64,
uct_ib_device_name(&md->super.dev), mt ? "-mt" : "", reason,
address, length, iova);
}
static void uct_ib_mlx5_devx_klm_entry_set(void **klm_p, size_t klm_idx,
void *address, struct ibv_mr *mr)
{
void *klm = *klm_p;
ucs_trace("klm[%ld] va %p mr [addr %p len %zu lkey 0x%x]", klm_idx, address,
mr->addr, mr->length, mr->lkey);
UCT_IB_MLX5DV_SET64(klm, klm, address, (uintptr_t)address);
UCT_IB_MLX5DV_SET(klm, klm, mkey, mr->lkey);
*klm_p = UCS_PTR_BYTE_OFFSET(klm, UCT_IB_MLX5DV_ST_SZ_BYTES(klm));
}
/*
* Register KSM data for given memory handle. Can work only with MRs
* that were registered in multi-threaded mode.
*/
static ucs_status_t
uct_ib_mlx5_devx_reg_ksm_data_mt(uct_ib_mlx5_md_t *md, void *address,
uint64_t iova, int atomic, uint32_t mkey_index,
const char *reason,
uct_ib_mlx5_devx_ksm_data_t *ksm_data,
struct mlx5dv_devx_obj **mr_p, uint32_t *mkey)
{
size_t chunk_size = md->super.config.mt_reg_chunk;
size_t padding = (uintptr_t)address % chunk_size; /* before first mr */
void* mr_address = UCS_PTR_BYTE_OFFSET(address, -padding);
size_t list_size = ksm_data->mr_num;
ucs_status_t status;
struct ibv_mr **mr;
char *in;
void *klm;
status = uct_ib_mlx5_alloc_mkey_inbox(list_size + 1, &in);
if (status != UCS_OK) {
goto out;
}
uct_ib_mlx5_devx_ksm_list_log(md, address, ksm_data->length, iova, 1,
reason);
ucs_log_indent(+1);
klm = UCT_IB_MLX5DV_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
ucs_carray_for_each(mr, ksm_data->mrs, ksm_data->mr_num) {
uct_ib_mlx5_devx_klm_entry_set(&klm, mr - ksm_data->mrs, mr_address,
*mr);
mr_address = UCS_PTR_BYTE_OFFSET(mr_address, chunk_size);
}
if ((void*)iova != address) {
/* Add offset to workaround CREATE_MKEY range check issue */
uct_ib_mlx5_devx_klm_entry_set(&klm, list_size, mr_address,
ksm_data->mrs[ksm_data->mr_num - 1]);
++list_size;
}
ucs_log_indent(-1);
status = uct_ib_mlx5_devx_reg_ksm(md, iova - padding,
ksm_data->length + padding, atomic,
mkey_index, reason, list_size,
chunk_size, in, mr_p, mkey);
ucs_free(in);
uct_ib_mlx5_devx_ksm_log(md, address, ksm_data->length, iova, atomic, 1,
mkey_index, reason, status);
out:
return status;
}
static ucs_status_t uct_ib_mlx5_devx_reg_ksm_data_addr(
uct_ib_mlx5_md_t *md, void *address, size_t length, uint64_t iova,
int atomic, uint32_t mkey_index, const char *reason, struct ibv_mr *mr,
int list_size, struct mlx5dv_devx_obj **mr_p, uint32_t *mkey)
{
ucs_status_t status;
void *klm;
char *in;
int i;
status = uct_ib_mlx5_alloc_mkey_inbox(list_size, &in);
if (status != UCS_OK) {
return status;
}
uct_ib_mlx5_devx_ksm_list_log(md, address, length, iova, 0, reason);
ucs_log_indent(+1);
klm = UCT_IB_MLX5DV_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
for (i = 0; i < list_size; i++) {
uct_ib_mlx5_devx_klm_entry_set(
&klm, i,
UCS_PTR_BYTE_OFFSET(address, i * UCT_IB_MD_MAX_MR_SIZE), mr);
}
ucs_log_indent(-1);
status = uct_ib_mlx5_devx_reg_ksm(md, iova, length, atomic, mkey_index,
reason, list_size, UCT_IB_MD_MAX_MR_SIZE,
in, mr_p, mkey);
ucs_free(in);
uct_ib_mlx5_devx_ksm_log(md, address, length, iova, atomic, 0, mkey_index,
reason, status);
return status;
}
/*
* Register KSM data for given memory handle. Can work only with MRs
* that were registered in single-threaded mode.
*/
static ucs_status_t uct_ib_mlx5_devx_reg_ksm_data_contig(
uct_ib_mlx5_md_t *md, void *address, uint64_t iova, int atomic,
uint32_t mkey_index, const char *reason, uct_ib_mlx5_devx_mr_t *mr,
struct mlx5dv_devx_obj **mr_p, uint32_t *mkey)
{
size_t mr_length = mr->super.ib->length;
uint64_t ksm_address;
uint64_t ksm_iova;
size_t ksm_length;
int list_size;
/* FW requires indirect atomic MR address and length to be aligned
* to max supported atomic argument size */
ksm_address = ucs_align_down_pow2((uint64_t)address, UCT_IB_MD_MAX_MR_SIZE);
ksm_iova = ksm_address - (uint64_t)address + iova;
ksm_length = mr_length + (uint64_t)address - ksm_address;
ksm_length = ucs_align_up(ksm_length, md->super.dev.atomic_align);
/* Add offset to workaround CREATE_MKEY range check issue */
list_size = ucs_div_round_up(ksm_length + ucs_get_page_size(),
UCT_IB_MD_MAX_MR_SIZE);
return uct_ib_mlx5_devx_reg_ksm_data_addr(md, (void*)ksm_address,
ksm_length, ksm_iova, atomic,
mkey_index, reason, mr->super.ib,
list_size, mr_p, mkey);
}
static void *
uct_ib_mlx5_devx_memh_base_address(const uct_ib_mlx5_devx_mem_t *memh)
{
#if HAVE_IBV_DM
if (memh->dm != NULL) {
/* Device memory memory key is zero based */
return NULL;
}
#endif
return memh->address;
}
/**
* Pop MR LRU-entry from @a md cash
*/
static void
uct_ib_mlx5_devx_md_mr_lru_pop(uct_ib_mlx5_md_t *md, const char *reason)
{
uct_ib_mlx5_mem_lru_entry_t *head;
struct mlx5dv_devx_obj *mr;
khint_t iter;
ucs_assert(!ucs_list_is_empty(&md->lru_rkeys.list));
head = ucs_list_extract_head(&md->lru_rkeys.list,
uct_ib_mlx5_mem_lru_entry_t, list);
ucs_trace("%s: pop mkey 0x%x from LRU because of %s",
uct_ib_device_name(&md->super.dev), head->rkey, reason);
iter = kh_get(rkeys, &md->lru_rkeys.hash, head->rkey);
ucs_assertv_always(iter != kh_end(&md->lru_rkeys.hash),
"%s: LRU mkey 0x%x not found",
uct_ib_device_name(&md->super.dev), head->rkey);
mr = kh_val(&md->lru_rkeys.hash, iter)->indirect_mr;
if ((mr != NULL) && head->is_dummy) {
ucs_debug("%s: destroy dvmr %p with key 0x%x",
uct_ib_device_name(&md->super.dev), mr, head->rkey);
uct_ib_mlx5_devx_obj_destroy(mr, "MKEY, LRU_INDIRECT");
}
kh_del(rkeys, &md->lru_rkeys.hash, iter);
ucs_free(head);
}
static void
uct_ib_md_mlx5_devx_mr_lru_entry_update(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_mem_lru_entry_t *entry,
struct mlx5dv_devx_obj *mr)
{
/* 2nd state of an entry must be resetting to NULL since the mr is
* destroyed or vice-versa */
ucs_assertv((entry->indirect_mr == NULL) != (mr == NULL),
"indirect_mr=%p mr=%p", entry->indirect_mr, mr);
entry->indirect_mr = mr;
/* move to the end of the list */
ucs_list_del(&entry->list);
ucs_list_add_tail(&md->lru_rkeys.list, &entry->list);
}
/**
* Cash @a mr with @a rkey on @a md.
* @param [in] md Memory domain.
* @param [in] rkey Remote key.
* @param [in] mr Memory region handle.
* @return Error code.
*/
static ucs_status_t
uct_ib_md_mlx5_devx_mr_lru_push(uct_ib_mlx5_md_t *md, uint32_t rkey, void *mr)
{
uct_ib_mlx5_mem_lru_entry_t *entry;
khint_t iter;
ucs_kh_put_t res;
ucs_assert(rkey != UCT_IB_INVALID_MKEY);
iter = kh_put(rkeys, &md->lru_rkeys.hash, rkey, &res);
if (ucs_unlikely(res == UCS_KH_PUT_FAILED)) {
ucs_error("Cannot allocate rkey LRU hash entry");
return UCS_ERR_NO_MEMORY;
}
if (res == UCS_KH_PUT_KEY_PRESENT) {
ucs_trace("%s: mr lru size=%d reset: %x->%p",
uct_ib_device_name(&md->super.dev),
kh_size(&md->lru_rkeys.hash), rkey, mr);
entry = kh_val(&md->lru_rkeys.hash, iter);
ucs_assertv(entry->rkey == rkey, "entry_rkey=0x%x, rkey=0x%x",
entry->rkey, rkey);
uct_ib_md_mlx5_devx_mr_lru_entry_update(md, entry, mr);
entry->is_dummy = 1;
return UCS_ERR_ALREADY_EXISTS;
}
if (mr == NULL) {
ucs_trace("%s: mr lru size=%d miss: %x",
uct_ib_device_name(&md->super.dev),
kh_size(&md->lru_rkeys.hash), rkey);
/* trying to reset non-exist entry, del empty iter */
kh_del(rkeys, &md->lru_rkeys.hash, iter);
return UCS_ERR_NO_ELEM;
}
if (kh_size(&md->lru_rkeys.hash) >= md->super.config.max_idle_rkey_count) {
uct_ib_mlx5_devx_md_mr_lru_pop(md, "limit");
}
entry = ucs_malloc(sizeof(*entry), "rkey_lru_entry");
if (entry == NULL) {
ucs_error("Cannot allocate rkey LRU entry");
return UCS_ERR_NO_MEMORY;
}
entry->indirect_mr = mr;
entry->rkey = rkey;
entry->is_dummy = 0;
ucs_list_add_tail(&md->lru_rkeys.list, &entry->list);
kh_val(&md->lru_rkeys.hash, iter) = entry;
ucs_trace("%s: push mkey 0x%x mr %p to LRU",
uct_ib_device_name(&md->super.dev), rkey, mr);
ucs_trace("%s: mr lru size=%d push: %x->%p", uct_ib_device_name(&md->super.dev),
kh_size(&md->lru_rkeys.hash), rkey, mr);
if ((++md->lru_rkeys.count % md->super.config.max_idle_rkey_count) == 0) {
/* Increment mkey tag in order to mitigate the rkey collision risk */
md->mkey_tag = (md->mkey_tag + 1) % UCT_IB_MLX5_MKEY_TAG_MAX;
}
return UCS_OK;
}
static void uct_ib_mlx5_devx_mr_lru_init(uct_ib_mlx5_md_t *md)
{
ucs_list_head_init(&md->lru_rkeys.list);
kh_init_inplace(rkeys, &md->lru_rkeys.hash);
md->lru_rkeys.count = 0;
}
static void uct_ib_mlx5_devx_mr_lru_cleanup(uct_ib_mlx5_md_t *md)
{
while (!ucs_list_is_empty(&md->lru_rkeys.list)) {
uct_ib_mlx5_devx_md_mr_lru_pop(md, "cleanup");
}
ucs_assertv(kh_size(&md->lru_rkeys.hash) == 0,
"%s: %d LRU cache entries are leaked",
uct_ib_device_name(&md->super.dev),
kh_size(&md->lru_rkeys.hash));
kh_destroy_inplace(rkeys, &md->lru_rkeys.hash);
}
/*
* Register KSM data for given memory handle. Distinguish the way of KSM creation
* structures filling by checking UCT_IB_MEM_MULTITHREADED flag.
*/
static ucs_status_t
uct_ib_mlx5_devx_reg_ksm_data(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh,
uct_ib_mr_type_t mr_type, uint32_t iova_offset,
int atomic, uint32_t mkey_index,
const char *reason, struct mlx5dv_devx_obj **mr_p,
uint32_t *mkey)
{
uct_ib_mlx5_devx_mr_t *mr = &memh->mrs[mr_type];
void *address = uct_ib_mlx5_devx_memh_base_address(memh);
uint64_t iova = (uint64_t)memh->address + iova_offset;
if (memh->super.flags & UCT_IB_MEM_MULTITHREADED) {
return uct_ib_mlx5_devx_reg_ksm_data_mt(md, address, iova, atomic,
mkey_index, reason,
mr->ksm_data, mr_p, mkey);
} else {
return uct_ib_mlx5_devx_reg_ksm_data_contig(md, address, iova, atomic,
mkey_index, reason, mr,
mr_p, mkey);
}
}
UCS_PROFILE_FUNC_ALWAYS(ucs_status_t, uct_ib_mlx5_devx_reg_indirect_key,
(md, memh), uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh)
{
ucs_status_t status;
ucs_assertv(md->flags & UCT_IB_MLX5_MD_FLAG_KSM, "md %p: name %s", md,
md->super.name);
do {
status = uct_ib_mlx5_devx_reg_ksm_data(md, memh, UCT_IB_MR_DEFAULT, 0,
0, 0, "indirect-key",
&memh->indirect_dvmr,
&memh->indirect_rkey);
if (status != UCS_OK) {
break;
}
/* This loop is guaranteed to finish because eventually all entries in
* the LRU will have an associated indirect_mr object, so the next key
* we will get from HW will be a new value not in the LRU. */
status = uct_ib_md_mlx5_devx_mr_lru_push(md, memh->indirect_rkey,
memh->indirect_dvmr);
} while (status == UCS_ERR_ALREADY_EXISTS);
if (status != UCS_OK) {
ucs_error("%s: LRU push returned %s",
uct_ib_device_name(&md->super.dev),
ucs_status_string(status));
return status;
}
return UCS_OK;
}
static UCS_F_ALWAYS_INLINE uint32_t uct_ib_mlx5_mkey_index(uint32_t mkey)
{
return mkey >> 8;
}
static UCS_F_ALWAYS_INLINE uct_ib_mr_type_t uct_ib_devx_get_atomic_mr_type(
uct_ib_md_t *md, const uct_ib_mlx5_devx_mem_t *memh)
{
#if HAVE_IBV_DM
/* Device memory only supports default mr */
if (memh->dm != NULL) {
return UCT_IB_MR_DEFAULT;
}
#endif
return uct_ib_md_get_atomic_mr_type(md);
}
UCS_PROFILE_FUNC_ALWAYS(ucs_status_t, uct_ib_mlx5_devx_reg_atomic_key,
(md, memh), uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh)
{
uct_ib_mr_type_t mr_type = uct_ib_devx_get_atomic_mr_type(&md->super, memh);
uint8_t mr_id = uct_ib_md_get_atomic_mr_id(&md->super);
uint32_t atomic_offset = uct_ib_md_atomic_offset(mr_id);
uint32_t mkey_index;
int is_atomic;
if (memh->smkey_mr != NULL) {
mkey_index = uct_ib_mlx5_mkey_index(memh->super.rkey) +
md->super.mkey_by_name_reserve.size;
} else {
mkey_index = 0;
}
is_atomic = memh->super.flags & UCT_IB_MEM_ACCESS_REMOTE_ATOMIC;
return uct_ib_mlx5_devx_reg_ksm_data(md, memh, mr_type, atomic_offset,
is_atomic, mkey_index, "atomic-key",
&memh->atomic_dvmr,
&memh->atomic_rkey);
}
static ucs_status_t
uct_ib_mlx5_devx_reg_mt(uct_ib_mlx5_md_t *md, void *address, size_t length,
int is_atomic, const uct_md_mem_reg_params_t *params,
uint64_t access_flags, uint32_t *mkey_p,
uct_ib_mlx5_devx_ksm_data_t **ksm_data_p)
{
size_t chunk_size = md->super.config.mt_reg_chunk;
size_t atomic_prefix = (uintptr_t)address % md->super.dev.atomic_align;
void* prefix_address = (void*)((uintptr_t)address - atomic_prefix);
size_t padding = ucs_padding((uintptr_t)prefix_address, chunk_size);
uct_ib_mlx5_devx_ksm_data_t *ksm_data;
ucs_status_t status;
int dmabuf_fd;
int mr_num;
length += atomic_prefix;
if (!(md->flags & UCT_IB_MLX5_MD_FLAG_KSM) ||
(is_atomic && !(md->flags & UCT_IB_MLX5_MD_FLAG_INDIRECT_ATOMICS))) {
return UCS_ERR_UNSUPPORTED;
}
/* Multi-threaded registration does not support dmabuf */
dmabuf_fd = UCS_PARAM_VALUE(UCT_MD_MEM_REG_FIELD, params, dmabuf_fd,
DMABUF_FD, UCT_DMABUF_FD_INVALID);
if (dmabuf_fd != UCT_DMABUF_FD_INVALID) {
return UCS_ERR_UNSUPPORTED;
}
mr_num = ucs_div_round_up(length - padding, chunk_size);
if (padding > 0) {
++mr_num;
}
ucs_trace("multithreaded register memory %p..%p chunks %d origin addr %p "
"atomic align %d prefix length %ld",
prefix_address, UCS_PTR_BYTE_OFFSET(prefix_address, length),
mr_num, address, md->super.dev.atomic_align, atomic_prefix);
ksm_data = ucs_malloc((mr_num * sizeof(*ksm_data->mrs)) + sizeof(*ksm_data),
"ksm_data");
if (ksm_data == NULL) {
status = UCS_ERR_NO_MEMORY;
goto err;
}
ksm_data->mr_num = mr_num;
ksm_data->length = length;
status = uct_ib_md_handle_mr_list_mt(&md->super, prefix_address, length, params,
access_flags, mr_num, ksm_data->mrs);
if (status != UCS_OK) {
goto err_free;
}
status = uct_ib_mlx5_devx_reg_ksm_data_mt(md, prefix_address,
(uint64_t)prefix_address,
is_atomic, 0, "multi-thread-key",
ksm_data, &ksm_data->dvmr,
mkey_p);
if (status != UCS_OK) {
goto err_dereg;
}
*ksm_data_p = ksm_data;
return UCS_OK;
err_dereg:
uct_ib_md_handle_mr_list_mt(&md->super, address, length, NULL, 0,
mr_num, ksm_data->mrs);
err_free:
ucs_free(ksm_data);
err:
return status;
}
static ucs_status_t
uct_ib_mlx5_devx_dereg_mt(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_ksm_data_t *ksm_data)
{
ucs_status_t status;
struct ibv_mr **mr;
ucs_trace("%s: destroy KSM %p", uct_ib_device_name(&md->super.dev),
ksm_data->dvmr);
status = uct_ib_mlx5_devx_obj_destroy(ksm_data->dvmr, "MKEY, KSM");
if (status != UCS_OK) {
return status;
}
status = uct_ib_md_handle_mr_list_mt(&md->super, ksm_data->mrs[0]->addr,
ksm_data->length, NULL, 0,
ksm_data->mr_num, ksm_data->mrs);
if (status == UCS_ERR_UNSUPPORTED) {
/* Fallback to direct deregistration */
ucs_carray_for_each(mr, ksm_data->mrs, ksm_data->mr_num) {
status = uct_ib_dereg_mr(*mr);
if (status != UCS_OK) {
return status;
}
}
} else if (status != UCS_OK) {
return status;
}
ucs_free(ksm_data);
return status;
}
static void uct_ib_mlx5_devx_reg_symmetric(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh,
void *address)
{
uint32_t start = md->smkey_index;
struct mlx5dv_devx_obj *smkey_mr;
uint32_t symmetric_rkey;
ucs_status_t status;
ucs_assert(!(memh->super.flags & UCT_IB_MEM_MULTITHREADED));
/* Best effort, only allocate in the range below the atomic keys. */
while (md->smkey_index < md->super.mkey_by_name_reserve.size) {
status = uct_ib_mlx5_devx_reg_ksm_data_contig(
md, address, (uint64_t)address,
(memh->super.flags & UCT_IB_MEM_ACCESS_REMOTE_ATOMIC),
md->super.mkey_by_name_reserve.base + md->smkey_index,
"symmetric-key", &memh->mrs[UCT_IB_MR_DEFAULT], &smkey_mr,
&symmetric_rkey);
if (status == UCS_OK) {
memh->smkey_mr = smkey_mr;
memh->super.rkey = symmetric_rkey;
md->smkey_index++;
return;
}
/* Use blocks of 8 mkeys, first mkey creation gives block ownership.
* Try from the start of the next block if any failure.
*/
md->smkey_index = ucs_align_up_pow2(md->smkey_index + 1,
md->super.config.smkey_block_size);
}
ucs_debug("%s: failed to allocate symmetric key start index 0x%x size %u",
uct_ib_device_name(&md->super.dev),
md->super.mkey_by_name_reserve.base + start,
md->super.mkey_by_name_reserve.size);
}
static UCS_F_ALWAYS_INLINE int
uct_ib_mlx5_devx_symmetric_rkey(const uct_ib_mlx5_md_t *md, unsigned flags)
{
return (flags & UCT_MD_MEM_SYMMETRIC_RKEY) &&
(md->flags & UCT_IB_MLX5_MD_FLAG_MKEY_BY_NAME_RESERVE);
}
static ucs_status_t
uct_ib_mlx5_devx_reg_mr(uct_ib_mlx5_md_t *md, uct_ib_mlx5_devx_mem_t *memh,
void *address, size_t length,
const uct_md_mem_reg_params_t *params,
uct_ib_mr_type_t mr_type, uint64_t access_mask,
uint32_t *lkey_p, uint32_t *rkey_p)
{
uint64_t access_flags = uct_ib_memh_access_flags(&md->super, &memh->super) &
access_mask;
unsigned flags = UCT_MD_MEM_REG_FIELD_VALUE(params, flags,
FIELD_FLAGS, 0);
ucs_status_t status;
uint32_t mkey;
if ((length >= md->super.config.min_mt_reg) &&
!(access_flags & IBV_ACCESS_ON_DEMAND) &&
!uct_ib_mlx5_devx_symmetric_rkey(md, flags)) {
/* Verbs transports can issue atomic operations to the default key */
status = uct_ib_mlx5_devx_reg_mt(md, address, length,
(memh->super.flags &
UCT_IB_MEM_ACCESS_REMOTE_ATOMIC),
params, access_flags, &mkey,
&memh->mrs[mr_type].ksm_data);
if (status == UCS_OK) {
*rkey_p = *lkey_p = mkey;
memh->super.flags |= UCT_IB_MEM_MULTITHREADED;
return UCS_OK;
} else if (status != UCS_ERR_UNSUPPORTED) {
return status;
}
/* Fallback if multi-thread registration is unsupported */
}
status = uct_ib_reg_mr(&md->super, address, length, params, access_flags,
NULL, &memh->mrs[mr_type].super.ib);
if (status != UCS_OK) {
return status;
}
*lkey_p = memh->mrs[mr_type].super.ib->lkey;
*rkey_p = memh->mrs[mr_type].super.ib->rkey;
return UCS_OK;
}
static ucs_status_t uct_ib_mlx5_devx_dereg_mr(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh,
uct_ib_mr_type_t mr_type)
{
if (memh->super.flags & UCT_IB_MEM_MULTITHREADED) {
return uct_ib_mlx5_devx_dereg_mt(md, memh->mrs[mr_type].ksm_data);
} else {
return uct_ib_dereg_mr(memh->mrs[mr_type].super.ib);
}
}
static ucs_status_t
uct_ib_mlx5_devx_memh_alloc(uct_ib_mlx5_md_t *md, size_t length,
unsigned flags, size_t mr_size,
uct_ib_mlx5_devx_mem_t **memh_p)
{
uct_ib_mlx5_devx_mem_t *memh;
uct_ib_mem_t *ib_memh;
ucs_status_t status;
status = uct_ib_memh_alloc(&md->super, length, flags, sizeof(*memh),
mr_size, &ib_memh);
if (status != UCS_OK) {
return status;
}
memh = ucs_derived_of(ib_memh, uct_ib_mlx5_devx_mem_t);
memh->exported_lkey = UCT_IB_INVALID_MKEY;
memh->atomic_rkey = UCT_IB_INVALID_MKEY;
memh->indirect_rkey = UCT_IB_INVALID_MKEY;
*memh_p = memh;
return UCS_OK;
}
ucs_status_t
uct_ib_mlx5_devx_mem_reg(uct_md_h uct_md, void *address, size_t length,
const uct_md_mem_reg_params_t *params,
uct_mem_h *memh_p)
{
uct_ib_mlx5_md_t *md = ucs_derived_of(uct_md, uct_ib_mlx5_md_t);
unsigned flags = UCT_MD_MEM_REG_FIELD_VALUE(params, flags, FIELD_FLAGS, 0);
uct_ib_mlx5_devx_mem_t *memh;
ucs_status_t status;
uint32_t dummy_mkey;
status = uct_ib_mlx5_devx_memh_alloc(md, length, flags,
sizeof(memh->mrs[0]), &memh);
if (status != UCS_OK) {
goto err;
}
status = uct_ib_mlx5_devx_reg_mr(md, memh, address, length, params,
UCT_IB_MR_DEFAULT, UINT64_MAX,
&memh->super.lkey, &memh->super.rkey);
if (status != UCS_OK) {
goto err_memh_free;
}
if (uct_ib_mlx5_devx_symmetric_rkey(md, flags)) {
uct_ib_mlx5_devx_reg_symmetric(md, memh, address);
}
if (md->super.relaxed_order) {
status = uct_ib_mlx5_devx_reg_mr(md, memh, address, length, params,
UCT_IB_MR_STRICT_ORDER,
~IBV_ACCESS_RELAXED_ORDERING,
&dummy_mkey, &dummy_mkey);
if (status != UCS_OK) {
goto err_dereg_default;
}
}
if (md->super.config.odp.prefetch) {
uct_ib_mem_prefetch(&md->super, &memh->super, address, length);
}
memh->address = address;
*memh_p = memh;
return UCS_OK;
err_dereg_default:
uct_ib_mlx5_devx_dereg_mr(md, memh, UCT_IB_MR_DEFAULT);
err_memh_free:
ucs_free(memh);
err:
return status;
}
static ucs_status_t
uct_ib_devx_dereg_invalidate_rkey_check(uct_ib_mlx5_md_t *md,
uct_ib_mlx5_devx_mem_t *memh,
uint32_t rkey, unsigned flags_mask,
uint64_t cap_mask, const char *name)
{
if (!(memh->super.flags & flags_mask)) {
return UCS_OK;
}
if (!(md->super.cap_flags & cap_mask)) {
ucs_debug("%s: invalidate %s is not supported (rkey=0x%x)",
uct_ib_device_name(&md->super.dev), name, rkey);
return UCS_ERR_UNSUPPORTED;
}
if (rkey == UCT_IB_INVALID_MKEY) {
return UCS_ERR_INVALID_PARAM;
}
return UCS_OK;
}
static ucs_status_t uct_ib_devx_dereg_invalidate_params_check(
uct_ib_mlx5_md_t *md, const uct_md_mem_dereg_params_t *params)
{
uct_ib_mlx5_devx_mem_t *memh;
ucs_status_t status;
unsigned flags;
flags = UCT_MD_MEM_DEREG_FIELD_VALUE(params, flags, FIELD_FLAGS, 0);
if (!(flags & UCT_MD_MEM_DEREG_FLAG_INVALIDATE)) {
return UCS_OK;
}
memh = UCT_MD_MEM_DEREG_FIELD_VALUE(params, memh, FIELD_MEMH, NULL);
status = uct_ib_devx_dereg_invalidate_rkey_check(
md, memh, memh->indirect_rkey, UCT_IB_MEM_ACCESS_REMOTE_RMA,
UCT_MD_FLAG_INVALIDATE_RMA, "RMA");
if (status != UCS_OK) {
return status;
}
return uct_ib_devx_dereg_invalidate_rkey_check(
md, memh, memh->atomic_rkey, UCT_IB_MEM_ACCESS_REMOTE_ATOMIC,
UCT_MD_FLAG_INVALIDATE_AMO, "AMO");
}
static ucs_status_t
uct_ib_mlx5_devx_dereg_keys(uct_ib_mlx5_md_t *md, uct_ib_mlx5_devx_mem_t *memh)
{
ucs_status_t status;
if (memh->atomic_dvmr != NULL) {
/* TODO atomic_dvmr should also be pushed to LRU since it can be used
to invalidate AMO or RMA with relaxed-order */
status = uct_ib_mlx5_devx_obj_destroy(memh->atomic_dvmr,
"MKEY, ATOMIC");
if (status != UCS_OK) {
return status;
}
}
if (memh->indirect_dvmr != NULL) {
uct_ib_md_mlx5_devx_mr_lru_push(md, memh->indirect_rkey, NULL);
ucs_trace("%s: destroy indirect_dvmr %p with key %x",
uct_ib_device_name(&md->super.dev), memh->indirect_dvmr,
memh->indirect_rkey);
status = uct_ib_mlx5_devx_obj_destroy(memh->indirect_dvmr,
"MKEY, INDIRECT");
if (status != UCS_OK) {
return status;
}
}
return UCS_OK;
}
static ucs_status_t uct_ib_mlx5_devx_umr_create_cq(uct_ib_mlx5_md_t *md)
{
md->umr.cq = ibv_create_cq(md->super.dev.ibv_context, 1, NULL, NULL, 0);
if (NULL == md->umr.cq) {
ucs_error("%s: ibv_create_cq() failed to create UMR CQ: %m",
uct_ib_mlx5_dev_name(md));
return UCS_ERR_IO_ERROR;
}
ucs_trace("%s: created UMR CQ %p", uct_ib_mlx5_dev_name(md), md->umr.cq);
return UCS_OK;
}
static ucs_status_t uct_ib_mlx5_devx_umr_create_qp(uct_ib_mlx5_md_t *md)
{
struct mlx5dv_qp_init_attr mlx5_qp_attr = {};
struct ibv_qp_init_attr_ex qp_attr_ex = {};
qp_attr_ex.send_cq = md->umr.cq;
qp_attr_ex.recv_cq = md->umr.cq;
qp_attr_ex.srq = NULL;
qp_attr_ex.cap.max_send_wr = 1;
qp_attr_ex.cap.max_recv_wr = 1;
qp_attr_ex.cap.max_send_sge = 1;
qp_attr_ex.cap.max_recv_sge = 1;
qp_attr_ex.cap.max_inline_data = sizeof(struct mlx5_wqe_umr_klm_seg);
qp_attr_ex.qp_type = IBV_QPT_RC;
qp_attr_ex.comp_mask = IBV_QP_INIT_ATTR_SEND_OPS_FLAGS |
IBV_QP_INIT_ATTR_PD;
qp_attr_ex.pd = md->super.pd;
qp_attr_ex.send_ops_flags = IBV_QP_EX_WITH_SEND;
mlx5_qp_attr.comp_mask = MLX5DV_QP_INIT_ATTR_MASK_SEND_OPS_FLAGS;
mlx5_qp_attr.send_ops_flags = MLX5DV_QP_EX_WITH_MR_LIST |
MLX5DV_QP_EX_WITH_MR_INTERLEAVED;
md->umr.qp = mlx5dv_create_qp(md->super.dev.ibv_context, &qp_attr_ex,
&mlx5_qp_attr);
if (NULL == md->umr.qp) {
ucs_error("%s: mlx5dv_create_qp() failed to create UMR QP: %m",
uct_ib_mlx5_dev_name(md));
return UCS_ERR_IO_ERROR;
}
ucs_trace("%s: created UMR QP QPN 0x%x", uct_ib_mlx5_dev_name(md),
md->umr.qp->qp_num);
return UCS_OK;
}
static ucs_status_t uct_ib_mlx5_devx_umr_modify_qp(uct_ib_mlx5_md_t *md)
{
uct_ib_device_t *ibdev = &md->super.dev;
struct ibv_qp_attr qp_attr = {};
uint8_t port_num;
struct ibv_port_attr *port_attr;
int attr_mask;
int ret;
port_num = ibdev->first_port;
port_attr = uct_ib_device_port_attr(ibdev, port_num);
/* Modify QP to INIT state */
attr_mask = IBV_QP_STATE |
IBV_QP_PKEY_INDEX |
IBV_QP_PORT |
IBV_QP_ACCESS_FLAGS;
qp_attr.qp_state = IBV_QPS_INIT;
qp_attr.pkey_index = 0;
qp_attr.port_num = port_num;
qp_attr.qp_access_flags = UCT_IB_MEM_ACCESS_FLAGS;
ret = ibv_modify_qp(md->umr.qp, &qp_attr, attr_mask);
if (ret) {
ucs_error("%s: ibv_modify_qp(UMR QP 0x%x) failed to modify to INIT: %m",
uct_ib_device_name(ibdev), md->umr.qp->qp_num);
return UCS_ERR_IO_ERROR;
}
/* Modify to RTR */
attr_mask = IBV_QP_STATE |
IBV_QP_DEST_QPN |
IBV_QP_PATH_MTU |
IBV_QP_RQ_PSN |
IBV_QP_MIN_RNR_TIMER |
IBV_QP_MAX_DEST_RD_ATOMIC |
IBV_QP_AV;
qp_attr.qp_state = IBV_QPS_RTR;
qp_attr.dest_qp_num = md->umr.qp->qp_num;
qp_attr.path_mtu = IBV_MTU_512;
qp_attr.rq_psn = 0;
qp_attr.min_rnr_timer = 7;
qp_attr.max_dest_rd_atomic = 1;
qp_attr.ah_attr.port_num = port_num;
qp_attr.ah_attr.dlid = port_attr->lid;
qp_attr.ah_attr.is_global = 1;
if (UCS_OK != uct_ib_device_query_gid(ibdev, port_num,
UCT_IB_DEVICE_DEFAULT_GID_INDEX,
&qp_attr.ah_attr.grh.dgid,
UCS_LOG_LEVEL_ERROR)) {
return UCS_ERR_IO_ERROR;
}