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rtl83xx-phy.c
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rtl83xx-phy.c
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// SPDX-License-Identifier: GPL-2.0-only
/* Realtek RTL838X Ethernet MDIO interface driver
*
* Copyright (C) 2020 B. Koblitz
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/phy.h>
#include <linux/netdevice.h>
#include <linux/firmware.h>
#include <linux/crc32.h>
#include <linux/sfp.h>
#include <linux/mii.h>
#include <linux/mdio.h>
#include <asm/mach-rtl838x/mach-rtl83xx.h>
#include "rtl83xx-phy.h"
extern struct rtl83xx_soc_info soc_info;
extern struct mutex smi_lock;
#define PHY_PAGE_2 2
#define PHY_PAGE_4 4
/* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
#define RTL8XXX_PAGE_SELECT 0x1f
#define RTL8XXX_PAGE_MAIN 0x0000
#define RTL821X_PAGE_PORT 0x0266
#define RTL821X_PAGE_POWER 0x0a40
#define RTL821X_PAGE_GPHY 0x0a42
#define RTL821X_PAGE_MAC 0x0a43
#define RTL821X_PAGE_STATE 0x0b80
#define RTL821X_PAGE_PATCH 0x0b82
/* Using the special page 0xfff with the MDIO controller found in
* RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
* the cache and paging engine of the MDIO controller.
*/
#define RTL83XX_PAGE_RAW 0x0fff
/* internal RTL821X PHY uses register 0x1d to select media page */
#define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
/* external RTL821X PHY uses register 0x1e to select media page */
#define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
#define RTL821X_CHIP_ID 0x6276
#define RTL821X_MEDIA_PAGE_AUTO 0
#define RTL821X_MEDIA_PAGE_COPPER 1
#define RTL821X_MEDIA_PAGE_FIBRE 3
#define RTL821X_MEDIA_PAGE_INTERNAL 8
#define RTL9300_PHY_ID_MASK 0xf0ffffff
/* RTL930X SerDes supports the following modes:
* 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
* 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
* 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
* 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
* 0x1b: 10GR1000BX_AUTO 0x1f: OFF
*/
#define RTL930X_SDS_MODE_SGMII 0x02
#define RTL930X_SDS_MODE_1000BASEX 0x04
#define RTL930X_SDS_MODE_USXGMII 0x0d
#define RTL930X_SDS_MODE_XGMII 0x10
#define RTL930X_SDS_MODE_HSGMII 0x12
#define RTL930X_SDS_MODE_2500BASEX 0x16
#define RTL930X_SDS_MODE_10GBASER 0x1a
#define RTL930X_SDS_OFF 0x1f
#define RTL930X_SDS_MASK 0x1f
/* This lock protects the state of the SoC automatically polling the PHYs over the SMI
* bus to detect e.g. link and media changes. For operations on the PHYs such as
* patching or other configuration changes such as EEE, polling needs to be disabled
* since otherwise these operations may fails or lead to unpredictable results.
*/
DEFINE_MUTEX(poll_lock);
static const struct firmware rtl838x_8380_fw;
static const struct firmware rtl838x_8214fc_fw;
static const struct firmware rtl838x_8218b_fw;
static u64 disable_polling(int port)
{
u64 saved_state;
mutex_lock(&poll_lock);
switch (soc_info.family) {
case RTL8380_FAMILY_ID:
saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
break;
case RTL8390_FAMILY_ID:
saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
saved_state <<= 32;
saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
sw_w32_mask(BIT(port % 32), 0,
RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
break;
case RTL9300_FAMILY_ID:
saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
break;
case RTL9310_FAMILY_ID:
pr_warn("%s not implemented for RTL931X\n", __func__);
break;
}
mutex_unlock(&poll_lock);
return saved_state;
}
static int resume_polling(u64 saved_state)
{
mutex_lock(&poll_lock);
switch (soc_info.family) {
case RTL8380_FAMILY_ID:
sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
break;
case RTL8390_FAMILY_ID:
sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
break;
case RTL9300_FAMILY_ID:
sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
break;
case RTL9310_FAMILY_ID:
pr_warn("%s not implemented for RTL931X\n", __func__);
break;
}
mutex_unlock(&poll_lock);
return 0;
}
static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
{
phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
}
static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
{
/* fiber ports */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
/* copper ports */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
}
static void rtl8380_phy_reset(struct phy_device *phydev)
{
phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
}
/* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
0x02A4, 0x02A4, 0x0198, 0x0198 };
u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
/* Reset the SerDes by powering it off and set a new operation mode
* of the SerDes.
*/
void rtl9300_sds_rst(int sds_num, u32 mode)
{
pr_info("%s %d\n", __func__, mode);
if (sds_num < 0 || sds_num > 11) {
pr_err("Wrong SerDes number: %d\n", sds_num);
return;
}
sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num],
RTL930X_SDS_OFF << rtl9300_sds_lsb[sds_num],
rtl9300_sds_regs[sds_num]);
mdelay(10);
sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
rtl9300_sds_regs[sds_num]);
mdelay(10);
pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
}
void rtl9300_sds_set(int sds_num, u32 mode)
{
pr_info("%s %d\n", __func__, mode);
if (sds_num < 0 || sds_num > 11) {
pr_err("Wrong SerDes number: %d\n", sds_num);
return;
}
sw_w32_mask(RTL930X_SDS_MASK << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
rtl9300_sds_regs[sds_num]);
mdelay(10);
pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
}
u32 rtl9300_sds_mode_get(int sds_num)
{
u32 v;
if (sds_num < 0 || sds_num > 11) {
pr_err("Wrong SerDes number: %d\n", sds_num);
return 0;
}
v = sw_r32(rtl9300_sds_regs[sds_num]);
v >>= rtl9300_sds_lsb[sds_num];
return v & RTL930X_SDS_MASK;
}
/* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
* a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
*/
int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
/* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
* which would otherwise read as 0.
*/
if (soc_info.id == 0x8393) {
if (phy_reg == MII_PHYSID1)
return 0x1c;
if (phy_reg == MII_PHYSID2)
return 0x8393;
}
/* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
* 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
* bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
* one 32 bit register.
*/
reg = (phy_reg << 1) & 0xfc;
val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
if (phy_reg & 1)
val = (val >> 16) & 0xffff;
else
val &= 0xffff;
return val;
}
/* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
* register which simulates commands to an internal MDIO bus.
*/
int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
{
int i;
u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
for (i = 0; i < 100; i++) {
if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
break;
mdelay(1);
}
if (i >= 100)
return -EIO;
return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
}
int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
{
int i;
u32 cmd;
sw_w32(v, RTL930X_SDS_INDACS_DATA);
cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
for (i = 0; i < 100; i++) {
if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
break;
mdelay(1);
}
if (i >= 100) {
pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
return -EIO;
}
return 0;
}
int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
{
int i;
u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
for (i = 0; i < 100; i++) {
if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
break;
mdelay(1);
}
if (i >= 100)
return -EIO;
pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
}
int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
{
int i;
u32 cmd;
cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
for (i = 0; i < 100; i++) {
if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
break;
mdelay(1);
}
if (i >= 100)
return -EIO;
return 0;
}
/* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
* standard PHY registers, where a 32 bit register holds a 16 bit word as found
* in a standard page 0 of a PHY
*/
int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
{
int offset = 0;
u32 val;
if (phy_addr == 26)
offset = 0x100;
val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
return val;
}
int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
{
int offset = 0;
int reg;
u32 val;
if (phy_addr == 49)
offset = 0x100;
reg = (phy_reg << 1) & 0xfc;
val = v;
if (phy_reg & 1) {
val = val << 16;
sw_w32_mask(0xffff0000, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
} else {
sw_w32_mask(0xffff, val,
RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
}
return 0;
}
/* Read the link and speed status of the 2 internal SGMII/1000Base-X
* ports of the RTL838x SoCs
*/
static int rtl8380_read_status(struct phy_device *phydev)
{
int err;
err = genphy_read_status(phydev);
if (phydev->link) {
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
}
return err;
}
/* Read the link and speed status of the 2 internal SGMII/1000Base-X
* ports of the RTL8393 SoC
*/
static int rtl8393_read_status(struct phy_device *phydev)
{
int offset = 0;
int err;
int phy_addr = phydev->mdio.addr;
u32 v;
err = genphy_read_status(phydev);
if (phy_addr == 49)
offset = 0x100;
if (phydev->link) {
phydev->speed = SPEED_100;
/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
* PHY registers
*/
v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
if (!(v & (1 << 13)) && (v & (1 << 6)))
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
}
return err;
}
static int rtl8226_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
}
static int rtl8226_write_page(struct phy_device *phydev, int page)
{
return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
}
static int rtl8226_read_status(struct phy_device *phydev)
{
int ret = 0;
u32 val;
/* TODO: ret = genphy_read_status(phydev);
* if (ret < 0) {
* pr_info("%s: genphy_read_status failed\n", __func__);
* return ret;
* }
*/
/* Link status must be read twice */
for (int i = 0; i < 2; i++)
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
phydev->link = val & BIT(2) ? 1 : 0;
if (!phydev->link)
goto out;
/* Read duplex status */
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
if (val < 0)
goto out;
phydev->duplex = !!(val & BIT(3));
/* Read speed */
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
switch (val & 0x0630) {
case 0x0000:
phydev->speed = SPEED_10;
break;
case 0x0010:
phydev->speed = SPEED_100;
break;
case 0x0020:
phydev->speed = SPEED_1000;
break;
case 0x0200:
phydev->speed = SPEED_10000;
break;
case 0x0210:
phydev->speed = SPEED_2500;
break;
case 0x0220:
phydev->speed = SPEED_5000;
break;
default:
break;
}
out:
return ret;
}
static int rtl8226_advertise_aneg(struct phy_device *phydev)
{
int ret = 0;
u32 v;
pr_info("In %s\n", __func__);
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
if (v < 0)
goto out;
v |= ADVERTISE_10HALF;
v |= ADVERTISE_10FULL;
v |= ADVERTISE_100HALF;
v |= ADVERTISE_100FULL;
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
/* Allow 1GBit */
v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
if (v < 0)
goto out;
v |= ADVERTISE_1000FULL;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
if (ret < 0)
goto out;
/* Allow 2.5G */
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
if (v < 0)
goto out;
v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
out:
return ret;
}
static int rtl8226_config_aneg(struct phy_device *phydev)
{
int ret = 0;
u32 v;
pr_debug("In %s\n", __func__);
if (phydev->autoneg == AUTONEG_ENABLE) {
ret = rtl8226_advertise_aneg(phydev);
if (ret)
goto out;
/* AutoNegotiationEnable */
v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
if (v < 0)
goto out;
v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
if (ret < 0)
goto out;
/* RestartAutoNegotiation */
v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
if (v < 0)
goto out;
v |= MDIO_AN_CTRL1_RESTART;
ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
}
/* TODO: ret = __genphy_config_aneg(phydev, ret); */
out:
return ret;
}
static int rtl8226_get_eee(struct phy_device *phydev,
struct ethtool_eee *e)
{
u32 val;
int addr = phydev->mdio.addr;
pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
if (e->eee_enabled) {
e->eee_enabled = !!(val & MDIO_EEE_100TX);
if (!e->eee_enabled) {
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
}
}
pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
return 0;
}
static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
{
int port = phydev->mdio.addr;
u64 poll_state;
bool an_enabled;
u32 val;
pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
poll_state = disable_polling(port);
/* Remember aneg state */
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
/* Setup 100/1000MBit */
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
if (e->eee_enabled)
val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
else
val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
/* Setup 2.5GBit */
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
if (e->eee_enabled)
val |= MDIO_EEE_2_5GT;
else
val &= MDIO_EEE_2_5GT;
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
/* RestartAutoNegotiation */
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
val |= MDIO_AN_CTRL1_RESTART;
phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
resume_polling(poll_state);
return 0;
}
static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
const struct firmware *fw,
const char *name)
{
struct device *dev = &phydev->mdio.dev;
int err;
struct fw_header *h;
uint32_t checksum, my_checksum;
err = request_firmware(&fw, name, dev);
if (err < 0)
goto out;
if (fw->size < sizeof(struct fw_header)) {
pr_err("Firmware size too small.\n");
err = -EINVAL;
goto out;
}
h = (struct fw_header *) fw->data;
pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
if (h->magic != 0x83808380) {
pr_err("Wrong firmware file: MAGIC mismatch.\n");
goto out;
}
checksum = h->checksum;
h->checksum = 0;
my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
if (checksum != my_checksum) {
pr_err("Firmware checksum mismatch.\n");
err = -EINVAL;
goto out;
}
h->checksum = checksum;
return h;
out:
dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
return NULL;
}
static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
{
int mac = phydev->mdio.addr;
/* select main page 0 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
/* write to 0x8 to register 0x1d on main page 0 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
/* select page 0x266 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
/* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
/* return to main page 0 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
/* write to 0x0 to register 0x1d on main page 0 */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
mdelay(1);
}
static int rtl8390_configure_generic(struct phy_device *phydev)
{
int mac = phydev->mdio.addr;
u32 val, phy_id;
val = phy_read(phydev, 2);
phy_id = val << 16;
val = phy_read(phydev, 3);
phy_id |= val;
pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
/* Read internal PHY ID */
phy_write_paged(phydev, 31, 27, 0x0002);
val = phy_read_paged(phydev, 31, 28);
/* Internal RTL8218B, version 2 */
phydev_info(phydev, "Detected unknown %x\n", val);
return 0;
}
static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
{
u32 val, phy_id;
int mac = phydev->mdio.addr;
struct fw_header *h;
u32 *rtl838x_6275B_intPhy_perport;
u32 *rtl8218b_6276B_hwEsd_perport;
val = phy_read(phydev, 2);
phy_id = val << 16;
val = phy_read(phydev, 3);
phy_id |= val;
pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
/* Read internal PHY ID */
phy_write_paged(phydev, 31, 27, 0x0002);
val = phy_read_paged(phydev, 31, 28);
if (val != 0x6275) {
phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
return -1;
}
/* Internal RTL8218B, version 2 */
phydev_info(phydev, "Detected internal RTL8218B\n");
h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
if (!h)
return -1;
if (h->phy != 0x83800000) {
phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
return -1;
}
rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
// Currently not used
// if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
// int ipd_flag = 1;
// }
val = phy_read(phydev, MII_BMCR);
if (val & BMCR_PDOWN)
rtl8380_int_phy_on_off(phydev, true);
else
rtl8380_phy_reset(phydev);
msleep(100);
/* Ready PHY for patch */
for (int p = 0; p < 8; p++) {
phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
}
msleep(500);
for (int p = 0; p < 8; p++) {
int i;
for (i = 0; i < 100 ; i++) {
val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
if (val & 0x40)
break;
}
if (i >= 100) {
phydev_err(phydev,
"ERROR: Port %d not ready for patch.\n",
mac + p);
return -1;
}
}
for (int p = 0; p < 8; p++) {
int i;
i = 0;
while (rtl838x_6275B_intPhy_perport[i * 2]) {
phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
rtl838x_6275B_intPhy_perport[i * 2],
rtl838x_6275B_intPhy_perport[i * 2 + 1]);
i++;
}
i = 0;
while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
rtl8218b_6276B_hwEsd_perport[i * 2],
rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
i++;
}
}
return 0;
}
static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
{
u32 val, ipd, phy_id;
int mac = phydev->mdio.addr;
struct fw_header *h;
u32 *rtl8380_rtl8218b_perchip;
u32 *rtl8218B_6276B_rtl8380_perport;
u32 *rtl8380_rtl8218b_perport;
if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
return -1;
}
val = phy_read(phydev, 2);
phy_id = val << 16;
val = phy_read(phydev, 3);
phy_id |= val;
pr_info("Phy on MAC %d: %x\n", mac, phy_id);
/* Read internal PHY ID */
phy_write_paged(phydev, 31, 27, 0x0002);
val = phy_read_paged(phydev, 31, 28);
if (val != RTL821X_CHIP_ID) {
phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
return -1;
}
phydev_info(phydev, "Detected external RTL8218B\n");
h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
if (!h)
return -1;
if (h->phy != 0x8218b000) {
phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
return -1;
}
rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
val = phy_read(phydev, MII_BMCR);
if (val & BMCR_PDOWN)
rtl8380_int_phy_on_off(phydev, true);
else
rtl8380_phy_reset(phydev);
msleep(100);
/* Get Chip revision */
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
phydev_info(phydev, "Detected chip revision %04x\n", val);
for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
rtl8380_rtl8218b_perchip[i * 3 + 2]);
}
/* Enable PHY */
for (int i = 0; i < 8; i++) {
phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
}
mdelay(100);
/* Request patch */
for (int i = 0; i < 8; i++) {
phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
}
mdelay(300);
/* Verify patch readiness */
for (int i = 0; i < 8; i++) {
int l;
for (l = 0; l < 100; l++) {
val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
if (val & 0x40)
break;
}
if (l >= 100) {
phydev_err(phydev, "Could not patch PHY\n");
return -1;
}
}
/* Use Broadcast ID method for patching */
rtl821x_phy_setup_package_broadcast(phydev, true);
phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
phy_write_paged(phydev, 0x26e, 17, 0xb);
phy_write_paged(phydev, 0x26e, 16, 0x2);
mdelay(1);
ipd = phy_read_paged(phydev, 0x26e, 19);
phy_write_paged(phydev, 0, 30, 0);
ipd = (ipd >> 4) & 0xf; /* unused ? */
for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
}
/* Disable broadcast ID */
rtl821x_phy_setup_package_broadcast(phydev, false);
return 0;
}
static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
{
int addr = phydev->mdio.addr;
/* Both the RTL8214FC and the external RTL8218B have the same
* PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
* at PHY IDs 0-7, while the RTL8214FC must be attached via
* the pair of SGMII/1000Base-X with higher PHY-IDs
*/
if (soc_info.family == RTL8380_FAMILY_ID)
return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
else
return phydev->phy_id == PHY_ID_RTL8218B_E;
}
static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
{
int mac = phydev->mdio.addr;
static int reg[] = {16, 19, 20, 21};
u32 val;
phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
if (val & BMCR_PDOWN)
return false;
return true;
}
static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
{
char *state = on ? "on" : "off";
if (port == PORT_FIBRE) {
pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
} else {
pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
}
if (on) {
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
} else {
phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
}
phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
}
static int rtl8214fc_suspend(struct phy_device *phydev)
{
rtl8214fc_power_set(phydev, PORT_MII, false);
rtl8214fc_power_set(phydev, PORT_FIBRE, false);
return 0;
}
static int rtl8214fc_resume(struct phy_device *phydev)
{
if (rtl8214fc_media_is_fibre(phydev)) {
rtl8214fc_power_set(phydev, PORT_MII, false);
rtl8214fc_power_set(phydev, PORT_FIBRE, true);
} else {
rtl8214fc_power_set(phydev, PORT_FIBRE, false);
rtl8214fc_power_set(phydev, PORT_MII, true);