"Invalid access size: 64" panic error in ARM based bare-metal FS simulation

[lczzz29]

A MiniLM pytorch model (gotten from hugging face) is compiled into LLVM IR file through the MLIR framework and into an ELF file through the arm-none-eabi gcc cross-compile toolchain. A custom linker script is offered to add some support for ARM GIC function. The body of linker script is as follows:

. = 0x00000000;

.text : {
	boot.o (INTERRUPT_VECTOR)
	*(.text)
}

.ARM.exidx : {
	__exidx_start = .;
	*(.ARM.exidx*)
	__exidx_end = .;
}
. = 0x80000000;

.data : { *(.data) }
.bss : { *(.bss COMMON) }
. = ALIGN(8);
stack_base = .;
. = . + 0x1000; /* 4kB of stack memory*/
. = . + 0x1000; /* 4kB of stack memory for IRQ*/

PROVIDE (end = .)   ;

The foremost some section headers of compiled program (main.elf) are listed:
`Section Headers:
[Nr] Name Type Addr

[ 0] NULL 00000000

[ 1] .text PROGBITS 00000000

[ 2] .rodata PROGBITS 00025cf0

[ 3] .rodata.str1.4 PROGBITS 056cca3c
`

The command options used to start the simulation are as follows (some are omitted):

./build/ARM/gem5.opt ./configs/fs_MiniLM.py --mem-size=4GB \ --mem-type=DDR4_2400_8x8 \ --kernel=./benchmarks/MiniLM/sw/main.elf \ --disk-image=./benchmarks/common/fake.iso \ --machine-type=VExpress_GEM5_V1 \ --dtb-file=none \ --bare-metal \ --cpu-type=DerivO3CPU \ --caches --l2cache

And i met the problem of invalid access size: 64 error when the initialization is executing to this point:
build/ARM/dev/isa_fake.cc:112: panic: invalid access size: 64 , packet address: 0x4040000, device: system.membus.badaddr_responder Memory Usage: 4666976 KBytes Program aborted at tick 0

I don't know why the address at which the error occured is 0x4040000, and it seems that the error doesn't appear at previous address sections as I enabled the debug flag XBar to see the output:

(the similar debug outputs in initialization of mem range [0:403ffbf] are omitted) 0: system.membus: recvFunctional: src system.membus.cpu_side_port[0] packet WriteReq [403ffc0:403ffff] 0: system.tol2bus: recvFunctionalSnoop: src system.tol2bus.mem_side_port[0] packet WriteReq [403ffc0:403ffff] 0: system.batch_matmul_kernel_cluster.coherency_bus: recvFunctionalSnoop: src system.batch_matmul_kernel_cluster.coherency_bus.mem_side_port[0] packet WriteReq [403ffc0:403ffff] 0: system.membus: recvFunctional: src system.membus.cpu_side_port[0] packet WriteReq [4040000:404003f] 0: system.tol2bus: recvFunctionalSnoop: src system.tol2bus.mem_side_port[0] packet WriteReq [4040000:404003f] 0: system.batch_matmul_kernel_cluster.coherency_bus: recvFunctionalSnoop: src system.batch_matmul_kernel_cluster.coherency_bus.mem_side_port[0] packet WriteReq [4040000:404003f] build/ARM/dev/isa_fake.cc:112: panic: invalid access size: 64 , packet address: 0x4040000, device: system.membus.badaddr_responder

the coherency bus is just a coherent xbar
coherency_bus = CoherentXBar(width=2, frontend_latency=1, forward_latency=0, response_latency=1) coherency_bus.snoop_filter = SnoopFilter() coherency_bus.snoop_response_latency = 4 coherency_bus.point_of_coherency = True coherency_bus.point_of_unification = True

Are there any considerations I ignored when compiling or running simulation? Thx if you can tell me.

[lczzz29]

I omitted the memory mapping of the platform used in configuration file, which led to this problem. After modifying the linker script to the correct mapping the error disappeared.