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We'll be running both UARTs through an FPGA proxy. I think this should be generally transparent given the FPGA will implement hardware-handshake UART interfaces there are debug things where we'd like to go back through the FPGA register interface and get more information. Unclear if we have big desires here but made for completeness and happy to discuss.
The text was updated successfully, but these errors were encountered:
We'll be running both UARTs through an FPGA proxy. I think this should be generally transparent given the FPGA will implement hardware-handshake UART interfaces there are debug things where we'd like to go back through the FPGA register interface and get more information. Unclear if we have big desires here but made for completeness and happy to discuss.
The text was updated successfully, but these errors were encountered: