forked from torvalds/linux
/
tsi721.c
2362 lines (1972 loc) · 65.8 KB
/
tsi721.c
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/*
* RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
*
* Copyright 2011 Integrated Device Technology, Inc.
* Alexandre Bounine <alexandre.bounine@idt.com>
* Chul Kim <chul.kim@idt.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/io.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/rio.h>
#include <linux/rio_drv.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/kfifo.h>
#include <linux/delay.h>
#include "tsi721.h"
#define DEBUG_PW /* Inbound Port-Write debugging */
static void tsi721_omsg_handler(struct tsi721_device *priv, int ch);
static void tsi721_imsg_handler(struct tsi721_device *priv, int ch);
/**
* tsi721_lcread - read from local SREP config space
* @mport: RapidIO master port info
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be read into
*
* Generates a local SREP space read. Returns %0 on
* success or %-EINVAL on failure.
*/
static int tsi721_lcread(struct rio_mport *mport, int index, u32 offset,
int len, u32 *data)
{
struct tsi721_device *priv = mport->priv;
if (len != sizeof(u32))
return -EINVAL; /* only 32-bit access is supported */
*data = ioread32(priv->regs + offset);
return 0;
}
/**
* tsi721_lcwrite - write into local SREP config space
* @mport: RapidIO master port info
* @index: ID of RapdiIO interface
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Value to be written
*
* Generates a local write into SREP configuration space. Returns %0 on
* success or %-EINVAL on failure.
*/
static int tsi721_lcwrite(struct rio_mport *mport, int index, u32 offset,
int len, u32 data)
{
struct tsi721_device *priv = mport->priv;
if (len != sizeof(u32))
return -EINVAL; /* only 32-bit access is supported */
iowrite32(data, priv->regs + offset);
return 0;
}
/**
* tsi721_maint_dma - Helper function to generate RapidIO maintenance
* transactions using designated Tsi721 DMA channel.
* @priv: pointer to tsi721 private data
* @sys_size: RapdiIO transport system size
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @data: Location to be read from or write into
* @do_wr: Operation flag (1 == MAINT_WR)
*
* Generates a RapidIO maintenance transaction (Read or Write).
* Returns %0 on success and %-EINVAL or %-EFAULT on failure.
*/
static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
u16 destid, u8 hopcount, u32 offset, int len,
u32 *data, int do_wr)
{
struct tsi721_dma_desc *bd_ptr;
u32 rd_count, swr_ptr, ch_stat;
int i, err = 0;
u32 op = do_wr ? MAINT_WR : MAINT_RD;
if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
return -EINVAL;
bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
rd_count = ioread32(
priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
/* Initialize DMA descriptor */
bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
bd_ptr[0].bcount = cpu_to_le32((sys_size << 26) | 0x04);
bd_ptr[0].raddr_lo = cpu_to_le32((hopcount << 24) | offset);
bd_ptr[0].raddr_hi = 0;
if (do_wr)
bd_ptr[0].data[0] = cpu_to_be32p(data);
else
bd_ptr[0].data[0] = 0xffffffff;
mb();
/* Start DMA operation */
iowrite32(rd_count + 2,
priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
i = 0;
/* Wait until DMA transfer is finished */
while ((ch_stat = ioread32(priv->regs +
TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
udelay(1);
if (++i >= 5000000) {
dev_dbg(&priv->pdev->dev,
"%s : DMA[%d] read timeout ch_status=%x\n",
__func__, TSI721_DMACH_MAINT, ch_stat);
if (!do_wr)
*data = 0xffffffff;
err = -EIO;
goto err_out;
}
}
if (ch_stat & TSI721_DMAC_STS_ABORT) {
/* If DMA operation aborted due to error,
* reinitialize DMA channel
*/
dev_dbg(&priv->pdev->dev, "%s : DMA ABORT ch_stat=%x\n",
__func__, ch_stat);
dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
iowrite32(TSI721_DMAC_INT_ALL,
priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
iowrite32(TSI721_DMAC_CTL_INIT,
priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
udelay(10);
iowrite32(0, priv->regs +
TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
udelay(1);
if (!do_wr)
*data = 0xffffffff;
err = -EIO;
goto err_out;
}
if (!do_wr)
*data = be32_to_cpu(bd_ptr[0].data[0]);
/*
* Update descriptor status FIFO RD pointer.
* NOTE: Skipping check and clear FIFO entries because we are waiting
* for transfer to be completed.
*/
swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
err_out:
return err;
}
/**
* tsi721_cread_dma - Generate a RapidIO maintenance read transaction
* using Tsi721 BDMA engine.
* @mport: RapidIO master port control structure
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @val: Location to be read into
*
* Generates a RapidIO maintenance read transaction.
* Returns %0 on success and %-EINVAL or %-EFAULT on failure.
*/
static int tsi721_cread_dma(struct rio_mport *mport, int index, u16 destid,
u8 hopcount, u32 offset, int len, u32 *data)
{
struct tsi721_device *priv = mport->priv;
return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
offset, len, data, 0);
}
/**
* tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
* using Tsi721 BDMA engine
* @mport: RapidIO master port control structure
* @index: ID of RapdiIO interface
* @destid: Destination ID of transaction
* @hopcount: Number of hops to target device
* @offset: Offset into configuration space
* @len: Length (in bytes) of the maintenance transaction
* @val: Value to be written
*
* Generates a RapidIO maintenance write transaction.
* Returns %0 on success and %-EINVAL or %-EFAULT on failure.
*/
static int tsi721_cwrite_dma(struct rio_mport *mport, int index, u16 destid,
u8 hopcount, u32 offset, int len, u32 data)
{
struct tsi721_device *priv = mport->priv;
u32 temp = data;
return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount,
offset, len, &temp, 1);
}
/**
* tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
* @mport: RapidIO master port structure
*
* Handles inbound port-write interrupts. Copies PW message from an internal
* buffer into PW message FIFO and schedules deferred routine to process
* queued messages.
*/
static int
tsi721_pw_handler(struct rio_mport *mport)
{
struct tsi721_device *priv = mport->priv;
u32 pw_stat;
u32 pw_buf[TSI721_RIO_PW_MSG_SIZE/sizeof(u32)];
pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT);
if (pw_stat & TSI721_RIO_PW_RX_STAT_PW_VAL) {
pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0));
pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1));
pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2));
pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3));
/* Queue PW message (if there is room in FIFO),
* otherwise discard it.
*/
spin_lock(&priv->pw_fifo_lock);
if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE)
kfifo_in(&priv->pw_fifo, pw_buf,
TSI721_RIO_PW_MSG_SIZE);
else
priv->pw_discard_count++;
spin_unlock(&priv->pw_fifo_lock);
}
/* Clear pending PW interrupts */
iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
priv->regs + TSI721_RIO_PW_RX_STAT);
schedule_work(&priv->pw_work);
return 0;
}
static void tsi721_pw_dpc(struct work_struct *work)
{
struct tsi721_device *priv = container_of(work, struct tsi721_device,
pw_work);
u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; /* Use full size PW message
buffer for RIO layer */
/*
* Process port-write messages
*/
while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)msg_buffer,
TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) {
/* Process one message */
#ifdef DEBUG_PW
{
u32 i;
pr_debug("%s : Port-Write Message:", __func__);
for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); ) {
pr_debug("0x%02x: %08x %08x %08x %08x", i*4,
msg_buffer[i], msg_buffer[i + 1],
msg_buffer[i + 2], msg_buffer[i + 3]);
i += 4;
}
pr_debug("\n");
}
#endif
/* Pass the port-write message to RIO core for processing */
rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
}
}
/**
* tsi721_pw_enable - enable/disable port-write interface init
* @mport: Master port implementing the port write unit
* @enable: 1=enable; 0=disable port-write message handling
*/
static int tsi721_pw_enable(struct rio_mport *mport, int enable)
{
struct tsi721_device *priv = mport->priv;
u32 rval;
rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE);
if (enable)
rval |= TSI721_RIO_EM_INT_ENABLE_PW_RX;
else
rval &= ~TSI721_RIO_EM_INT_ENABLE_PW_RX;
/* Clear pending PW interrupts */
iowrite32(TSI721_RIO_PW_RX_STAT_PW_DISC | TSI721_RIO_PW_RX_STAT_PW_VAL,
priv->regs + TSI721_RIO_PW_RX_STAT);
/* Update enable bits */
iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE);
return 0;
}
/**
* tsi721_dsend - Send a RapidIO doorbell
* @mport: RapidIO master port info
* @index: ID of RapidIO interface
* @destid: Destination ID of target device
* @data: 16-bit info field of RapidIO doorbell
*
* Sends a RapidIO doorbell message. Always returns %0.
*/
static int tsi721_dsend(struct rio_mport *mport, int index,
u16 destid, u16 data)
{
struct tsi721_device *priv = mport->priv;
u32 offset;
offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) |
(destid << 2);
dev_dbg(&priv->pdev->dev,
"Send Doorbell 0x%04x to destID 0x%x\n", data, destid);
iowrite16be(data, priv->odb_base + offset);
return 0;
}
/**
* tsi721_dbell_handler - Tsi721 doorbell interrupt handler
* @mport: RapidIO master port structure
*
* Handles inbound doorbell interrupts. Copies doorbell entry from an internal
* buffer into DB message FIFO and schedules deferred routine to process
* queued DBs.
*/
static int
tsi721_dbell_handler(struct rio_mport *mport)
{
struct tsi721_device *priv = mport->priv;
u32 regval;
/* Disable IDB interrupts */
regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
regval &= ~TSI721_SR_CHINT_IDBQRCV;
iowrite32(regval,
priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
schedule_work(&priv->idb_work);
return 0;
}
static void tsi721_db_dpc(struct work_struct *work)
{
struct tsi721_device *priv = container_of(work, struct tsi721_device,
idb_work);
struct rio_mport *mport;
struct rio_dbell *dbell;
int found = 0;
u32 wr_ptr, rd_ptr;
u64 *idb_entry;
u32 regval;
union {
u64 msg;
u8 bytes[8];
} idb;
/*
* Process queued inbound doorbells
*/
mport = priv->mport;
wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE;
rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE;
while (wr_ptr != rd_ptr) {
idb_entry = (u64 *)(priv->idb_base +
(TSI721_IDB_ENTRY_SIZE * rd_ptr));
rd_ptr++;
rd_ptr %= IDB_QSIZE;
idb.msg = *idb_entry;
*idb_entry = 0;
/* Process one doorbell */
list_for_each_entry(dbell, &mport->dbells, node) {
if ((dbell->res->start <= DBELL_INF(idb.bytes)) &&
(dbell->res->end >= DBELL_INF(idb.bytes))) {
found = 1;
break;
}
}
if (found) {
dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes),
DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
} else {
dev_dbg(&priv->pdev->dev,
"spurious inb doorbell, sid %2.2x tid %2.2x"
" info %4.4x\n", DBELL_SID(idb.bytes),
DBELL_TID(idb.bytes), DBELL_INF(idb.bytes));
}
}
iowrite32(rd_ptr & (IDB_QSIZE - 1),
priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
/* Re-enable IDB interrupts */
regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
regval |= TSI721_SR_CHINT_IDBQRCV;
iowrite32(regval,
priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
}
/**
* tsi721_irqhandler - Tsi721 interrupt handler
* @irq: Linux interrupt number
* @ptr: Pointer to interrupt-specific data (mport structure)
*
* Handles Tsi721 interrupts signaled using MSI and INTA. Checks reported
* interrupt events and calls an event-specific handler(s).
*/
static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
{
struct rio_mport *mport = (struct rio_mport *)ptr;
struct tsi721_device *priv = mport->priv;
u32 dev_int;
u32 dev_ch_int;
u32 intval;
u32 ch_inte;
dev_int = ioread32(priv->regs + TSI721_DEV_INT);
if (!dev_int)
return IRQ_NONE;
dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT);
if (dev_int & TSI721_DEV_INT_SR2PC_CH) {
/* Service SR2PC Channel interrupts */
if (dev_ch_int & TSI721_INT_SR2PC_CHAN(IDB_QUEUE)) {
/* Service Inbound Doorbell interrupt */
intval = ioread32(priv->regs +
TSI721_SR_CHINT(IDB_QUEUE));
if (intval & TSI721_SR_CHINT_IDBQRCV)
tsi721_dbell_handler(mport);
else
dev_info(&priv->pdev->dev,
"Unsupported SR_CH_INT %x\n", intval);
/* Clear interrupts */
iowrite32(intval,
priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
}
}
if (dev_int & TSI721_DEV_INT_SMSG_CH) {
int ch;
/*
* Service channel interrupts from Messaging Engine
*/
if (dev_ch_int & TSI721_INT_IMSG_CHAN_M) { /* Inbound Msg */
/* Disable signaled OB MSG Channel interrupts */
ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
ch_inte &= ~(dev_ch_int & TSI721_INT_IMSG_CHAN_M);
iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
/*
* Process Inbound Message interrupt for each MBOX
*/
for (ch = 4; ch < RIO_MAX_MBOX + 4; ch++) {
if (!(dev_ch_int & TSI721_INT_IMSG_CHAN(ch)))
continue;
tsi721_imsg_handler(priv, ch);
}
}
if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */
/* Disable signaled OB MSG Channel interrupts */
ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE);
ch_inte &= ~(dev_ch_int & TSI721_INT_OMSG_CHAN_M);
iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE);
/*
* Process Outbound Message interrupts for each MBOX
*/
for (ch = 0; ch < RIO_MAX_MBOX; ch++) {
if (!(dev_ch_int & TSI721_INT_OMSG_CHAN(ch)))
continue;
tsi721_omsg_handler(priv, ch);
}
}
}
if (dev_int & TSI721_DEV_INT_SRIO) {
/* Service SRIO MAC interrupts */
intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
if (intval & TSI721_RIO_EM_INT_STAT_PW_RX)
tsi721_pw_handler(mport);
}
return IRQ_HANDLED;
}
static void tsi721_interrupts_init(struct tsi721_device *priv)
{
u32 intr;
/* Enable IDB interrupts */
iowrite32(TSI721_SR_CHINT_ALL,
priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
iowrite32(TSI721_SR_CHINT_IDBQRCV,
priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
priv->regs + TSI721_DEV_CHAN_INTE);
/* Enable SRIO MAC interrupts */
iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
priv->regs + TSI721_RIO_EM_DEV_INT_EN);
if (priv->flags & TSI721_USING_MSIX)
intr = TSI721_DEV_INT_SRIO;
else
intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
TSI721_DEV_INT_SMSG_CH;
iowrite32(intr, priv->regs + TSI721_DEV_INTE);
ioread32(priv->regs + TSI721_DEV_INTE);
}
#ifdef CONFIG_PCI_MSI
/**
* tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
* @irq: Linux interrupt number
* @ptr: Pointer to interrupt-specific data (mport structure)
*
* Handles outbound messaging interrupts signaled using MSI-X.
*/
static irqreturn_t tsi721_omsg_msix(int irq, void *ptr)
{
struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
int mbox;
mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX;
tsi721_omsg_handler(priv, mbox);
return IRQ_HANDLED;
}
/**
* tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
* @irq: Linux interrupt number
* @ptr: Pointer to interrupt-specific data (mport structure)
*
* Handles inbound messaging interrupts signaled using MSI-X.
*/
static irqreturn_t tsi721_imsg_msix(int irq, void *ptr)
{
struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
int mbox;
mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX;
tsi721_imsg_handler(priv, mbox + 4);
return IRQ_HANDLED;
}
/**
* tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
* @irq: Linux interrupt number
* @ptr: Pointer to interrupt-specific data (mport structure)
*
* Handles Tsi721 interrupts from SRIO MAC.
*/
static irqreturn_t tsi721_srio_msix(int irq, void *ptr)
{
struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
u32 srio_int;
/* Service SRIO MAC interrupts */
srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT);
if (srio_int & TSI721_RIO_EM_INT_STAT_PW_RX)
tsi721_pw_handler((struct rio_mport *)ptr);
return IRQ_HANDLED;
}
/**
* tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
* @irq: Linux interrupt number
* @ptr: Pointer to interrupt-specific data (mport structure)
*
* Handles Tsi721 interrupts from SR2PC Channel.
* NOTE: At this moment services only one SR2PC channel associated with inbound
* doorbells.
*/
static irqreturn_t tsi721_sr2pc_ch_msix(int irq, void *ptr)
{
struct tsi721_device *priv = ((struct rio_mport *)ptr)->priv;
u32 sr_ch_int;
/* Service Inbound DB interrupt from SR2PC channel */
sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
if (sr_ch_int & TSI721_SR_CHINT_IDBQRCV)
tsi721_dbell_handler((struct rio_mport *)ptr);
/* Clear interrupts */
iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
/* Read back to ensure that interrupt was cleared */
sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
return IRQ_HANDLED;
}
/**
* tsi721_request_msix - register interrupt service for MSI-X mode.
* @mport: RapidIO master port structure
*
* Registers MSI-X interrupt service routines for interrupts that are active
* immediately after mport initialization. Messaging interrupt service routines
* should be registered during corresponding open requests.
*/
static int tsi721_request_msix(struct rio_mport *mport)
{
struct tsi721_device *priv = mport->priv;
int err = 0;
err = request_irq(priv->msix[TSI721_VECT_IDB].vector,
tsi721_sr2pc_ch_msix, 0,
priv->msix[TSI721_VECT_IDB].irq_name, (void *)mport);
if (err)
goto out;
err = request_irq(priv->msix[TSI721_VECT_PWRX].vector,
tsi721_srio_msix, 0,
priv->msix[TSI721_VECT_PWRX].irq_name, (void *)mport);
if (err)
free_irq(
priv->msix[TSI721_VECT_IDB].vector,
(void *)mport);
out:
return err;
}
/**
* tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
* @priv: pointer to tsi721 private data
*
* Configures MSI-X support for Tsi721. Supports only an exact number
* of requested vectors.
*/
static int tsi721_enable_msix(struct tsi721_device *priv)
{
struct msix_entry entries[TSI721_VECT_MAX];
int err;
int i;
entries[TSI721_VECT_IDB].entry = TSI721_MSIX_SR2PC_IDBQ_RCV(IDB_QUEUE);
entries[TSI721_VECT_PWRX].entry = TSI721_MSIX_SRIO_MAC_INT;
/*
* Initialize MSI-X entries for Messaging Engine:
* this driver supports four RIO mailboxes (inbound and outbound)
* NOTE: Inbound message MBOX 0...4 use IB channels 4...7. Therefore
* offset +4 is added to IB MBOX number.
*/
for (i = 0; i < RIO_MAX_MBOX; i++) {
entries[TSI721_VECT_IMB0_RCV + i].entry =
TSI721_MSIX_IMSG_DQ_RCV(i + 4);
entries[TSI721_VECT_IMB0_INT + i].entry =
TSI721_MSIX_IMSG_INT(i + 4);
entries[TSI721_VECT_OMB0_DONE + i].entry =
TSI721_MSIX_OMSG_DONE(i);
entries[TSI721_VECT_OMB0_INT + i].entry =
TSI721_MSIX_OMSG_INT(i);
}
err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
if (err) {
if (err > 0)
dev_info(&priv->pdev->dev,
"Only %d MSI-X vectors available, "
"not using MSI-X\n", err);
return err;
}
/*
* Copy MSI-X vector information into tsi721 private structure
*/
priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector;
snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX,
DRV_NAME "-idb@pci:%s", pci_name(priv->pdev));
priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector;
snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX,
DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev));
for (i = 0; i < RIO_MAX_MBOX; i++) {
priv->msix[TSI721_VECT_IMB0_RCV + i].vector =
entries[TSI721_VECT_IMB0_RCV + i].vector;
snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name,
IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s",
i, pci_name(priv->pdev));
priv->msix[TSI721_VECT_IMB0_INT + i].vector =
entries[TSI721_VECT_IMB0_INT + i].vector;
snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name,
IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s",
i, pci_name(priv->pdev));
priv->msix[TSI721_VECT_OMB0_DONE + i].vector =
entries[TSI721_VECT_OMB0_DONE + i].vector;
snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name,
IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s",
i, pci_name(priv->pdev));
priv->msix[TSI721_VECT_OMB0_INT + i].vector =
entries[TSI721_VECT_OMB0_INT + i].vector;
snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name,
IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s",
i, pci_name(priv->pdev));
}
return 0;
}
#endif /* CONFIG_PCI_MSI */
static int tsi721_request_irq(struct rio_mport *mport)
{
struct tsi721_device *priv = mport->priv;
int err;
#ifdef CONFIG_PCI_MSI
if (priv->flags & TSI721_USING_MSIX)
err = tsi721_request_msix(mport);
else
#endif
err = request_irq(priv->pdev->irq, tsi721_irqhandler,
(priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED,
DRV_NAME, (void *)mport);
if (err)
dev_err(&priv->pdev->dev,
"Unable to allocate interrupt, Error: %d\n", err);
return err;
}
/**
* tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
* translation regions.
* @priv: pointer to tsi721 private data
*
* Disables SREP translation regions.
*/
static void tsi721_init_pc2sr_mapping(struct tsi721_device *priv)
{
int i;
/* Disable all PC2SR translation windows */
for (i = 0; i < TSI721_OBWIN_NUM; i++)
iowrite32(0, priv->regs + TSI721_OBWINLB(i));
}
/**
* tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
* translation regions.
* @priv: pointer to tsi721 private data
*
* Disables inbound windows.
*/
static void tsi721_init_sr2pc_mapping(struct tsi721_device *priv)
{
int i;
/* Disable all SR2PC inbound windows */
for (i = 0; i < TSI721_IBWIN_NUM; i++)
iowrite32(0, priv->regs + TSI721_IBWINLB(i));
}
/**
* tsi721_port_write_init - Inbound port write interface init
* @priv: pointer to tsi721 private data
*
* Initializes inbound port write handler.
* Returns %0 on success or %-ENOMEM on failure.
*/
static int tsi721_port_write_init(struct tsi721_device *priv)
{
priv->pw_discard_count = 0;
INIT_WORK(&priv->pw_work, tsi721_pw_dpc);
spin_lock_init(&priv->pw_fifo_lock);
if (kfifo_alloc(&priv->pw_fifo,
TSI721_RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
dev_err(&priv->pdev->dev, "PW FIFO allocation failed\n");
return -ENOMEM;
}
/* Use reliable port-write capture mode */
iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL);
return 0;
}
static int tsi721_doorbell_init(struct tsi721_device *priv)
{
/* Outbound Doorbells do not require any setup.
* Tsi721 uses dedicated PCI BAR1 to generate doorbells.
* That BAR1 was mapped during the probe routine.
*/
/* Initialize Inbound Doorbell processing DPC and queue */
priv->db_discard_count = 0;
INIT_WORK(&priv->idb_work, tsi721_db_dpc);
/* Allocate buffer for inbound doorbells queue */
priv->idb_base = dma_zalloc_coherent(&priv->pdev->dev,
IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
&priv->idb_dma, GFP_KERNEL);
if (!priv->idb_base)
return -ENOMEM;
dev_dbg(&priv->pdev->dev, "Allocated IDB buffer @ %p (phys = %llx)\n",
priv->idb_base, (unsigned long long)priv->idb_dma);
iowrite32(TSI721_IDQ_SIZE_VAL(IDB_QSIZE),
priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE));
iowrite32(((u64)priv->idb_dma >> 32),
priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE));
iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR),
priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE));
/* Enable accepting all inbound doorbells */
iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE));
iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE));
iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE));
return 0;
}
static void tsi721_doorbell_free(struct tsi721_device *priv)
{
if (priv->idb_base == NULL)
return;
/* Free buffer allocated for inbound doorbell queue */
dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE,
priv->idb_base, priv->idb_dma);
priv->idb_base = NULL;
}
static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
{
struct tsi721_dma_desc *bd_ptr;
u64 *sts_ptr;
dma_addr_t bd_phys, sts_phys;
int sts_size;
int bd_num = priv->bdma[chnum].bd_num;
dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
/*
* Initialize DMA channel for maintenance requests
*/
/* Allocate space for DMA descriptors */
bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
bd_num * sizeof(struct tsi721_dma_desc),
&bd_phys, GFP_KERNEL);
if (!bd_ptr)
return -ENOMEM;
priv->bdma[chnum].bd_phys = bd_phys;
priv->bdma[chnum].bd_base = bd_ptr;
dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
bd_ptr, (unsigned long long)bd_phys);
/* Allocate space for descriptor status FIFO */
sts_size = (bd_num >= TSI721_DMA_MINSTSSZ) ?
bd_num : TSI721_DMA_MINSTSSZ;
sts_size = roundup_pow_of_two(sts_size);
sts_ptr = dma_zalloc_coherent(&priv->pdev->dev,
sts_size * sizeof(struct tsi721_dma_sts),
&sts_phys, GFP_KERNEL);
if (!sts_ptr) {
/* Free space allocated for DMA descriptors */
dma_free_coherent(&priv->pdev->dev,
bd_num * sizeof(struct tsi721_dma_desc),
bd_ptr, bd_phys);
priv->bdma[chnum].bd_base = NULL;
return -ENOMEM;
}
priv->bdma[chnum].sts_phys = sts_phys;
priv->bdma[chnum].sts_base = sts_ptr;
priv->bdma[chnum].sts_size = sts_size;
dev_dbg(&priv->pdev->dev,
"desc status FIFO @ %p (phys = %llx) size=0x%x\n",
sts_ptr, (unsigned long long)sts_phys, sts_size);
/* Initialize DMA descriptors ring */
bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29);
bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys &
TSI721_DMAC_DPTRL_MASK);
bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
/* Setup DMA descriptor pointers */
iowrite32(((u64)bd_phys >> 32),
priv->regs + TSI721_DMAC_DPTRH(chnum));
iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
priv->regs + TSI721_DMAC_DPTRL(chnum));
/* Setup descriptor status FIFO */
iowrite32(((u64)sts_phys >> 32),
priv->regs + TSI721_DMAC_DSBH(chnum));
iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
priv->regs + TSI721_DMAC_DSBL(chnum));
iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
priv->regs + TSI721_DMAC_DSSZ(chnum));
/* Clear interrupt bits */
iowrite32(TSI721_DMAC_INT_ALL,
priv->regs + TSI721_DMAC_INT(chnum));
ioread32(priv->regs + TSI721_DMAC_INT(chnum));
/* Toggle DMA channel initialization */
iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
udelay(10);
return 0;
}
static int tsi721_bdma_ch_free(struct tsi721_device *priv, int chnum)
{
u32 ch_stat;
if (priv->bdma[chnum].bd_base == NULL)
return 0;
/* Check if DMA channel still running */
ch_stat = ioread32(priv->regs + TSI721_DMAC_STS(chnum));
if (ch_stat & TSI721_DMAC_STS_RUN)
return -EFAULT;
/* Put DMA channel into init state */
iowrite32(TSI721_DMAC_CTL_INIT,
priv->regs + TSI721_DMAC_CTL(chnum));
/* Free space allocated for DMA descriptors */
dma_free_coherent(&priv->pdev->dev,
priv->bdma[chnum].bd_num * sizeof(struct tsi721_dma_desc),
priv->bdma[chnum].bd_base, priv->bdma[chnum].bd_phys);
priv->bdma[chnum].bd_base = NULL;
/* Free space allocated for status FIFO */
dma_free_coherent(&priv->pdev->dev,
priv->bdma[chnum].sts_size * sizeof(struct tsi721_dma_sts),