forked from analogdevicesinc/linux
/
zynq-parallella1.dtsi
285 lines (261 loc) · 7.51 KB
/
zynq-parallella1.dtsi
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
/include/ "zynq-common.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Parallella Gen1";
aliases {
ethernet0 = ð
serial0 = &uart;
};
amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
gic: intc@f8f01000 {
interrupt-controller;
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
reg = <0xf8f01000 0x1000>,
<0xf8f00100 0x0100>;
};
pl310@f8f02000 {
compatible = "arm,pl310-cache";
cache-unified;
cache-level = <2>;
reg = <0xf8f02000 0x1000>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
};
/* UART-->MIO 8:9 */
uart: uart@e0001000 {
compatible = "xlnx,xuartps";
reg = <0xe0001000 0x1000>;
interrupts = < 0 50 4>;
interrupt-parent = <&gic>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 24>, <&clkc 41>;
port-number = <0>;
current-speed = <115200>;
device_type = "serial";
};
ps7_dma: ps7-dma@f8003000 {
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <4>;
compatible = "arm,primecell", "arm,pl330";
interrupt-parent = <&gic>;
interrupts = <0 13 4 0 14 4 0 15 4 0 16 4 0 17 4 0 40 4 0 41 4 0 42 4 0 43 4>;
reg = <0xf8003000 0x1000>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
slcr: slcr@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon";
reg = <0xf8000000 0x1000>;
ranges ;
clkc: clkc {
#clock-cells = <1>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0xf>;
reg = <0x100 0x100>;
};
};
timer@0xf8001000 {
compatible = "cdns,ttc";
reg = <0xf8001000 0x1000>;
interrupt-names = "ttc0", "ttc1", "ttc2";
interrupts = < 0 10 4 0 11 4 0 12 4 >;
interrupt-parent = <&gic>;
clocks = <&clkc 6>;
};
timer@f8f00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
interrupts = <1 13 0x301>;
clocks = <&clkc 4>;
interrupt-parent = <&gic>;
};
swdt@f8005000 {
device_type = "watchdog";
compatible = "xlnx,ps7-wdt-1.00.a", "xlnx,zynq-wdt-1.00.a";
reg = <0xf8005000 0x100>;
interrupts = <0 9 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 45>;
reset = <0>;
timeout = <10>;
};
scuwdt@f8f00620 {
device_type = "watchdog";
compatible = "arm,mpcore_wdt";
reg = <0xf8f00620 0x20>;
clocks = <&clkc 4>;
reset = <1>;
};
/* ETHERNET0-->MIO 17:27 & MIO 52:53 */
eth: eth@e000b000 {
compatible = "xlnx,ps7-ethernet-1.00.a";
reg = <0xe000b000 0x1000>;
interrupts = <0 22 4>;
interrupt-parent = <&gic>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 13>, <&clkc 30>;
xlnx,enet-clk-freq-hz = <0x17d7840>;
xlnx,enet-reset = "MIO 11";
xlnx,enet-slcr-1000mbps-div0 = <0x8>;
xlnx,enet-slcr-1000mbps-div1 = <0x1>;
xlnx,enet-slcr-100mbps-div0 = <0x8>;
xlnx,enet-slcr-100mbps-div1 = <0x5>;
xlnx,enet-slcr-10mbps-div0 = <0x8>;
xlnx,enet-slcr-10mbps-div1 = <0x32>;
xlnx,eth-mode = <0x1>;
xlnx,has-mdio = <0x1>;
xlnx,ptp-enet-clock = <0x69f6bcb>;
phy-handle = <0x3>;
phy-mode = "rgmii-id";
phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0x0>;
marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>;
linux,phandle = <0x3>;
phandle = <0x3>;
};
};
gpio: gpio@e000a000 {
compatible = "xlnx,ps7-gpio-1.00.a", "xlnx,zynq-gpio-1.00.a", "xlnx,zynq-gpio-1.0";
reg = <0xe000a000 0x1000>;
interrupts = <0 20 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 42>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* MICRO-SD (SD1)-->MIO 10:15 */
sdhci@e0101000 {
compatible = "xlnx,ps7-sdio-1.00.a", "arasan,sdhci-8.9a";
reg = <0xe0101000 0x1000>;
interrupts = <0x0 0x2f 0x0>;
interrupt-parent = <&gic>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 22>, <&clkc 33>;
xlnx,has-cd = <0x0>;
clock-frequency = <50000000>;
};
/* USB0(HOST)-->MIO 28:39 */
usb: usb@e0002000 {
compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a";
reg = <0xe0002000 0x1000>;
interrupts = <0 21 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 28>;
dr_mode = "host";
phy_type = "ulpi";
};
/* BOOT-FLASH-->MIO 1:6 */
qspi0: qspi@e000d000 {
#address-cells = <1>;
#size-cells = <0>;
bus-num = <0>;
compatible = "xlnx,zynq-qspi-1.00.a", "xlnx,ps7-qspi-1.00.a";
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 10>, <&clkc 43>;
is-dual = <0>;
num-chip-select = <1>;
reg = <0xe000d000 0x1000>;
xlnx,fb-clk = <0x1>;
xlnx,qspi-clk-freq-hz = <0xbebc200>;
xlnx,qspi-mode = <0x0>;
primary_flash: ps7-qspi@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
reg = <0x0>;
spi-max-frequency = <50000000>;
partition@0x00000000 {
label = "boot";
reg = <0x00000000 0x00500000>;
};
partition@0x00500000 {
label = "bootenv";
reg = <0x00500000 0x00020000>;
};
partition@0x00520000 {
label = "config";
reg = <0x00520000 0x00020000>;
};
partition@0x00540000 {
label = "image";
reg = <0x00540000 0x00a80000>;
};
partition@0x00fc0000 {
label = "spare";
reg = <0x00fc0000 0x00000000>;
};
};
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupts = <0 8 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
};
xadc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a", "xlnx,ps7-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 12>;
};
ps7_ddrc_0: ps7-ddrc@f8006000 {
compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc", "xlnx,zynq-ddrc-1.00.a";
reg = <0xf8006000 0x1000>;
xlnx,has-ecc = <0x0>;
};
ps7_ocm_0: ps7-ocm@0xfffc0000 {
compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocm-1.0";
interrupt-parent = <&gic>;
interrupts = <0 3 4>;
reg = <0xfffc0000 0x40000>;
};
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
reg = <0xe0004000 0x1000>;
interrupts = <0 25 4>;
interrupt-parent = <&gic>;
bus-id = <0x0>;
clocks = <&clkc 38>;
clock-frequency = <100000>;
#address-cells = <0x1>;
#size-cells = <0x0>;
adv7511: adv7511@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-style = <0x2>;
adi,input-id = <0x1>;
adi,input-color-depth = <0x0>;
adi,sync-pulse = <0x3>;
adi,bit-justification = <0x0>;
adi,up-conversion = <0x0>;
adi,timing-generation-sequence = <0x0>;
adi,vsync-polarity = <0x2>;
adi,hsync-polarity = <0x2>;
adi,tdms-clock-inversion;
adi,clock-delay = <0x3>;
};
};
};
};