Wiki page for coding style

[UlisesLuzius]

Given the arrival of new developers to the Team, we need a way to maintain consistency through the code different team members are working on in parallel

Currently there's no convention regarding what style should be used for naming

Chisel being somewhat of a mixture of RTL and Scala has two naming conventions that conflict each other, and special specifications related to the code generation part of Chisel.

1. In the Java/Scala world, people tend to follow the naming convention of writing variables like fooBar
2. In the RTL world, people tend to follow c-like naming things like foo_bar
3. Verilog (and VHDL) being constrained by physical requirements, developers make use of suffixes to hint what kind
   of hardware element is behind a name with _i,_o,_r corresponding to IO ports, and Register
4. Chisel generated code tends to add a _ on every Scala attribute, module port name. such as

val myBun = new Bundle {
   val a = UInt
   val b = new Bundle { 
        val c = Bool
        val d = Bool 
   }
}

will generate

myBun_a
myBun_b_c
myBun_b_d

Taking the best from both worlds, we should keep the good hits hardware developers use to ease readability while taking into consideration the heritage of Scala and the Chisel code generation

[UlisesLuzius]

See Wiki Page PARSA Chisel Coding Style.