Intel MAX 10 Ethernet Packet Generator

University of Limerick Electronic and Computer Engineering Final Year Project
Author: Patrick Corley
Supervisor: Dr. Richard Conway

Gigabit network packet generator implemented on an Intel MAX 10 FPGA

This project uses Verilog modules written by Alex Forencich under the Verilog-Ethernet project found at https://github.com/alexforencich/verilog-ethernet