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SpinalHDL basics
An "sbt" based installation is easy to get started with, unless you prefer using IDE's!
Check out this link.
Clone the getting started repo.
Remove the two .scala files in the src/main/scala/mylib folder and replace it with Hello.scala as shown below:
package mylib
import spinal.core._
import spinal.lib._
class Hello extends Component {
val io = new Bundle {
val pinA = in Bool
val pinB = out Bool
}
io.pinB := io.pinA
}
object HelloVerilog {
def main(args: Array[String]) {
SpinalVerilog(new Hello)
}
}
Run the code with "sbt run" (at the top level of the repo); we will get a Verilog file Hello.v:
module Hello (
input io_pinA,
output io_pinB);
assign io_pinB = io_pinA;
endmodule
Some of the interesting points:
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The scala code uses some small tricks to make the code look like a DSL (I am wondering why they decided to do it this way) - like say writing "8 bits" instead of "8.bits", "in Bool" instead of "in.Bool".
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The "component" defines a Verilog module and the bundle defines its interface (i/o pins).
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The "io" bundle (looks like it must be named as "io" itself) defines the external interfaces of the verilog module.
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"Bundle" is a class; I was initially surprised by how we can instantiate a class with arbitrary members stored in it ... but it looks like Scala supports structural typing and that may be how it is done.
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Don't confuse := with assignment; it is a function which is dressed up to look like an operator.