Memory-Map.md

@@ -79,18 +79,23 @@ Most of them live in 60000000h.
 |    60000100h | 100h | spi1  | *Unconfirmed:* The SPI controller registers, see examples/IoT_Demo/include/driver/spi_register.h
 |    60000200h | 100h | spi0  | *Unconfirmed:* The SPI controller registers, see examples/IoT_Demo/include/driver/spi_register.h
 |    60000300h |  74h | gpio  | *Unconfirmed:* The timer config registers, see `include/eagle_soc.h`
+|    60000500h | >=E4h| ?     | Referenced by rom_iq_est_disable/rom_iq_est_enable/rom_dc_iq_est/rom_get_corr_power/rom_start_tx_tone/rom_pbus_force_test
 |    60000600h |  28h | timer | *Unconfirmed:* The timer config registers, see `include/eagle_soc.h`
-|    60000700h |  A4h | rtc   | *Unconfirmed:* The RTC config registers, see `include/eagle_soc.h`
+|    60000700h |  A4h | rtc   | *Unconfirmed:* The RTC config registers, see `include/eagle_soc.h` + reset control
 |    60000800h |  44h | iomux | The IO MUX config registers, see `include/eagle_soc.h`
+|    60000B00h | >=10h| slc   | Referenced by slc_enable, IRQ 1,
 |    60000d00h | >=8  | i2c   | *Unconfirmed:* Internal I2C controller registers, see ROM functions rom_i2c_readReg, rom_i2c_writeReg
+|    60000D00h | >=5Ch| sar   | Referenced by rom_en_pwdet/rom_get_fm_sar_dout/readvdd33
 |    60000F00h |  80h | uart1 | The UART1 config registers, see `examples/IoT_Demo/include/drivers/uart_register.h`
 |    60001000h | 100h | rtcb  | RTC backup memory, see `rtc_mem_backup`
 |    60001100h | 100h | rtcs  | RTC system memory, see `system_rtc_mem_write`
 |    60001200h | 200h | rtcu  | RTC user memory
+|    60009A00h |>=324h| ?     | Referenced by rom_get_noisefloor, rom_chip_v5_sense_backoff
 
 ### dport0 (3FF00000h–)
 
 * 3FF00014h is a clock setting register. Setting bit 0 changes the CPU to 160 MHz mode. Clearing it means 80 MHz. Note that you need to call `os_update_cpu_frequency(int freq_in_mhz)` when changing the bit. Probably to calibrate timers. The UART divisor is not updated automatically, so you also have to call `uart_div_modify(uart_no, clock_freq_in_hz / baud_rate_in_baud)`.
+* 3FF20A00h (>=3e0) referenced by rom_tx_mac_disable/rom_tx_mac_enable
 
 ### iomux Pin Registers (60000804h–60000843h)