/
ar9300_ani.c
1304 lines (1178 loc) · 47.3 KB
/
ar9300_ani.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
* INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
* LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "opt_ah.h"
#include "ah.h"
#include "ah_internal.h"
#include "ah_desc.h"
//#include "ah_pktlog.h"
#include "ar9300/ar9300.h"
#include "ar9300/ar9300reg.h"
#include "ar9300/ar9300phy.h"
extern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits);
extern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah);
#define HAL_ANI_DEBUG 1
/*
* Anti noise immunity support. We track phy errors and react
* to excessive errors by adjusting the noise immunity parameters.
*/
/******************************************************************************
*
* New Ani Algorithm for Station side only
*
*****************************************************************************/
#define HAL_ANI_OFDM_TRIG_HIGH 1000 /* units are errors per second */
#define HAL_ANI_OFDM_TRIG_LOW 400 /* units are errors per second */
#define HAL_ANI_CCK_TRIG_HIGH 600 /* units are errors per second */
#define HAL_ANI_CCK_TRIG_LOW 300 /* units are errors per second */
#define HAL_ANI_USE_OFDM_WEAK_SIG AH_TRUE
#define HAL_ANI_ENABLE_MRC_CCK AH_TRUE /* default is enabled */
#define HAL_ANI_DEF_SPUR_IMMUNE_LVL 3
#define HAL_ANI_DEF_FIRSTEP_LVL 2
#define HAL_ANI_RSSI_THR_HIGH 40
#define HAL_ANI_RSSI_THR_LOW 7
#define HAL_ANI_PERIOD 1000
#define HAL_NOISE_DETECT_PERIOD 100
#define HAL_NOISE_RECOVER_PERIOD 5000
#define HAL_SIG_FIRSTEP_SETTING_MIN 0
#define HAL_SIG_FIRSTEP_SETTING_MAX 20
#define HAL_SIG_SPUR_IMM_SETTING_MIN 0
#define HAL_SIG_SPUR_IMM_SETTING_MAX 22
#define HAL_EP_RND(x, mul) \
((((x) % (mul)) >= ((mul) / 2)) ? ((x) + ((mul) - 1)) / (mul) : (x) / (mul))
#define BEACON_RSSI(ahp) \
HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
HAL_RSSI_EP_MULTIPLIER)
typedef int TABLE[];
/*
* level: 0 1 2 3 4 5 6 7 8
* firstep_table: lvl 0-8, default 2
*/
static const TABLE firstep_table = { -4, -2, 0, 2, 4, 6, 8, 10, 12};
/* cycpwr_thr1_table: lvl 0-7, default 3 */
static const TABLE cycpwr_thr1_table = { -6, -4, -2, 0, 2, 4, 6, 8 };
/* values here are relative to the INI */
typedef struct _HAL_ANI_OFDM_LEVEL_ENTRY {
int spur_immunity_level;
int fir_step_level;
int ofdm_weak_signal_on;
} HAL_ANI_OFDM_LEVEL_ENTRY;
static const HAL_ANI_OFDM_LEVEL_ENTRY ofdm_level_table[] = {
/* SI FS WS */
{ 0, 0, 1 }, /* lvl 0 */
{ 1, 1, 1 }, /* lvl 1 */
{ 2, 2, 1 }, /* lvl 2 */
{ 3, 2, 1 }, /* lvl 3 (default) */
{ 4, 3, 1 }, /* lvl 4 */
{ 5, 4, 1 }, /* lvl 5 */
{ 6, 5, 1 }, /* lvl 6 */
{ 7, 6, 1 }, /* lvl 7 */
{ 7, 7, 1 }, /* lvl 8 */
{ 7, 8, 0 } /* lvl 9 */
};
#define HAL_ANI_OFDM_NUM_LEVEL \
(sizeof(ofdm_level_table) / sizeof(ofdm_level_table[0]))
#define HAL_ANI_OFDM_MAX_LEVEL (HAL_ANI_OFDM_NUM_LEVEL - 1)
#define HAL_ANI_OFDM_DEF_LEVEL 3 /* default level - matches the INI settings */
typedef struct _HAL_ANI_CCK_LEVEL_ENTRY {
int fir_step_level;
int mrc_cck_on;
} HAL_ANI_CCK_LEVEL_ENTRY;
static const HAL_ANI_CCK_LEVEL_ENTRY cck_level_table[] = {
/* FS MRC-CCK */
{ 0, 1 }, /* lvl 0 */
{ 1, 1 }, /* lvl 1 */
{ 2, 1 }, /* lvl 2 (default) */
{ 3, 1 }, /* lvl 3 */
{ 4, 0 }, /* lvl 4 */
{ 5, 0 }, /* lvl 5 */
{ 6, 0 }, /* lvl 6 */
{ 7, 0 }, /* lvl 7 (only for high rssi) */
{ 8, 0 } /* lvl 8 (only for high rssi) */
};
#define HAL_ANI_CCK_NUM_LEVEL \
(sizeof(cck_level_table) / sizeof(cck_level_table[0]))
#define HAL_ANI_CCK_MAX_LEVEL (HAL_ANI_CCK_NUM_LEVEL - 1)
#define HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI (HAL_ANI_CCK_NUM_LEVEL - 3)
#define HAL_ANI_CCK_DEF_LEVEL 2 /* default level - matches the INI settings */
/*
* register values to turn OFDM weak signal detection OFF
*/
static const int m1_thresh_low_off = 127;
static const int m2_thresh_low_off = 127;
static const int m1_thresh_off = 127;
static const int m2_thresh_off = 127;
static const int m2_count_thr_off = 31;
static const int m2_count_thr_low_off = 63;
static const int m1_thresh_low_ext_off = 127;
static const int m2_thresh_low_ext_off = 127;
static const int m1_thresh_ext_off = 127;
static const int m2_thresh_ext_off = 127;
void
ar9300_enable_mib_counters(struct ath_hal *ah)
{
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Enable MIB counters\n", __func__);
/* Clear the mib counters and save them in the stats */
ar9300_update_mib_mac_stats(ah);
OS_REG_WRITE(ah, AR_FILT_OFDM, 0);
OS_REG_WRITE(ah, AR_FILT_CCK, 0);
OS_REG_WRITE(ah, AR_MIBC,
~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
}
void
ar9300_disable_mib_counters(struct ath_hal *ah)
{
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Disabling MIB counters\n", __func__);
OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
/* Clear the mib counters and save them in the stats */
ar9300_update_mib_mac_stats(ah);
OS_REG_WRITE(ah, AR_FILT_OFDM, 0);
OS_REG_WRITE(ah, AR_FILT_CCK, 0);
}
/*
* This routine returns the index into the ani_state array that
* corresponds to the channel in *chan. If no match is found and the
* array is still not fully utilized, a new entry is created for the
* channel. We assume the attach function has already initialized the
* ah_ani values and only the channel field needs to be set.
*/
static int
ar9300_get_ani_channel_index(struct ath_hal *ah,
const struct ieee80211_channel *chan)
{
struct ath_hal_9300 *ahp = AH9300(ah);
int i;
for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) {
/* XXX this doesn't distinguish between 20/40 channels */
if (ahp->ah_ani[i].c.ic_freq == chan->ic_freq) {
return i;
}
if (ahp->ah_ani[i].c.ic_freq == 0) {
ahp->ah_ani[i].c.ic_freq = chan->ic_freq;
ahp->ah_ani[i].c.ic_flags = chan->ic_flags;
return i;
}
}
/* XXX statistic */
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: No more channel states left. Using channel 0\n", __func__);
return 0; /* XXX gotta return something valid */
}
/*
* Return the current ANI state of the channel we're on
*/
struct ar9300_ani_state *
ar9300_ani_get_current_state(struct ath_hal *ah)
{
return AH9300(ah)->ah_curani;
}
/*
* Return the current statistics.
*/
HAL_ANI_STATS *
ar9300_ani_get_current_stats(struct ath_hal *ah)
{
return &AH9300(ah)->ah_stats;
}
/*
* Setup ANI handling. Sets all thresholds and levels to default level AND
* resets the channel statistics
*/
void
ar9300_ani_attach(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
int i;
OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
for (i = 0; i < ARRAY_LENGTH(ahp->ah_ani); i++) {
ahp->ah_ani[i].ofdm_trig_high = HAL_ANI_OFDM_TRIG_HIGH;
ahp->ah_ani[i].ofdm_trig_low = HAL_ANI_OFDM_TRIG_LOW;
ahp->ah_ani[i].cck_trig_high = HAL_ANI_CCK_TRIG_HIGH;
ahp->ah_ani[i].cck_trig_low = HAL_ANI_CCK_TRIG_LOW;
ahp->ah_ani[i].rssi_thr_high = HAL_ANI_RSSI_THR_HIGH;
ahp->ah_ani[i].rssi_thr_low = HAL_ANI_RSSI_THR_LOW;
ahp->ah_ani[i].ofdm_noise_immunity_level = HAL_ANI_OFDM_DEF_LEVEL;
ahp->ah_ani[i].cck_noise_immunity_level = HAL_ANI_CCK_DEF_LEVEL;
ahp->ah_ani[i].ofdm_weak_sig_detect_off = !HAL_ANI_USE_OFDM_WEAK_SIG;
ahp->ah_ani[i].spur_immunity_level = HAL_ANI_DEF_SPUR_IMMUNE_LVL;
ahp->ah_ani[i].firstep_level = HAL_ANI_DEF_FIRSTEP_LVL;
ahp->ah_ani[i].mrc_cck_off = !HAL_ANI_ENABLE_MRC_CCK;
ahp->ah_ani[i].ofdms_turn = AH_TRUE;
ahp->ah_ani[i].must_restore = AH_FALSE;
}
/*
* Since we expect some ongoing maintenance on the tables,
* let's sanity check here.
* The default level should not modify INI setting.
*/
HALASSERT(firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] == 0);
HALASSERT(cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] == 0);
HALASSERT(
ofdm_level_table[HAL_ANI_OFDM_DEF_LEVEL].fir_step_level ==
HAL_ANI_DEF_FIRSTEP_LVL);
HALASSERT(
ofdm_level_table[HAL_ANI_OFDM_DEF_LEVEL].spur_immunity_level ==
HAL_ANI_DEF_SPUR_IMMUNE_LVL);
HALASSERT(
cck_level_table[HAL_ANI_CCK_DEF_LEVEL].fir_step_level ==
HAL_ANI_DEF_FIRSTEP_LVL);
/* Initialize and enable MIB Counters */
OS_REG_WRITE(ah, AR_PHY_ERR_1, 0);
OS_REG_WRITE(ah, AR_PHY_ERR_2, 0);
ar9300_enable_mib_counters(ah);
ahp->ah_ani_period = HAL_ANI_PERIOD;
if (ah->ah_config.ath_hal_enable_ani) {
ahp->ah_proc_phy_err |= HAL_PROCESS_ANI;
}
}
/*
* Cleanup any ANI state setup.
*/
void
ar9300_ani_detach(struct ath_hal *ah)
{
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Detaching Ani\n", __func__);
ar9300_disable_mib_counters(ah);
OS_REG_WRITE(ah, AR_PHY_ERR_1, 0);
OS_REG_WRITE(ah, AR_PHY_ERR_2, 0);
}
/*
* Initialize the ANI register values with default (ini) values.
* This routine is called during a (full) hardware reset after
* all the registers are initialised from the INI.
*/
void
ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int index;
u_int32_t val;
HALASSERT(chan != AH_NULL);
index = ar9300_get_ani_channel_index(ah, chan);
ani_state = &ahp->ah_ani[index];
ahp->ah_curani = ani_state;
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ver %d.%d opmode %u chan %d Mhz/0x%x macmode %d\n",
__func__, AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev,
AH_PRIVATE(ah)->ah_opmode, chan->ic_freq, chan->ic_flags, macmode);
val = OS_REG_READ(ah, AR_PHY_SFCORR);
ani_state->ini_def.m1_thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
ani_state->ini_def.m2_thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
ani_state->ini_def.m2_count_thr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
val = OS_REG_READ(ah, AR_PHY_SFCORR_LOW);
ani_state->ini_def.m1_thresh_low =
MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
ani_state->ini_def.m2_thresh_low =
MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
ani_state->ini_def.m2_count_thr_low =
MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
val = OS_REG_READ(ah, AR_PHY_SFCORR_EXT);
ani_state->ini_def.m1_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
ani_state->ini_def.m2_thresh_ext = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
ani_state->ini_def.m1_thresh_low_ext =
MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
ani_state->ini_def.m2_thresh_low_ext =
MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
ani_state->ini_def.firstep =
OS_REG_READ_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP);
ani_state->ini_def.firstep_low =
OS_REG_READ_FIELD(
ah, AR_PHY_FIND_SIG_LOW, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
ani_state->ini_def.cycpwr_thr1 =
OS_REG_READ_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1);
ani_state->ini_def.cycpwr_thr1_ext =
OS_REG_READ_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1);
/* these levels just got reset to defaults by the INI */
ani_state->spur_immunity_level = HAL_ANI_DEF_SPUR_IMMUNE_LVL;
ani_state->firstep_level = HAL_ANI_DEF_FIRSTEP_LVL;
ani_state->ofdm_weak_sig_detect_off = !HAL_ANI_USE_OFDM_WEAK_SIG;
ani_state->mrc_cck_off = !HAL_ANI_ENABLE_MRC_CCK;
ani_state->cycle_count = 0;
}
/*
* Set the ANI settings to match an OFDM level.
*/
static void
ar9300_ani_set_odfm_noise_immunity_level(struct ath_hal *ah,
u_int8_t ofdm_noise_immunity_level)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state = ahp->ah_curani;
ani_state->rssi = BEACON_RSSI(ahp);
HALDEBUG(ah, HAL_DEBUG_ANI,
"**** %s: ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", __func__,
ani_state->ofdm_noise_immunity_level, ofdm_noise_immunity_level,
ani_state->rssi, ani_state->rssi_thr_low, ani_state->rssi_thr_high);
ani_state->ofdm_noise_immunity_level = ofdm_noise_immunity_level;
if (ani_state->spur_immunity_level !=
ofdm_level_table[ofdm_noise_immunity_level].spur_immunity_level)
{
ar9300_ani_control(
ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
ofdm_level_table[ofdm_noise_immunity_level].spur_immunity_level);
}
if (ani_state->firstep_level !=
ofdm_level_table[ofdm_noise_immunity_level].fir_step_level &&
ofdm_level_table[ofdm_noise_immunity_level].fir_step_level >=
cck_level_table[ani_state->cck_noise_immunity_level].fir_step_level)
{
ar9300_ani_control(
ah, HAL_ANI_FIRSTEP_LEVEL,
ofdm_level_table[ofdm_noise_immunity_level].fir_step_level);
}
if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA ||
ani_state->rssi <= ani_state->rssi_thr_high))
{
if (ani_state->ofdm_weak_sig_detect_off) {
/*
* force on ofdm weak sig detect.
*/
ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, AH_TRUE);
}
} else if (ani_state->ofdm_weak_sig_detect_off ==
ofdm_level_table[ofdm_noise_immunity_level].ofdm_weak_signal_on)
{
ar9300_ani_control(
ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
ofdm_level_table[ofdm_noise_immunity_level].ofdm_weak_signal_on);
}
}
/*
* Set the ANI settings to match a CCK level.
*/
static void
ar9300_ani_set_cck_noise_immunity_level(struct ath_hal *ah,
u_int8_t cck_noise_immunity_level)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state = ahp->ah_curani;
int level;
ani_state->rssi = BEACON_RSSI(ahp);
HALDEBUG(ah, HAL_DEBUG_ANI,
"**** %s: ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
__func__, ani_state->cck_noise_immunity_level, cck_noise_immunity_level,
ani_state->rssi, ani_state->rssi_thr_low, ani_state->rssi_thr_high);
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA &&
ani_state->rssi <= ani_state->rssi_thr_low &&
cck_noise_immunity_level > HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI)
{
cck_noise_immunity_level = HAL_ANI_CCK_MAX_LEVEL_LOW_RSSI;
}
ani_state->cck_noise_immunity_level = cck_noise_immunity_level;
level = ani_state->ofdm_noise_immunity_level;
if (ani_state->firstep_level !=
cck_level_table[cck_noise_immunity_level].fir_step_level &&
cck_level_table[cck_noise_immunity_level].fir_step_level >=
ofdm_level_table[level].fir_step_level)
{
ar9300_ani_control(
ah, HAL_ANI_FIRSTEP_LEVEL,
cck_level_table[cck_noise_immunity_level].fir_step_level);
}
if (ani_state->mrc_cck_off ==
cck_level_table[cck_noise_immunity_level].mrc_cck_on)
{
ar9300_ani_control(
ah, HAL_ANI_MRC_CCK,
cck_level_table[cck_noise_immunity_level].mrc_cck_on);
}
}
/*
* Control Adaptive Noise Immunity Parameters
*/
HAL_BOOL
ar9300_ani_control(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state = ahp->ah_curani;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
int32_t value, value2;
u_int level = param;
u_int is_on;
if (chan == NULL && cmd != HAL_ANI_MODE) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: ignoring cmd 0x%02x - no channel\n", __func__, cmd);
return AH_FALSE;
}
switch (cmd & ahp->ah_ani_function) {
case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:
{
int m1_thresh_low, m2_thresh_low;
int m1_thresh, m2_thresh;
int m2_count_thr, m2_count_thr_low;
int m1_thresh_low_ext, m2_thresh_low_ext;
int m1_thresh_ext, m2_thresh_ext;
/*
* is_on == 1 means ofdm weak signal detection is ON
* (default, less noise imm)
* is_on == 0 means ofdm weak signal detection is OFF
* (more noise imm)
*/
is_on = param ? 1 : 0;
if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah))
goto skip_ws_det;
/*
* make register setting for default (weak sig detect ON)
* come from INI file
*/
m1_thresh_low = is_on ?
ani_state->ini_def.m1_thresh_low : m1_thresh_low_off;
m2_thresh_low = is_on ?
ani_state->ini_def.m2_thresh_low : m2_thresh_low_off;
m1_thresh = is_on ?
ani_state->ini_def.m1_thresh : m1_thresh_off;
m2_thresh = is_on ?
ani_state->ini_def.m2_thresh : m2_thresh_off;
m2_count_thr = is_on ?
ani_state->ini_def.m2_count_thr : m2_count_thr_off;
m2_count_thr_low = is_on ?
ani_state->ini_def.m2_count_thr_low : m2_count_thr_low_off;
m1_thresh_low_ext = is_on ?
ani_state->ini_def.m1_thresh_low_ext : m1_thresh_low_ext_off;
m2_thresh_low_ext = is_on ?
ani_state->ini_def.m2_thresh_low_ext : m2_thresh_low_ext_off;
m1_thresh_ext = is_on ?
ani_state->ini_def.m1_thresh_ext : m1_thresh_ext_off;
m2_thresh_ext = is_on ?
ani_state->ini_def.m2_thresh_ext : m2_thresh_ext_off;
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M1_THRESH,
m1_thresh);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2_THRESH,
m2_thresh);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR, AR_PHY_SFCORR_M2COUNT_THR,
m2_count_thr);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M1_THRESH,
m1_thresh_ext);
OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, AR_PHY_SFCORR_EXT_M2_THRESH,
m2_thresh_ext);
skip_ws_det:
if (is_on) {
OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
} else {
OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
}
if (!is_on != ani_state->ofdm_weak_sig_detect_off) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: ofdm weak signal: %s=>%s\n",
__func__, chan->ic_freq,
!ani_state->ofdm_weak_sig_detect_off ? "on" : "off",
is_on ? "on" : "off");
if (is_on) {
ahp->ah_stats.ast_ani_ofdmon++;
} else {
ahp->ah_stats.ast_ani_ofdmoff++;
}
ani_state->ofdm_weak_sig_detect_off = !is_on;
}
break;
}
case HAL_ANI_FIRSTEP_LEVEL:
if (level >= ARRAY_LENGTH(firstep_table)) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: HAL_ANI_FIRSTEP_LEVEL level out of range (%u > %u)\n",
__func__, level, (unsigned) ARRAY_LENGTH(firstep_table));
return AH_FALSE;
}
/*
* make register setting relative to default
* from INI file & cap value
*/
value =
firstep_table[level] -
firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] +
ani_state->ini_def.firstep;
if (value < HAL_SIG_FIRSTEP_SETTING_MIN) {
value = HAL_SIG_FIRSTEP_SETTING_MIN;
}
if (value > HAL_SIG_FIRSTEP_SETTING_MAX) {
value = HAL_SIG_FIRSTEP_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRSTEP, value);
/*
* we need to set first step low register too
* make register setting relative to default from INI file & cap value
*/
value2 =
firstep_table[level] -
firstep_table[HAL_ANI_DEF_FIRSTEP_LVL] +
ani_state->ini_def.firstep_low;
if (value2 < HAL_SIG_FIRSTEP_SETTING_MIN) {
value2 = HAL_SIG_FIRSTEP_SETTING_MIN;
}
if (value2 > HAL_SIG_FIRSTEP_SETTING_MAX) {
value2 = HAL_SIG_FIRSTEP_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
if (level != ani_state->firstep_level) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value, ani_state->ini_def.firstep);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"firstep_low[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->firstep_level, level,
HAL_ANI_DEF_FIRSTEP_LVL, value2,
ani_state->ini_def.firstep_low);
if (level > ani_state->firstep_level) {
ahp->ah_stats.ast_ani_stepup++;
} else if (level < ani_state->firstep_level) {
ahp->ah_stats.ast_ani_stepdown++;
}
ani_state->firstep_level = level;
}
break;
case HAL_ANI_SPUR_IMMUNITY_LEVEL:
if (level >= ARRAY_LENGTH(cycpwr_thr1_table)) {
HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
"%s: HAL_ANI_SPUR_IMMUNITY_LEVEL level "
"out of range (%u > %u)\n",
__func__, level, (unsigned) ARRAY_LENGTH(cycpwr_thr1_table));
return AH_FALSE;
}
/*
* make register setting relative to default from INI file & cap value
*/
value =
cycpwr_thr1_table[level] -
cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] +
ani_state->ini_def.cycpwr_thr1;
if (value < HAL_SIG_SPUR_IMM_SETTING_MIN) {
value = HAL_SIG_SPUR_IMM_SETTING_MIN;
}
if (value > HAL_SIG_SPUR_IMM_SETTING_MAX) {
value = HAL_SIG_SPUR_IMM_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5, AR_PHY_TIMING5_CYCPWR_THR1, value);
/*
* set AR_PHY_EXT_CCA for extension channel
* make register setting relative to default from INI file & cap value
*/
value2 =
cycpwr_thr1_table[level] -
cycpwr_thr1_table[HAL_ANI_DEF_SPUR_IMMUNE_LVL] +
ani_state->ini_def.cycpwr_thr1_ext;
if (value2 < HAL_SIG_SPUR_IMM_SETTING_MIN) {
value2 = HAL_SIG_SPUR_IMM_SETTING_MIN;
}
if (value2 > HAL_SIG_SPUR_IMM_SETTING_MAX) {
value2 = HAL_SIG_SPUR_IMM_SETTING_MAX;
}
OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CYCPWR_THR1, value2);
if (level != ani_state->spur_immunity_level) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value,
ani_state->ini_def.cycpwr_thr1);
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: level %d=>%d[def:%d] "
"cycpwr_thr1_ext[level]=%d ini=%d\n",
__func__, chan->ic_freq, ani_state->spur_immunity_level, level,
HAL_ANI_DEF_SPUR_IMMUNE_LVL, value2,
ani_state->ini_def.cycpwr_thr1_ext);
if (level > ani_state->spur_immunity_level) {
ahp->ah_stats.ast_ani_spurup++;
} else if (level < ani_state->spur_immunity_level) {
ahp->ah_stats.ast_ani_spurdown++;
}
ani_state->spur_immunity_level = level;
}
break;
case HAL_ANI_MRC_CCK:
/*
* is_on == 1 means MRC CCK ON (default, less noise imm)
* is_on == 0 means MRC CCK is OFF (more noise imm)
*/
is_on = param ? 1 : 0;
if (!AR_SREV_POSEIDON(ah)) {
OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
AR_PHY_MRC_CCK_ENABLE, is_on);
OS_REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
AR_PHY_MRC_CCK_MUX_REG, is_on);
}
if (!is_on != ani_state->mrc_cck_off) {
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ** ch %d: MRC CCK: %s=>%s\n", __func__, chan->ic_freq,
!ani_state->mrc_cck_off ? "on" : "off", is_on ? "on" : "off");
if (is_on) {
ahp->ah_stats.ast_ani_ccklow++;
} else {
ahp->ah_stats.ast_ani_cckhigh++;
}
ani_state->mrc_cck_off = !is_on;
}
break;
case HAL_ANI_PRESENT:
break;
#ifdef AH_PRIVATE_DIAG
case HAL_ANI_MODE:
if (param == 0) {
ahp->ah_proc_phy_err &= ~HAL_PROCESS_ANI;
/* Turn off HW counters if we have them */
ar9300_ani_detach(ah);
if (AH_PRIVATE(ah)->ah_curchan == NULL) {
return AH_TRUE;
}
/* if we're turning off ANI, reset regs back to INI settings */
if (ah->ah_config.ath_hal_enable_ani) {
HAL_ANI_CMD savefunc = ahp->ah_ani_function;
/* temporarly allow all functions so we can reset */
ahp->ah_ani_function = HAL_ANI_ALL;
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: disable all ANI functions\n", __func__);
ar9300_ani_set_odfm_noise_immunity_level(
ah, HAL_ANI_OFDM_DEF_LEVEL);
ar9300_ani_set_cck_noise_immunity_level(
ah, HAL_ANI_CCK_DEF_LEVEL);
ahp->ah_ani_function = savefunc;
}
} else { /* normal/auto mode */
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: enabled\n", __func__);
ahp->ah_proc_phy_err |= HAL_PROCESS_ANI;
if (AH_PRIVATE(ah)->ah_curchan == NULL) {
return AH_TRUE;
}
ar9300_enable_mib_counters(ah);
ar9300_ani_reset(ah, AH_FALSE);
ani_state = ahp->ah_curani;
}
HALDEBUG(ah, HAL_DEBUG_ANI, "5 ANC: ahp->ah_proc_phy_err %x \n",
ahp->ah_proc_phy_err);
break;
case HAL_ANI_PHYERR_RESET:
ahp->ah_stats.ast_ani_ofdmerrs = 0;
ahp->ah_stats.ast_ani_cckerrs = 0;
break;
#endif /* AH_PRIVATE_DIAG */
default:
#if HAL_ANI_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: invalid cmd 0x%02x (allowed=0x%02x)\n",
__func__, cmd, ahp->ah_ani_function);
#endif
return AH_FALSE;
}
#if HAL_ANI_DEBUG
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: ANI parameters: SI=%d, ofdm_ws=%s FS=%d MRCcck=%s listen_time=%d "
"CC=%d listen=%d ofdm_errs=%d cck_errs=%d\n",
__func__, ani_state->spur_immunity_level,
!ani_state->ofdm_weak_sig_detect_off ? "on" : "off",
ani_state->firstep_level, !ani_state->mrc_cck_off ? "on" : "off",
ani_state->listen_time, ani_state->cycle_count,
ani_state->listen_time, ani_state->ofdm_phy_err_count,
ani_state->cck_phy_err_count);
#endif
#ifndef REMOVE_PKT_LOG
/* do pktlog */
{
struct log_ani log_data;
/* Populate the ani log record */
log_data.phy_stats_disable = DO_ANI(ah);
log_data.noise_immun_lvl = ani_state->ofdm_noise_immunity_level;
log_data.spur_immun_lvl = ani_state->spur_immunity_level;
log_data.ofdm_weak_det = ani_state->ofdm_weak_sig_detect_off;
log_data.cck_weak_thr = ani_state->cck_noise_immunity_level;
log_data.fir_lvl = ani_state->firstep_level;
log_data.listen_time = ani_state->listen_time;
log_data.cycle_count = ani_state->cycle_count;
/* express ofdm_phy_err_count as errors/second */
log_data.ofdm_phy_err_count = ani_state->listen_time ?
ani_state->ofdm_phy_err_count * 1000 / ani_state->listen_time : 0;
/* express cck_phy_err_count as errors/second */
log_data.cck_phy_err_count = ani_state->listen_time ?
ani_state->cck_phy_err_count * 1000 / ani_state->listen_time : 0;
log_data.rssi = ani_state->rssi;
/* clear interrupt context flag */
ath_hal_log_ani(AH_PRIVATE(ah)->ah_sc, &log_data, 0);
}
#endif
return AH_TRUE;
}
static void
ar9300_ani_restart(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
if (!DO_ANI(ah)) {
return;
}
ani_state = ahp->ah_curani;
ani_state->listen_time = 0;
OS_REG_WRITE(ah, AR_PHY_ERR_1, 0);
OS_REG_WRITE(ah, AR_PHY_ERR_2, 0);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
/* Clear the mib counters and save them in the stats */
ar9300_update_mib_mac_stats(ah);
ani_state->ofdm_phy_err_count = 0;
ani_state->cck_phy_err_count = 0;
}
static void
ar9300_ani_ofdm_err_trigger(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
if (!DO_ANI(ah)) {
return;
}
ani_state = ahp->ah_curani;
if (ani_state->ofdm_noise_immunity_level < HAL_ANI_OFDM_MAX_LEVEL) {
ar9300_ani_set_odfm_noise_immunity_level(
ah, ani_state->ofdm_noise_immunity_level + 1);
}
}
static void
ar9300_ani_cck_err_trigger(struct ath_hal *ah)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
if (!DO_ANI(ah)) {
return;
}
ani_state = ahp->ah_curani;
if (ani_state->cck_noise_immunity_level < HAL_ANI_CCK_MAX_LEVEL) {
ar9300_ani_set_cck_noise_immunity_level(
ah, ani_state->cck_noise_immunity_level + 1);
}
}
/*
* Restore the ANI parameters in the HAL and reset the statistics.
* This routine should be called for every hardware reset and for
* every channel change.
*/
void
ar9300_ani_reset(struct ath_hal *ah, HAL_BOOL is_scanning)
{
struct ath_hal_9300 *ahp = AH9300(ah);
struct ar9300_ani_state *ani_state;
const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
int index;
HALASSERT(chan != AH_NULL);
if (!DO_ANI(ah)) {
return;
}
/*
* we need to re-point to the correct ANI state since the channel
* may have changed due to a fast channel change
*/
index = ar9300_get_ani_channel_index(ah, chan);
ani_state = &ahp->ah_ani[index];
HALASSERT(ani_state != AH_NULL);
ahp->ah_curani = ani_state;
ahp->ah_stats.ast_ani_reset++;
ani_state->phy_noise_spur = 0;
/* only allow a subset of functions in AP mode */
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
if (IS_CHAN_2GHZ(ichan)) {
ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
HAL_ANI_FIRSTEP_LEVEL |
HAL_ANI_MRC_CCK);
} else {
ahp->ah_ani_function = 0;
}
}
/* always allow mode (on/off) to be controlled */
ahp->ah_ani_function |= HAL_ANI_MODE;
if (is_scanning ||
(AH_PRIVATE(ah)->ah_opmode != HAL_M_STA &&
AH_PRIVATE(ah)->ah_opmode != HAL_M_IBSS))
{
/*
* If we're scanning or in AP mode, the defaults (ini) should be
* in place.
* For an AP we assume the historical levels for this channel are
* probably outdated so start from defaults instead.
*/
if (ani_state->ofdm_noise_immunity_level != HAL_ANI_OFDM_DEF_LEVEL ||
ani_state->cck_noise_immunity_level != HAL_ANI_CCK_DEF_LEVEL)
{
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore defaults: opmode %u chan %d Mhz/0x%x "
"is_scanning=%d restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
/*
* for STA/IBSS, we want to restore the historical values later
* (when we're not scanning)
*/
if (AH_PRIVATE(ah)->ah_opmode == HAL_M_STA ||
AH_PRIVATE(ah)->ah_opmode == HAL_M_IBSS)
{
ar9300_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
HAL_ANI_DEF_SPUR_IMMUNE_LVL);
ar9300_ani_control(
ah, HAL_ANI_FIRSTEP_LEVEL, HAL_ANI_DEF_FIRSTEP_LVL);
ar9300_ani_control(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
HAL_ANI_USE_OFDM_WEAK_SIG);
ar9300_ani_control(ah, HAL_ANI_MRC_CCK, HAL_ANI_ENABLE_MRC_CCK);
ani_state->must_restore = AH_TRUE;
} else {
ar9300_ani_set_odfm_noise_immunity_level(
ah, HAL_ANI_OFDM_DEF_LEVEL);
ar9300_ani_set_cck_noise_immunity_level(
ah, HAL_ANI_CCK_DEF_LEVEL);
}
}
} else {
/*
* restore historical levels for this channel
*/
HALDEBUG(ah, HAL_DEBUG_ANI,
"%s: Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d "
"restore=%d ofdm:%d cck:%d\n",
__func__, AH_PRIVATE(ah)->ah_opmode, chan->ic_freq,
chan->ic_flags, is_scanning, ani_state->must_restore,
ani_state->ofdm_noise_immunity_level,
ani_state->cck_noise_immunity_level);
ar9300_ani_set_odfm_noise_immunity_level(
ah, ani_state->ofdm_noise_immunity_level);
ar9300_ani_set_cck_noise_immunity_level(
ah, ani_state->cck_noise_immunity_level);
ani_state->must_restore = AH_FALSE;
}
/* enable phy counters */
ar9300_ani_restart(ah);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
}
/*
* Process a MIB interrupt. We may potentially be invoked because
* any of the MIB counters overflow/trigger so don't assume we're
* here because a PHY error counter triggered.
*/
void
ar9300_process_mib_intr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
{
struct ath_hal_9300 *ahp = AH9300(ah);
u_int32_t phy_cnt1, phy_cnt2;
#if 0
HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Processing Mib Intr\n", __func__);
#endif
/* Reset these counters regardless */
OS_REG_WRITE(ah, AR_FILT_OFDM, 0);
OS_REG_WRITE(ah, AR_FILT_CCK, 0);
if (!(OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING)) {
OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
}
/* Clear the mib counters and save them in the stats */
ar9300_update_mib_mac_stats(ah);
ahp->ah_stats.ast_nodestats = *stats;
if (!DO_ANI(ah)) {
/*
* We must always clear the interrupt cause by resetting
* the phy error regs.
*/
OS_REG_WRITE(ah, AR_PHY_ERR_1, 0);
OS_REG_WRITE(ah, AR_PHY_ERR_2, 0);
return;
}