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Specifically it would be great to be passed data whenever:
a module is instantiated. a wire is declared (a wire module is instantiated). m.wire is called
This data could be used by the CoreIR verilog backend to produce much prettier verilog that could correspond pretty well to the original magma file.
The text was updated successfully, but these errors were encountered:
Done via #266, waiting for coreir dev merge
Sorry, something went wrong.
rdaly525
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Specifically it would be great to be passed data whenever:
a module is instantiated.
a wire is declared (a wire module is instantiated).
m.wire is called
This data could be used by the CoreIR verilog backend to produce much prettier verilog that could correspond pretty well to the original magma file.
The text was updated successfully, but these errors were encountered: