-
Notifications
You must be signed in to change notification settings - Fork 67
/
CogIA32Compiler.class.st
4230 lines (3941 loc) · 134 KB
/
CogIA32Compiler.class.st
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
"
I generate IA32 (x86) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
(® is supposed to be the Unicode ""registered sign"".
This class does not take any special action to flush the instruction cache on instruction-modification, trusting that Intel and AMD processors correctly invalidate the instruction cache via snooping. According to the manuals, this will work on systems where code and data have the same virtual address. The CogICacheFlushingIA32Compiler subclass exists to use the CPUID instruction to serialize instruction-modification for systems with code and data at different virtual addresses.
"
Class {
#name : #CogIA32Compiler,
#superclass : #CogAbstractInstruction,
#classVars : [
'CDQ',
'CLD',
'CMPXCHGAwR',
'CMPXCHGMwrR',
'CPUID',
'EAX',
'EBP',
'EBX',
'ECX',
'EDI',
'EDX',
'ESI',
'ESP',
'FSTPD',
'FSTPS',
'IDIVR',
'IMULRR',
'LFENCE',
'LOCK',
'MFENCE',
'MOVSB',
'MOVSD',
'ModReg',
'ModRegInd',
'ModRegIndDisp32',
'ModRegIndSIB',
'ModRegRegDisp32',
'ModRegRegDisp8',
'REP',
'SFENCE',
'SIB1',
'SIB2',
'SIB4',
'SIB8',
'XCHGAwR',
'XCHGMwrR',
'XCHGRR',
'XMM0L',
'XMM1L',
'XMM2L',
'XMM3L',
'XMM4L',
'XMM5L',
'XMM6L',
'XMM7L'
],
#category : #'VMMaker-JIT'
}
{ #category : #translation }
CogIA32Compiler class >> ISA [
"Answer the name of the ISA the receiver implements."
^#IA32
]
{ #category : #translation }
CogIA32Compiler class >> identifyingPredefinedMacros [
^#('_M_I386' '_M_IX86' '_X86_' 'i386' 'i486' 'i586' 'i686' '__i386__' '__386__' 'X86' 'I386')
]
{ #category : #'class initialization' }
CogIA32Compiler class >> initialize [
"Initialize various IA32/x86 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogIA32Compiler initialize"
self ~~ CogIA32Compiler ifTrue: [^self].
"N.B. EAX ECX and EDX are caller-save (scratch) registers.
EBX ESI and EDI are callee-save; see concreteRegisterFor:"
EAX := 0.
ECX := 1. "Were they completely mad or simply sadistic?"
EDX := 2.
EBX := 3.
ESP := 4.
EBP := 5.
ESI := 6.
EDI := 7.
XMM0L := 0.
XMM1L := 1.
XMM2L := 2.
XMM3L := 3.
XMM4L := 4.
XMM5L := 5.
XMM6L := 6.
XMM7L := 7.
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR FSTPS FSTPD CLD REP MOVSB MOVSD)
in: thisContext method
]
{ #category : #'class initialization' }
CogIA32Compiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
super initializeAbstractRegisters.
"N.B. EAX ECX & EDX are caller-save (scratch) registers. Hence we use ECX for class and EDX for
receiver/result since these are written in all normal sends. EBX ESI & EDI are callee-save."
CallerSavedRegisterMask := self registerMaskFor: EAX and: ECX and: EDX.
TempReg := EAX.
ClassReg := ECX.
ReceiverResultReg := EDX.
SendNumArgsReg := EBX.
SPReg := ESP.
FPReg := EBP.
Arg0Reg := ESI.
Arg1Reg := EDI.
NumRegisters := 8.
DPFPReg0 := XMM0L.
DPFPReg1 := XMM1L.
DPFPReg2 := XMM2L.
DPFPReg3 := XMM3L.
DPFPReg4 := XMM4L.
DPFPReg5 := XMM5L.
DPFPReg6 := XMM6L.
DPFPReg7 := XMM7L.
NumFloatRegisters := 8
]
{ #category : #testing }
CogIA32Compiler class >> isRISCTempRegister: reg [
"For tests to filter-out bogus values left in the RISCTempRegister, if any."
^false
]
{ #category : #translation }
CogIA32Compiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array."
^{#'unsigned char'. '[', self basicNew machineCodeBytes printString, ']'}
]
{ #category : #verification }
CogIA32Compiler class >> specificOpcodes [
"Answer the processor-specific opcodes for this class.
They're all in an Array literal in the initialize method."
^(self class >> #initialize) literals detect: [:l| l isArray and: [l includes: #LOCK]]
]
{ #category : #translation }
CogIA32Compiler class >> wordSize [
"This is a 32-bit ISA"
^4
]
{ #category : #testing }
CogIA32Compiler >> byteReadsZeroExtend [
"Answer if a byte read, via MoveAbR, MoveMbrR, or MoveXbrRR zero-extends
into the full register, or merely affects the least significant 8 bits of the
the register. By default the code generator assumes that byte reads
to not zero extend. Note that byte reads /must not/ sign extend.
On x86 we always use movzbl"
^true
]
{ #category : #abi }
CogIA32Compiler >> cFloatResultToRd: reg [
cogit gen: FSTPD operand: -8 operand: SPReg .
cogit MoveM64: -8 r: SPReg Rd: reg
]
{ #category : #abi }
CogIA32Compiler >> cFloatResultToRs: reg [
cogit gen: FSTPS operand: -4 operand: SPReg.
cogit MoveM32: -4 r: SPReg Rs: reg
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegister [
"Answer the register through which C funcitons return integral results."
<inline: true>
^EAX
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegisterHigh [
"Answer the abstract register for the C result register.
Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
^ EDX
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegisterLow [
"Answer the abstract register for the C result register.
Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
^ EAX
]
{ #category : #accessing }
CogIA32Compiler >> cStackPointer [
^ ESP
]
{ #category : #'inline cacheing' }
CogIA32Compiler >> callFullTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the call immediately preceding callSiteReturnAddress will jump to."
^self callTargetFromReturnAddress: callSiteReturnAddress
]
{ #category : #accessing }
CogIA32Compiler >> callInstructionByteSize [
^5
]
{ #category : #'inline cacheing' }
CogIA32Compiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the call immediately preceding callSiteReturnAddress will jump to."
| callDistance |
callDistance := self literalBeforeFollowingAddress: callSiteReturnAddress.
^callSiteReturnAddress + callDistance signedIntFromLong
]
{ #category : #testing }
CogIA32Compiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogIA32Compiler >> canMulRR [
^true
]
{ #category : #testing }
CogIA32Compiler >> canSignExtend [
"IA32 has native SignExtend8RR & SignExtend16RR."
<inline: true>
^true
]
{ #category : #testing }
CogIA32Compiler >> canZeroExtend [
"IA32 has native ZeroExtend8RR & ZeroExtend16RR."
<inline: true>
^true
]
{ #category : #accessing }
CogIA32Compiler >> cmpC32RTempByteSize [
^5
]
{ #category : #accessing }
CogIA32Compiler >> codeGranularity [
"Answer the size in bytes of a unit of machine code."
^1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> computeMaximumSize [
"Compute the maximum size for each opcode. This allows jump offsets to
be determined, provided that all backward branches are long branches."
"N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[AlignmentNops] -> [^(operands at: 0) - 1].
[Fill32] -> [^4].
[Nop] -> [^1].
"Specific Control/Data Movement"
[REP] -> [^1].
[CLD] -> [^1].
[MOVSB] -> [^1].
[MOVSD] -> [^1].
[CDQ] -> [^1].
[IDIVR] -> [^2].
[IMULRR] -> [^3].
[CPUID] -> [^2].
[CMPXCHGAwR] -> [^7].
[CMPXCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[LFENCE] -> [^3].
[MFENCE] -> [^3].
[SFENCE] -> [^3].
[LOCK] -> [^1].
[XCHGAwR] -> [^6].
[XCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]].
[XCHGRR] -> [^((operands at: 0) = EAX
or: [(operands at: 1) = EAX])
ifTrue: [1]
ifFalse: [2]].
[FSTPS] -> [^7].
[FSTPD] -> [^7].
"Control"
[CallFull] -> [^5].
[Call] -> [^5].
[CallR] -> [^2].
[JumpR] -> [^2].
[JumpFull] -> [self resolveJumpTarget. ^5].
[JumpLong] -> [self resolveJumpTarget. ^5].
[Jump] -> [self resolveJumpTarget. ^5].
[JumpZero] -> [self resolveJumpTarget. ^6].
[JumpNonZero] -> [self resolveJumpTarget. ^6].
[JumpNegative] -> [self resolveJumpTarget. ^6].
[JumpNonNegative] -> [self resolveJumpTarget. ^6].
[JumpOverflow] -> [self resolveJumpTarget. ^6].
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].
[JumpCarry] -> [self resolveJumpTarget. ^6].
[JumpNoCarry] -> [self resolveJumpTarget. ^6].
[JumpLess] -> [self resolveJumpTarget. ^6].
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpGreater] -> [self resolveJumpTarget. ^6].
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpBelow] -> [self resolveJumpTarget. ^6].
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].
[JumpAbove] -> [self resolveJumpTarget. ^6].
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].
[JumpLongZero] -> [self resolveJumpTarget. ^6].
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].
[JumpFPEqual] -> [self resolveJumpTarget. ^6].
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].
[JumpFPLess] -> [self resolveJumpTarget. ^6].
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPGreater] -> [self resolveJumpTarget. ^6].
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].
[Stop] -> [^1].
"Arithmetic"
[AddCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AddcCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AndCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[CmpCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[OrCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[SubCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(operands at: 1) < 4])
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AddCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AndCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[CmpCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[OrCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[SubCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[XorCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AddRR] -> [^2].
[AndRR] -> [^2].
[CmpRR] -> [^2].
[OrRR] -> [^2].
[XorRR] -> [^2].
[SubRR] -> [^2].
[NegateR] -> [^2].
[NotR] -> [^2].
[LoadEffectiveAddressMwrR]
-> [^((self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].
[LogicalShiftRightRR] -> [^self computeShiftRRSize].
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
[XorRdRd] -> [^4].
[AddRsRs] -> [^4].
[CmpRsRs] -> [^3].
[SubRsRs] -> [^4].
[MulRsRs] -> [^4].
[DivRsRs] -> [^4].
[SqrtRs] -> [^4].
[XorRsRs] -> [^3].
"Data Movement"
[MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]].
[MoveCwR] -> [^5].
[MoveRR] -> [^2].
[MoveRdRd] -> [^4].
[MoveRsRs] -> [^4].
[MoveAwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRAw] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
[MoveAbR] -> [^7].
[MoveRAb] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [(operands at: 2) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRMwr] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [(operands at: 2) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRsM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveMbrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRMbr] -> [^(operands at: 2) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
[MoveM8rR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRM8r] -> [^(operands at: 2) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
[MoveM16rR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRM16r] -> [^(operands at: 2) = ESP
ifTrue: [8]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [4] ifFalse: [7]]].
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveM32rRs] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveM32rR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [(operands at: 1) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveMwrR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [(operands at: 1) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveXbrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [5]
ifFalse: [4]].
[MoveRXbrR] -> [self assert: (operands at: 1) ~= ESP.
^((operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3])
+ ((operands at: 0) >= 4
ifTrue: [2]
ifFalse: [0])].
[MoveXwrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [4]
ifFalse: [3]].
[MoveRXwrR] -> [self assert: (operands at: 1) ~= ESP.
^(operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3]].
[PopR] -> [^1].
[PushR] -> [^1].
[PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]].
[PushCw] -> [^5].
[PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]].
"Conversion"
[ConvertRRd] -> [^4].
[ConvertRdR] -> [^4].
[ConvertRsRd] -> [^4].
[ConvertRdRs] -> [^4].
[ConvertRsR] -> [^4].
[ConvertRRs] -> [^4].
[SignExtend8RR] -> [^3].
[SignExtend16RR] -> [^3].
[ZeroExtend8RR] -> [^3].
[ZeroExtend16RR] -> [^3].
"This is a fixed size instruction using a patcheable literal. This takes ALWAYS 1 instruction of 5 bytes"
[MovePatcheableC32R] -> [ ^ 5 ]
}.
^0 "to keep C compiler quiet"
]
{ #category : #'generate machine code' }
CogIA32Compiler >> computeShiftRRSize [
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
shiftCountReg := operands at: 0.
^shiftCountReg = ECX
ifTrue: [2]
ifFalse:
[shiftCountReg = EAX
ifTrue: [1 "XCHG EAX,r2" + 2 "Sxx" + 1 "XCHG EAX,r2"]
ifFalse: [2 "XCHG r1,r2" + 2 "Sxx" + 2 "XCHG r1,r2"]]
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddcCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 2);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r15;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 2);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddcRR [
"Will get inlined into concretizeAt: switch."
<inline: true>
"Assemble the ADC instruction"
| regLHS regRHS |
regLHS := operands at: 0.
regRHS := operands at: 1.
machineCode
at: 0 put: 16r13;
at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAlignmentNops [
<inline: true>
self flag: 'if performance is an issue generate longer nops'.
0 to: machineCodeSize - 1 do:
[:i|
machineCode at: i put: 16r90]
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAndCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| mask reg |
mask := operands at: 0.
reg := operands at: 1.
(self isQuick: mask) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (mask bitAnd: 16rFF);
at: 2 put: (mask >> 8 bitAnd: 16rFF);
at: 3 put: (mask >> 16 bitAnd: 16rFF);
at: 4 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF);
at: 3 put: (mask >> 8 bitAnd: 16rFF);
at: 4 put: (mask >> 16 bitAnd: 16rFF);
at: 5 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAndCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeArithmeticShiftRightCqR [
<inline: true>
| shiftCount reg |
shiftCount := (operands at: 0) min: 31.
reg := operands at: 1.
shiftCount = 1 ifTrue:
[machineCode
at: 0 put: 16rD1;
at: 1 put: (self mod: ModReg RM: reg RO: 7).
^machineCodeSize := 2].
machineCode
at: 0 put: 16rC1;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: shiftCount.
^machineCodeSize := 3
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeArithmeticShiftRightRR [
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into %ecx."
<inline: true>
| shiftCountReg destReg regToShift |
shiftCountReg := operands at: 0.
destReg := operands at: 1.
shiftCountReg = ECX ifTrue:
[machineCode
at: 0 put: 16rD3;
at: 1 put: (self mod: ModReg RM: destReg RO: 7).
^machineCodeSize := 2].
regToShift := destReg == shiftCountReg
ifTrue: [ECX]
ifFalse: [destReg = ECX
ifTrue: [shiftCountReg]
ifFalse: [destReg]].
shiftCountReg = EAX ifTrue:
[machineCode
at: 0 put: 16r90 + ECX; "XCHG EAX,ECX"
at: 1 put: 16rD3; "SAR ECX,EAX"
at: 2 put: (self mod: ModReg RM: regToShift RO: 7);
at: 3 put: 16r90 + ECX. "XCHG EAX,ECX"
^machineCodeSize := 4].
machineCode
at: 0 put: 16r87; "XCHG E?X,ECX"
at: 1 put: (self mod: ModReg RM: ECX RO: shiftCountReg);
at: 2 put: 16rD3; "SAR ECX,E!X"
at: 3 put: (self mod: ModReg RM: regToShift RO: 7);
at: 4 put: 16r87; "XCHG E?X,ECX"
at: 5 put: (self mod: ModReg RM: ECX RO: shiftCountReg).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCDQ [
"Will get inlined into concretizeAt: switch."
<inline: true>
machineCode at: 0 put: 16r99.
^machineCodeSize := 1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCLD [
<inline: true>
machineCode at: 0 put: 16rFC.
^machineCodeSize := 1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCMPXCHGAwR [
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
reg := operands at: 1.
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 3 put: (addressOperand bitAnd: 16rFF);
at: 4 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 6 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 7
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCMPXCHGMwrR [
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
srcReg := operands at: 1.
destReg := operands at: 2.
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCPUID [
<inline: true>
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rA2.
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCall [
"Will get inlined into concretizeAt: switch."
<inline: true>
| offset |
self assert: (operands at: 0) ~= 0.
offset := (operands at: 0) signedIntFromLong - (address + 5) signedIntFromLong.
machineCode
at: 0 put: 16rE8;
at: 1 put: (offset bitAnd: 16rFF);
at: 2 put: (offset >> 8 bitAnd: 16rFF);
at: 3 put: (offset >> 16 bitAnd: 16rFF);
at: 4 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 5
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCallR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
reg := operands at: 0.
machineCode
at: 0 put: 16rFF;
at: 1 put: (self mod: ModReg RM: reg RO: 2).
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpRdRd [
"Will get inlined into concretizeAt: switch.
We use UCOMISD (see p 4-260 [2])"
<inline: true>
| regLHS regRHS |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
regRHS := operands at: 0.
regLHS := operands at: 1.
machineCode
at: 0 put: 16r66;
at: 1 put: 16r0F;
at: 2 put: 16r2E;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpRsRs [
"Will get inlined into concretizeAt: switch.
We use UCOMISS (see p 4-260 [2])"