-
Notifications
You must be signed in to change notification settings - Fork 65
/
VMARMV8SIMDEncodingTest.class.st
145 lines (104 loc) · 3.39 KB
/
VMARMV8SIMDEncodingTest.class.st
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Class {
#name : #VMARMV8SIMDEncodingTest,
#superclass : #VMSimpleStackBasedCogitAbstractTest,
#category : #'VMMakerTests-JitTests'
}
{ #category : #'building suites' }
VMARMV8SIMDEncodingTest class >> wordSizeParameters [
^ ParametrizedTestMatrix new
addCase: { #ISA -> #'aarch64'. #wordSize -> 8};
yourself
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> armInstructionAt: index [
| addr inst |
addr := memory getMemoryMap codeZoneStart + ((index - 1) * 8).
inst := memory uint32AtPointer: addr.
^ inst aarch64Disassembled
]
{ #category : #configuration }
VMARMV8SIMDEncodingTest >> generateCaptureCStackPointers [
^ false
]
{ #category : #accessing }
VMARMV8SIMDEncodingTest >> initializationOptions [
^ super initializationOptions , {
#ProcessorClass . DummyProcessor }
]
{ #category : #accessing }
VMARMV8SIMDEncodingTest >> jitOptions [
^ super jitOptions
at: #ProcessorClass
put: DummyProcessor;
yourself
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeDupWith64BitLanes [
self compile: [ cogit DupS: 64 R: 3 Vr: 0 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'dup v0.2d, x3'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeFaddWith32BitLanes [
self compile: [ cogit FaddS: 32 Rv: 0 Rv: 1 Rv: 2 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'fadd v2.4s, v0.4s, v1.4s'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeFaddWith64BitLanes [
self compile: [ cogit FaddS: 64 Rv: 0 Rv: 1 Rv: 2 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'fadd v2.2d, v0.2d, v1.2d'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeFsubWith64BitLanes [
self compile: [ cogit FsubS: 64 Rv: 0 Rv: 1 Rv: 2 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'fsub v2.2d, v0.2d, v1.2d'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeLd1WithOne32BitLaneRegisterAndImmediateOffset [
self compile: [ cogit Ld1S: 32 Vr: 0 R: 1 Mw: 16 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'ld1 { v0.4s }, [x1], #16'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeLd1WithOne64BitLaneRegisterAndImmediateOffset [
self compile: [ cogit Ld1S: 64 Vr: 0 R: 1 Mw: 16 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'ld1 { v0.2d }, [x1], #16'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeLd1WithOne64BitLaneRegisterAndNoOffset [
self compile: [ cogit Ld1S: 64 Vr: 0 R: 1 Mw: 0 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'ld1 { v0.2d }, [x1]'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeSt1WithOne32BitLaneRegisterAndImmediateOffset [
self compile: [ cogit St1S: 32 Vr: 0 R: 1 Mw: 16 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'st1 { v0.4s }, [x1], #16'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeSt1WithOne64BitLaneRegisterAndImmediateOffset [
self compile: [ cogit St1S: 64 Vr: 0 R: 1 Mw: 16 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'st1 { v0.2d }, [x1], #16'
]
{ #category : #tests }
VMARMV8SIMDEncodingTest >> testEncodeSt1WithOne64BitLaneRegisterAndNoOffset [
self compile: [ cogit St1S: 64 Vr: 0 R: 1 Mw: 0 ].
self
assert: (self armInstructionAt: 1) assemblyCodeString
equals: 'st1 { v0.2d }, [x1]'
]