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CogIA32Compiler.class.st
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CogIA32Compiler.class.st
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"
I generate IA32 (x86) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
(® is supposed to be the Unicode ""registered sign"".
This class does not take any special action to flush the instruction cache on instruction-modification, trusting that Intel and AMD processors correctly invalidate the instruction cache via snooping. According to the manuals, this will work on systems where code and data have the same virtual address. The CogICacheFlushingIA32Compiler subclass exists to use the CPUID instruction to serialize instruction-modification for systems with code and data at different virtual addresses.
"
Class {
#name : #CogIA32Compiler,
#superclass : #CogAbstractInstruction,
#classVars : [
'CDQ',
'CLD',
'CMPXCHGAwR',
'CMPXCHGMwrR',
'CPUID',
'EAX',
'EBP',
'EBX',
'ECX',
'EDI',
'EDX',
'ESI',
'ESP',
'FSTPD',
'FSTPS',
'IDIVR',
'IMULRR',
'LFENCE',
'LOCK',
'MFENCE',
'MOVSB',
'MOVSD',
'ModReg',
'ModRegInd',
'ModRegIndDisp32',
'ModRegIndSIB',
'ModRegRegDisp32',
'ModRegRegDisp8',
'REP',
'SFENCE',
'SIB1',
'SIB2',
'SIB4',
'SIB8',
'XCHGAwR',
'XCHGMwrR',
'XCHGRR',
'XMM0L',
'XMM1L',
'XMM2L',
'XMM3L',
'XMM4L',
'XMM5L',
'XMM6L',
'XMM7L'
],
#category : #'VMMaker-JIT'
}
{ #category : #translation }
CogIA32Compiler class >> ISA [
"Answer the name of the ISA the receiver implements."
^#IA32
]
{ #category : #translation }
CogIA32Compiler class >> identifyingPredefinedMacros [
^#('_M_I386' '_M_IX86' '_X86_' 'i386' 'i486' 'i586' 'i686' '__i386__' '__386__' 'X86' 'I386')
]
{ #category : #'class initialization' }
CogIA32Compiler class >> initialize [
"Initialize various IA32/x86 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogIA32Compiler initialize"
self ~~ CogIA32Compiler ifTrue: [^self].
"N.B. EAX ECX and EDX are caller-save (scratch) registers.
EBX ESI and EDI are callee-save; see concreteRegisterFor:"
EAX := 0.
ECX := 1. "Were they completely mad or simply sadistic?"
EDX := 2.
EBX := 3.
ESP := 4.
EBP := 5.
ESI := 6.
EDI := 7.
XMM0L := 0.
XMM1L := 1.
XMM2L := 2.
XMM3L := 3.
XMM4L := 4.
XMM5L := 5.
XMM6L := 6.
XMM7L := 7.
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR FSTPS FSTPD CLD REP MOVSB MOVSD)
in: thisContext method
]
{ #category : #'class initialization' }
CogIA32Compiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
super initializeAbstractRegisters.
"N.B. EAX ECX & EDX are caller-save (scratch) registers. Hence we use ECX for class and EDX for
receiver/result since these are written in all normal sends. EBX ESI & EDI are callee-save."
CallerSavedRegisterMask := self registerMaskFor: EAX and: ECX and: EDX.
TempReg := EAX.
ClassReg := ECX.
ReceiverResultReg := EDX.
SendNumArgsReg := EBX.
SPReg := ESP.
FPReg := EBP.
Arg0Reg := ESI.
Arg1Reg := EDI.
NumRegisters := 8.
DPFPReg0 := XMM0L.
DPFPReg1 := XMM1L.
DPFPReg2 := XMM2L.
DPFPReg3 := XMM3L.
DPFPReg4 := XMM4L.
DPFPReg5 := XMM5L.
DPFPReg6 := XMM6L.
DPFPReg7 := XMM7L.
NumFloatRegisters := 8
]
{ #category : #testing }
CogIA32Compiler class >> isRISCTempRegister: reg [
"For tests to filter-out bogus values left in the RISCTempRegister, if any."
^false
]
{ #category : #translation }
CogIA32Compiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array."
^{#'unsigned char'. '[', self basicNew machineCodeBytes printString, ']'}
]
{ #category : #verification }
CogIA32Compiler class >> specificOpcodes [
"Answer the processor-specific opcodes for this class.
They're all in an Array literal in the initialize method."
^(self class >> #initialize) literals detect: [:l| l isArray and: [l includes: #LOCK]]
]
{ #category : #translation }
CogIA32Compiler class >> wordSize [
"This is a 32-bit ISA"
^4
]
{ #category : #testing }
CogIA32Compiler >> byteReadsZeroExtend [
"Answer if a byte read, via MoveAbR, MoveMbrR, or MoveXbrRR zero-extends
into the full register, or merely affects the least significant 8 bits of the
the register. By default the code generator assumes that byte reads
to not zero extend. Note that byte reads /must not/ sign extend.
On x86 we always use movzbl"
^true
]
{ #category : #abi }
CogIA32Compiler >> cFloatResultToRd: reg [
cogit gen: FSTPD operand: -8 operand: SPReg .
cogit MoveM64: -8 r: SPReg Rd: reg
]
{ #category : #abi }
CogIA32Compiler >> cFloatResultToRs: reg [
cogit gen: FSTPS operand: -4 operand: SPReg.
cogit MoveM32: -4 r: SPReg Rs: reg
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegister [
"Answer the register through which C funcitons return integral results."
<inline: true>
^EAX
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegisterHigh [
"Answer the abstract register for the C result register.
Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
^ EDX
]
{ #category : #accessing }
CogIA32Compiler >> cResultRegisterLow [
"Answer the abstract register for the C result register.
Only partially implemented. Works on x86 since TempReg = EAX = C result reg."
^ EAX
]
{ #category : #accessing }
CogIA32Compiler >> cStackPointer [
^ ESP
]
{ #category : #'inline cacheing' }
CogIA32Compiler >> callFullTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the call immediately preceding callSiteReturnAddress will jump to."
^self callTargetFromReturnAddress: callSiteReturnAddress
]
{ #category : #accessing }
CogIA32Compiler >> callInstructionByteSize [
^5
]
{ #category : #'inline cacheing' }
CogIA32Compiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the call immediately preceding callSiteReturnAddress will jump to."
| callDistance |
callDistance := self literalBeforeFollowingAddress: callSiteReturnAddress.
^callSiteReturnAddress + callDistance signedIntFromLong
]
{ #category : #testing }
CogIA32Compiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogIA32Compiler >> canMulRR [
^true
]
{ #category : #testing }
CogIA32Compiler >> canSignExtend [
"IA32 has native SignExtend8RR & SignExtend16RR."
<inline: true>
^true
]
{ #category : #testing }
CogIA32Compiler >> canZeroExtend [
"IA32 has native ZeroExtend8RR & ZeroExtend16RR."
<inline: true>
^true
]
{ #category : #accessing }
CogIA32Compiler >> cmpC32RTempByteSize [
^5
]
{ #category : #accessing }
CogIA32Compiler >> codeGranularity [
"Answer the size in bytes of a unit of machine code."
^1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> computeMaximumSize [
"Compute the maximum size for each opcode. This allows jump offsets to
be determined, provided that all backward branches are long branches."
"N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[AlignmentNops] -> [^(operands at: 0) - 1].
[Fill32] -> [^4].
[Nop] -> [^1].
"Specific Control/Data Movement"
[REP] -> [^1].
[CLD] -> [^1].
[MOVSB] -> [^1].
[MOVSD] -> [^1].
[CDQ] -> [^1].
[IDIVR] -> [^2].
[IMULRR] -> [^3].
[CPUID] -> [^2].
[CMPXCHGAwR] -> [^7].
[CMPXCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[LFENCE] -> [^3].
[MFENCE] -> [^3].
[SFENCE] -> [^3].
[LOCK] -> [^1].
[XCHGAwR] -> [^6].
[XCHGMwrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [3] ifFalse: [6]]].
[XCHGRR] -> [^((operands at: 0) = EAX
or: [(operands at: 1) = EAX])
ifTrue: [1]
ifFalse: [2]].
[FSTPS] -> [^7].
[FSTPD] -> [^7].
"Control"
[CallFull] -> [^5].
[Call] -> [^5].
[CallR] -> [^2].
[JumpR] -> [^2].
[JumpFull] -> [self resolveJumpTarget. ^5].
[JumpLong] -> [self resolveJumpTarget. ^5].
[Jump] -> [self resolveJumpTarget. ^5].
[JumpZero] -> [self resolveJumpTarget. ^6].
[JumpNonZero] -> [self resolveJumpTarget. ^6].
[JumpNegative] -> [self resolveJumpTarget. ^6].
[JumpNonNegative] -> [self resolveJumpTarget. ^6].
[JumpOverflow] -> [self resolveJumpTarget. ^6].
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].
[JumpCarry] -> [self resolveJumpTarget. ^6].
[JumpNoCarry] -> [self resolveJumpTarget. ^6].
[JumpLess] -> [self resolveJumpTarget. ^6].
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpGreater] -> [self resolveJumpTarget. ^6].
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpBelow] -> [self resolveJumpTarget. ^6].
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].
[JumpAbove] -> [self resolveJumpTarget. ^6].
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].
[JumpLongZero] -> [self resolveJumpTarget. ^6].
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].
[JumpFPEqual] -> [self resolveJumpTarget. ^6].
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].
[JumpFPLess] -> [self resolveJumpTarget. ^6].
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPGreater] -> [self resolveJumpTarget. ^6].
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].
[Stop] -> [^1].
"Arithmetic"
[AddCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AddcCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AndCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[CmpCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[OrCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[SubCqR] -> [^(self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[TstCqR] -> [^((self isQuick: (operands at: 0)) and: [(operands at: 1) < 4])
ifTrue: [3]
ifFalse: [(operands at: 1) = EAX
ifTrue: [5]
ifFalse: [6]]].
[AddCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AndCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[CmpCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[OrCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[SubCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[XorCwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[AddRR] -> [^2].
[AndRR] -> [^2].
[CmpRR] -> [^2].
[OrRR] -> [^2].
[XorRR] -> [^2].
[SubRR] -> [^2].
[NegateR] -> [^2].
[NotR] -> [^2].
[LoadEffectiveAddressMwrR]
-> [^((self isQuick: (operands at: 0))
ifTrue: [3]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [2] ifFalse: [3]].
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].
[LogicalShiftRightRR] -> [^self computeShiftRRSize].
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
[XorRdRd] -> [^4].
[AddRsRs] -> [^4].
[CmpRsRs] -> [^3].
[SubRsRs] -> [^4].
[MulRsRs] -> [^4].
[DivRsRs] -> [^4].
[SqrtRs] -> [^4].
[XorRsRs] -> [^3].
"Data Movement"
[MoveCqR] -> [^(operands at: 0) = 0 ifTrue: [2] ifFalse: [5]].
[MoveCwR] -> [^5].
[MoveRR] -> [^2].
[MoveRdRd] -> [^4].
[MoveRsRs] -> [^4].
[MoveAwR] -> [^(operands at: 1) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRAw] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
[MoveAbR] -> [^7].
[MoveRAb] -> [^(operands at: 0) = EAX ifTrue: [5] ifFalse: [6]].
[MoveRM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [(operands at: 2) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRMwr] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [(operands at: 2) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveRsM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 2) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveMbrR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRMbr] -> [^(operands at: 2) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
[MoveM8rR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRM8r] -> [^(operands at: 2) = ESP
ifTrue: [7]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [3] ifFalse: [6]]].
[MoveM16rR] -> [^(operands at: 1) = ESP
ifTrue: [(self isQuick: (operands at: 0)) ifTrue: [5] ifFalse: [8]]
ifFalse: [(self isQuick: (operands at: 0)) ifTrue: [4] ifFalse: [7]]].
[MoveRM16r] -> [^(operands at: 2) = ESP
ifTrue: [8]
ifFalse: [(self isQuick: (operands at: 1)) ifTrue: [4] ifFalse: [7]]].
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveM32rRs] -> [^((self isQuick: (operands at: 0))
ifTrue: [5]
ifFalse: [8])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveM32rR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [(operands at: 1) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveMwrR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [(operands at: 1) ~= EBP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((operands at: 1) = ESP
ifTrue: [1]
ifFalse: [0])].
[MoveXbrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [5]
ifFalse: [4]].
[MoveRXbrR] -> [self assert: (operands at: 1) ~= ESP.
^((operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3])
+ ((operands at: 0) >= 4
ifTrue: [2]
ifFalse: [0])].
[MoveXwrRR] -> [self assert: (operands at: 0) ~= ESP.
^(operands at: 1) = EBP
ifTrue: [4]
ifFalse: [3]].
[MoveRXwrR] -> [self assert: (operands at: 1) ~= ESP.
^(operands at: 2) = EBP
ifTrue: [4]
ifFalse: [3]].
[PopR] -> [^1].
[PushR] -> [^1].
[PushCq] -> [^(self isQuick: (operands at: 0)) ifTrue: [2] ifFalse: [5]].
[PushCw] -> [^5].
[PrefetchAw] -> [^self hasSSEInstructions ifTrue: [7] ifFalse: [0]].
"Conversion"
[ConvertRRd] -> [^4].
[ConvertRdR] -> [^4].
[ConvertRsRd] -> [^4].
[ConvertRdRs] -> [^4].
[ConvertRsR] -> [^4].
[ConvertRRs] -> [^4].
[SignExtend8RR] -> [^3].
[SignExtend16RR] -> [^3].
[ZeroExtend8RR] -> [^3].
[ZeroExtend16RR] -> [^3].
"This is a fixed size instruction using a patcheable literal. This takes ALWAYS 1 instruction of 5 bytes"
[MovePatcheableC32R] -> [ ^ 5 ]
}.
^0 "to keep C compiler quiet"
]
{ #category : #'generate machine code' }
CogIA32Compiler >> computeShiftRRSize [
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
shiftCountReg := operands at: 0.
^shiftCountReg = ECX
ifTrue: [2]
ifFalse:
[shiftCountReg = EAX
ifTrue: [1 "XCHG EAX,r2" + 2 "Sxx" + 1 "XCHG EAX,r2"]
ifFalse: [2 "XCHG r1,r2" + 2 "Sxx" + 2 "XCHG r1,r2"]]
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r05;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 0);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddcCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 2);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r15;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 2);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAddcRR [
"Will get inlined into concretizeAt: switch."
<inline: true>
"Assemble the ADC instruction"
| regLHS regRHS |
regLHS := operands at: 0.
regRHS := operands at: 1.
machineCode
at: 0 put: 16r13;
at: 1 put: (self mod: ModReg RM: regLHS RO: regRHS).
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAlignmentNops [
<inline: true>
self flag: 'if performance is an issue generate longer nops'.
0 to: machineCodeSize - 1 do:
[:i|
machineCode at: i put: 16r90]
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAndCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| mask reg |
mask := operands at: 0.
reg := operands at: 1.
(self isQuick: mask) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (mask bitAnd: 16rFF);
at: 2 put: (mask >> 8 bitAnd: 16rFF);
at: 3 put: (mask >> 16 bitAnd: 16rFF);
at: 4 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (mask bitAnd: 16rFF);
at: 3 put: (mask >> 8 bitAnd: 16rFF);
at: 4 put: (mask >> 16 bitAnd: 16rFF);
at: 5 put: (mask >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeAndCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r25;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 4);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeArithmeticShiftRightCqR [
<inline: true>
| shiftCount reg |
shiftCount := (operands at: 0) min: 31.
reg := operands at: 1.
shiftCount = 1 ifTrue:
[machineCode
at: 0 put: 16rD1;
at: 1 put: (self mod: ModReg RM: reg RO: 7).
^machineCodeSize := 2].
machineCode
at: 0 put: 16rC1;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: shiftCount.
^machineCodeSize := 3
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeArithmeticShiftRightRR [
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into %ecx."
<inline: true>
| shiftCountReg destReg regToShift |
shiftCountReg := operands at: 0.
destReg := operands at: 1.
shiftCountReg = ECX ifTrue:
[machineCode
at: 0 put: 16rD3;
at: 1 put: (self mod: ModReg RM: destReg RO: 7).
^machineCodeSize := 2].
regToShift := destReg == shiftCountReg
ifTrue: [ECX]
ifFalse: [destReg = ECX
ifTrue: [shiftCountReg]
ifFalse: [destReg]].
shiftCountReg = EAX ifTrue:
[machineCode
at: 0 put: 16r90 + ECX; "XCHG EAX,ECX"
at: 1 put: 16rD3; "SAR ECX,EAX"
at: 2 put: (self mod: ModReg RM: regToShift RO: 7);
at: 3 put: 16r90 + ECX. "XCHG EAX,ECX"
^machineCodeSize := 4].
machineCode
at: 0 put: 16r87; "XCHG E?X,ECX"
at: 1 put: (self mod: ModReg RM: ECX RO: shiftCountReg);
at: 2 put: 16rD3; "SAR ECX,E!X"
at: 3 put: (self mod: ModReg RM: regToShift RO: 7);
at: 4 put: 16r87; "XCHG E?X,ECX"
at: 5 put: (self mod: ModReg RM: ECX RO: shiftCountReg).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCDQ [
"Will get inlined into concretizeAt: switch."
<inline: true>
machineCode at: 0 put: 16r99.
^machineCodeSize := 1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCLD [
<inline: true>
machineCode at: 0 put: 16rFC.
^machineCodeSize := 1
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCMPXCHGAwR [
<inline: true>
| addressOperand reg |
addressOperand := operands at: 0.
reg := operands at: 1.
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegInd RM: 5 RO: reg);
at: 3 put: (addressOperand bitAnd: 16rFF);
at: 4 put: (addressOperand >> 8 bitAnd: 16rFF);
at: 5 put: (addressOperand >> 16 bitAnd: 16rFF);
at: 6 put: (addressOperand >> 24 bitAnd: 16rFF).
^machineCodeSize := 7
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCMPXCHGMwrR [
<inline: true>
| srcReg offset destReg |
offset := operands at: 0.
srcReg := operands at: 1.
destReg := operands at: 2.
srcReg ~= ESP ifTrue:
[(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF).
^machineCodeSize := 4].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (offset bitAnd: 16rFF);
at: 4 put: (offset >> 8 bitAnd: 16rFF);
at: 5 put: (offset >> 16 bitAnd: 16rFF);
at: 6 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 7].
"ESP:"
(self isQuick: offset) ifTrue:
[machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp8 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rB1;
at: 2 put: (self mod: ModRegRegDisp32 RM: srcReg RO: destReg);
at: 3 put: (self s: SIB1 i: 4 b: srcReg);
at: 4 put: (offset bitAnd: 16rFF);
at: 5 put: (offset >> 8 bitAnd: 16rFF);
at: 6 put: (offset >> 16 bitAnd: 16rFF);
at: 7 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 8
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCPUID [
<inline: true>
machineCode
at: 0 put: 16r0F;
at: 1 put: 16rA2.
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCall [
"Will get inlined into concretizeAt: switch."
<inline: true>
| offset |
self assert: (operands at: 0) ~= 0.
offset := (operands at: 0) signedIntFromLong - (address + 5) signedIntFromLong.
machineCode
at: 0 put: 16rE8;
at: 1 put: (offset bitAnd: 16rFF);
at: 2 put: (offset >> 8 bitAnd: 16rFF);
at: 3 put: (offset >> 16 bitAnd: 16rFF);
at: 4 put: (offset >> 24 bitAnd: 16rFF).
^machineCodeSize := 5
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCallR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| reg |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
reg := operands at: 0.
machineCode
at: 0 put: 16rFF;
at: 1 put: (self mod: ModReg RM: reg RO: 2).
^machineCodeSize := 2
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpCqR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
(self isQuick: value) ifTrue:
[machineCode
at: 0 put: 16r83;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF).
^machineCodeSize := 3].
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpCwR [
"Will get inlined into concretizeAt: switch."
<inline: true>
| value reg |
value := operands at: 0.
reg := operands at: 1.
reg = EAX ifTrue:
[machineCode
at: 0 put: 16r3D;
at: 1 put: (value bitAnd: 16rFF);
at: 2 put: (value >> 8 bitAnd: 16rFF);
at: 3 put: (value >> 16 bitAnd: 16rFF);
at: 4 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 5].
machineCode
at: 0 put: 16r81;
at: 1 put: (self mod: ModReg RM: reg RO: 7);
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpRdRd [
"Will get inlined into concretizeAt: switch.
We use UCOMISD (see p 4-260 [2])"
<inline: true>
| regLHS regRHS |
"CmpRR RHS LHS computes LHS - RHS, i.e. apparently reversed. You have to think subtract."
regRHS := operands at: 0.
regLHS := operands at: 1.
machineCode
at: 0 put: 16r66;
at: 1 put: 16r0F;
at: 2 put: 16r2E;
at: 3 put: (self mod: ModReg RM: regRHS RO: regLHS).
^machineCodeSize := 4
]
{ #category : #'generate machine code' }
CogIA32Compiler >> concretizeCmpRsRs [
"Will get inlined into concretizeAt: switch.
We use UCOMISS (see p 4-260 [2])"