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CogMIPSELCompiler.class.st
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CogMIPSELCompiler.class.st
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"
Implemenation for 32-bit, little-endian MIPS running with the OABI (Debian port name 'mipsel').
Status: incomplete, no work planned
In December 2015, this implementation was complete enough to run the Newspeak test suite under the simulator. The compiled VM, however, failed at startup. The author suspects that some variables are lacking correct type annotations, being translated by Slang as unsigned when they should be signed or vice versa, causing some shift or comparison to have the wrong signness in C, but it may well be some other discrepancy between the behavior of Slang code when run in Smalltalk and when translated to C.
This implementation also does not provide instructions for working with floating point numbers, instead falling back to the interpreter's implementation for all floating point operations.
"
Class {
#name : #CogMIPSELCompiler,
#superclass : #CogAbstractInstruction,
#classVars : [
'AddCheckOverflowCqR',
'AddCheckOverflowRR',
'BrEqualRR',
'BrLongEqualRR',
'BrLongNotEqualRR',
'BrNotEqualRR',
'BrSignedGreaterEqualRR',
'BrSignedGreaterRR',
'BrSignedLessEqualRR',
'BrSignedLessRR',
'BrUnsignedGreaterEqualRR',
'BrUnsignedGreaterRR',
'BrUnsignedLessEqualRR',
'BrUnsignedLessRR',
'BranchTemp',
'Cmp',
'ConcreteVarBaseReg',
'DivRR',
'MoveHighR',
'MoveLowR',
'MulCheckOverflowRR',
'MulRR',
'Overflow',
'OverflowTemp1',
'OverflowTemp2',
'SubCheckOverflowCqR',
'SubCheckOverflowRR',
'TargetReg'
],
#pools : [
'MIPSConstants'
],
#category : #'VMMaker-JIT'
}
{ #category : #'class initialization' }
CogMIPSELCompiler class >> ISA [
^#MIPSEL
]
{ #category : #translation }
CogMIPSELCompiler class >> declareCVarsIn: aCCodeGenerator [
super declareCVarsIn: aCCodeGenerator.
aCCodeGenerator addHeaderFile: '<asm/cachectl.h>'. "For cacheflush"
]
{ #category : #translation }
CogMIPSELCompiler class >> identifyingPredefinedMacros [
^#('__MIPSEL__')
]
{ #category : #'class initialization' }
CogMIPSELCompiler class >> initialize [
"CogRTLOpcodes initialize. CogMIPSELCompiler initialize"
super initialize.
ConcreteVarBaseReg := S6.
Cmp := T0.
Overflow := T0.
OverflowTemp1 := T1.
OverflowTemp2 := T2.
"Can't use AT, Cmp or Overflow because we may need to preserve them for sequences like
CmpCwR
JumpZero
JumpBelow"
BranchTemp := T3.
"OABI position independent code expects T9 to have its entry point on entry?"
self flag: #OABI.
TargetReg := T9.
"Specific instructions"
self initializeSpecificOpcodes: #(
MulRR
DivRR
MoveLowR
MoveHighR
AddCheckOverflowCqR
AddCheckOverflowRR
MulCheckOverflowRR
SubCheckOverflowCqR
SubCheckOverflowRR
BrEqualRR
BrNotEqualRR
BrUnsignedLessRR
BrUnsignedLessEqualRR
BrUnsignedGreaterRR
BrUnsignedGreaterEqualRR
BrSignedLessRR
BrSignedLessEqualRR
BrSignedGreaterRR
BrSignedGreaterEqualRR
BrLongEqualRR
BrLongNotEqualRR)
in: thisContext method
]
{ #category : #'class initialization' }
CogMIPSELCompiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"See MIPSConstants>>initializeRegisters for a description of the C ABI."
"Note we can fit all of the abstract registers in C preserved registers, and
not need to save or restore them at runtime calls."
super initializeAbstractRegisters.
self flag: #OABI.
CallerSavedRegisterMask := self
registerMaskFor: T0 and: T1 and: T2 and: T3
and: T4 and: T5 and: T6 and: T7 and: T8 and: T9.
ReceiverResultReg := S0.
Arg0Reg := S1.
Arg1Reg := S2.
ClassReg := S3.
SendNumArgsReg := S4.
TempReg := S5.
VarBaseReg := S6. "Must be callee saved"
SPReg := SP.
FPReg := FP.
RISCTempReg := AT.
LinkReg := RA.
NumRegisters := 32.
self flag: #todo.
"Extra0Reg := ??.
Extra1Reg := ??.
Extra2Reg := ??.
Extra3Reg := ??.
Extra4Reg := ??.
Extra5Reg := ??.
Extra6Reg := ??.
Extra7Reg := ??."
self flag: #todo.
"DPFPReg0 := ??.
DPFPReg1 := ??.
DPFPReg2 := ??.
DPFPReg3 := ??.
DPFPReg4 := ??.
DPFPReg5 := ??.
DPFPReg6 := ??.
DPFPReg7 := ??.
DPFPReg8 := ??.
DPFPReg9 := ??.
DPFPReg10 := ??.
DPFPReg11 := ??.
DPFPReg12 := ??.
DPFPReg13 := ??.
DPFPReg14 := ??.
DPFPReg15 := ??"
]
{ #category : #translation }
CogMIPSELCompiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array.
MPIS instructions are 32-bits in length."
^{#'unsigned int'. '[', self basicNew machineCodeWords printString, ']'}
]
{ #category : #'debug printing' }
CogMIPSELCompiler class >> printFormatForOpcodeName: opcodeName [
"Answer a sequence of $r, $f or nil for the operands in the opcode, used for printing, where
r => integer register, f => floating point register, and nil => numeric or address operand.
Subclasses can override to provide a format string for their own private opcodes."
^(opcodeName startsWith: 'Br') ifTrue: [' rr'] ifFalse: [#()]
]
{ #category : #translation }
CogMIPSELCompiler class >> wordSize [
"This is a 32-bit ISA"
^4
]
{ #category : #'encoding - arithmetic' }
CogMIPSELCompiler >> addiuR: destReg R: srcReg C: imm [
^self itype: ADDIU rs: srcReg rt: destReg signedImmediate: imm
]
{ #category : #'encoding - arithmetic' }
CogMIPSELCompiler >> adduR: destReg R: leftReg R: rightReg [
^self rtype: SPECIAL rs: leftReg rt: rightReg rd: destReg sa: 0 funct: ADDU
]
{ #category : #'encoding - arithmetic' }
CogMIPSELCompiler >> andR: destReg R: leftReg R: rightReg [
^self rtype: SPECIAL rs: leftReg rt: rightReg rd: destReg sa: 0 funct: AND
]
{ #category : #'encoding - arithmetic' }
CogMIPSELCompiler >> andiR: destReg R: srcReg C: imm [
^self itype: ANDI rs: srcReg rt: destReg eitherImmediate: imm
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> beqR: leftReg R: rightReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: BEQ rs: leftReg rt: rightReg signedImmediate: offset >>> 2
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> bgezR: cmpReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: REGIMM rs: cmpReg rt: BGEZ signedImmediate: offset >>> 2
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> bgtzR: cmpReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: BGTZ rs: cmpReg rt: 0 signedImmediate: offset >>> 2
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> blezR: cmpReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: BLEZ rs: cmpReg rt: 0 signedImmediate: offset >>> 2
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> bltzR: cmpReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: REGIMM rs: cmpReg rt: BLTZ signedImmediate: offset >>> 2
]
{ #category : #'encoding - control' }
CogMIPSELCompiler >> bneR: leftReg R: rightReg offset: offset [
self assert: (offset bitAnd: 3) = 0.
self assert: (offset between: -16r20000 and: 16r1FFFF).
^self itype: BNE rs: leftReg rt: rightReg signedImmediate: offset >>> 2
]
{ #category : #'generate machine code' }
CogMIPSELCompiler >> cResultRegister [
"Answer the register through which C funcitons return integral results."
<inline: true>
^V0
]
{ #category : #accessing }
CogMIPSELCompiler >> callInstructionByteSize [
self flag: #todo. "Which call opcode does this want the size of?"
^16
]
{ #category : #'inline cacheing' }
CogMIPSELCompiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"csra - 16: lui t9, high
csra - 12: ori t9, low
csra - 8: jalr t9
csra - 4: nop (delay slot)"
self assert: (self opcodeAtAddress: callSiteReturnAddress - 16) == LUI.
self assert: (self opcodeAtAddress: callSiteReturnAddress - 12) == ORI.
self assert: (self opcodeAtAddress: callSiteReturnAddress - 8) == SPECIAL.
self assert: (self functionAtAddress: callSiteReturnAddress - 8) == JALR.
self assert: (objectMemory longAt: callSiteReturnAddress - 4) == self nop. "Delay slot"
^self literalAtAddress: callSiteReturnAddress - 12
]
{ #category : #testing }
CogMIPSELCompiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogMIPSELCompiler >> canMulRR [
^true
]
{ #category : #accessing }
CogMIPSELCompiler >> cmpC32RTempByteSize [
^8
]
{ #category : #accessing }
CogMIPSELCompiler >> codeGranularity [
"Answer the size in bytes of a unit of machine code."
<inline: true>
^4
]
{ #category : #'generate machine code' }
CogMIPSELCompiler >> computeMaximumSize [
"Each MIPS instruction has 4 bytes. Many abstract opcodes need more than one
instruction. Instructions that refer to constants and/or literals depend on literals
being stored in-line or out-of-line.
N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode
caseOf: {
[BrEqualRR] -> [^8].
[BrNotEqualRR] -> [^8].
[BrUnsignedLessRR] -> [^12].
[BrUnsignedLessEqualRR] -> [^12].
[BrUnsignedGreaterRR] -> [^12].
[BrUnsignedGreaterEqualRR] -> [^12].
[BrSignedLessRR] -> [^12].
[BrSignedLessEqualRR] -> [^12].
[BrSignedGreaterRR] -> [^12].
[BrSignedGreaterEqualRR] -> [^12].
[BrLongEqualRR] -> [^16].
[BrLongNotEqualRR] -> [^16].
[MulRR] -> [^4].
[DivRR] -> [^4].
[MoveLowR] -> [^4].
[MoveHighR] -> [^4].
"Noops & Pseudo Ops"
[Label] -> [^0].
[Literal] -> [^4].
[AlignmentNops] -> [^(operands at: 0) - 4].
[Fill32] -> [^4].
[Nop] -> [^4].
"Control"
[Call] -> [^self literalLoadInstructionBytes + 8].
[CallFull] -> [^self literalLoadInstructionBytes + 8].
[JumpR] -> [^8].
[Jump] -> [^8].
[JumpFull] -> [^self literalLoadInstructionBytes + 8].
[JumpLong] -> [^self literalLoadInstructionBytes + 8].
[JumpZero] -> [^8].
[JumpNonZero] -> [^8].
[JumpNegative] -> [^8].
[JumpNonNegative] -> [^8].
[JumpOverflow] -> [^8].
[JumpNoOverflow] -> [^8].
[JumpCarry] -> [^8].
[JumpNoCarry] -> [^8].
[JumpLess] -> [^8].
[JumpGreaterOrEqual] -> [^8].
[JumpGreater] -> [^8].
[JumpLessOrEqual] -> [^8].
[JumpBelow] -> [^8].
[JumpAboveOrEqual] -> [^8].
[JumpAbove] -> [^8].
[JumpBelowOrEqual] -> [^8].
[JumpLongZero] -> [^self literalLoadInstructionBytes + 8].
[JumpLongNonZero] -> [^self literalLoadInstructionBytes + 8].
[JumpFPEqual] -> [^8].
[JumpFPNotEqual] -> [^8].
[JumpFPLess] -> [^8].
[JumpFPGreaterOrEqual]-> [^8].
[JumpFPGreater] -> [^8].
[JumpFPLessOrEqual] -> [^8].
[JumpFPOrdered] -> [^8].
[JumpFPUnordered] -> [^8].
[RetN] -> [^8].
[Stop] -> [^4].
"Arithmetic"
[AddCqR] -> [^12].
[AndCqR] -> [^16].
[AndCqRR] -> [^12].
[CmpCqR] -> [^28].
[OrCqR] -> [^12].
[SubCqR] -> [^12].
[TstCqR] -> [^12].
[XorCqR] -> [^12].
[AddCwR] -> [^12].
[AndCwR] -> [^12].
[CmpCwR] -> [^28].
[OrCwR] -> [^12].
[SubCwR] -> [^12].
[XorCwR] -> [^12].
[AddRR] -> [^4].
[AndRR] -> [^4].
[CmpRR] -> [^20].
[OrRR] -> [^4].
[XorRR] -> [^4].
[SubRR] -> [^4].
[NegateR] -> [^4].
[LoadEffectiveAddressMwrR] -> [^12].
[LogicalShiftLeftCqR] -> [^4].
[LogicalShiftRightCqR] -> [^4].
[ArithmeticShiftRightCqR] -> [^4].
[LogicalShiftLeftRR] -> [^4].
[LogicalShiftRightRR] -> [^4].
[ArithmeticShiftRightRR] -> [^4].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
[AddCheckOverflowCqR] -> [^28].
[AddCheckOverflowRR] -> [^20].
[SubCheckOverflowCqR] -> [^28].
[SubCheckOverflowRR] -> [^20].
[MulCheckOverflowRR] -> [^20].
"Data Movement"
[MoveCqR] -> [^8 "or 4"].
[MoveCwR] -> [^8].
[MoveRR] -> [^4].
[MoveRdRd] -> [^4].
[MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [4]
ifFalse: [self literalLoadInstructionBytes + 4]].
[MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [self literalLoadInstructionBytes + 4]].
[MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [4]
ifFalse: [self literalLoadInstructionBytes + 4]].
[MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [4]
ifFalse: [self literalLoadInstructionBytes + 4]].
[MoveRMwr] -> [^16].
[MoveRdM64r] -> [^self literalLoadInstructionBytes + 4].
[MoveMbrR] -> [^4].
[MoveRMbr] -> [^4].
[MoveM16rR] -> [^4].
[MoveRM16r] -> [^4].
[MoveM64rRd] -> [^self literalLoadInstructionBytes + 4].
[MoveMwrR] -> [^16].
[MoveXbrRR] -> [^8].
[MoveRXbrR] -> [^8].
[MoveXwrRR] -> [^12].
[MoveRXwrR] -> [^12].
[PopR] -> [^8].
[PushR] -> [^8].
[PushCw] -> [^16].
[PushCq] -> [^16].
[PrefetchAw] -> [^12].
"Conversion"
[ConvertRRd] -> [^8].
}.
^0 "to keep C compiler quiet"
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAddCheckOverflowCqR [
| destReg leftReg rightImm |
rightImm := operands at: 0.
destReg := leftReg := operands at: 1.
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
"Save original LHS"
self machineCodeAt: 8 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual addition"
self machineCodeAt: 12 put: (self adduR: destReg R: leftReg R: AT).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 16 put: (self xorR: OverflowTemp2 R: destReg R: AT).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 20 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 24 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 28
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAddCheckOverflowRR [
| destReg leftReg rightReg |
rightReg := operands at: 0.
destReg := leftReg := operands at: 1.
"Save original LHS"
self machineCodeAt: 0 put: (self adduR: OverflowTemp1 R: leftReg R: ZR).
"The actual addition"
self machineCodeAt: 4 put: (self adduR: destReg R: leftReg R: rightReg).
"Set sign bit of OverflowTemp2 if sign of result differs from sign of RHS."
self machineCodeAt: 8 put: (self xorR: OverflowTemp2 R: destReg R: rightReg).
"Set sign bit of OverflowTemp1 if sign of result differs from sign of LHS."
self machineCodeAt: 12 put: (self xorR: OverflowTemp1 R: destReg R: OverflowTemp1).
"Set sign bit of Overflow if sign of result differs from both LHS and RHS, which indicates overflow."
self machineCodeAt: 16 put: (self andR: Overflow R: OverflowTemp1 R: OverflowTemp2).
^machineCodeSize := 20
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAddCqR [
| destReg leftReg rightImm |
rightImm := operands at: 0.
destReg := leftReg := operands at: 1.
(rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAddCwR].
self machineCodeAt: 0 put: (self addiuR: destReg R: leftReg C: rightImm).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAddCwR [
| destReg leftReg rightImm |
rightImm := operands at: 0.
destReg := leftReg := operands at: 1.
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self adduR: destReg R: leftReg R: AT).
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAddRR [
| destReg leftReg rightReg |
rightReg := operands at: 0.
destReg := leftReg := operands at: 1.
self machineCodeAt: 0 put: (self adduR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAlignmentNops [
self assert: machineCodeSize \\ 4 = 0.
0 to: machineCodeSize - 1 by: 4 do:
[:p | self machineCodeAt: p put: self nop]
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAndCqR [
| destReg leftReg rightImm |
rightImm := operands at: 0.
destReg := leftReg := operands at: 1.
(rightImm between: -16r8000 and: 16r7FFF) ifFalse: [^self concretizeAndCwR].
self machineCodeAt: 0 put: (self andiR: destReg R: leftReg C: rightImm).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAndCqRR [
| value srcReg dstReg |
value := operands at: 0.
srcReg := operands at: 1.
dstReg := operands at: 2.
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: value)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: value)).
self machineCodeAt: 8 put: (self andR: dstReg R: srcReg R: AT).
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAndCwR [
| destReg leftReg rightImm |
rightImm := operands at: 0.
destReg := leftReg := operands at: 1.
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: rightImm)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: rightImm)).
self machineCodeAt: 8 put: (self andR: destReg R: leftReg R: AT).
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeAndRR [
| destReg leftReg rightReg |
rightReg := operands at: 0.
destReg := leftReg := operands at: 1.
self machineCodeAt: 0 put: (self andR: destReg R: leftReg R: rightReg).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeArithmeticShiftRightCqR [
| distance reg |
distance := (operands at: 0) min: 31.
reg := operands at: 1.
self machineCodeAt: 0 put: (self sraR: reg R: reg C: distance).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeArithmeticShiftRightRR [
| destReg distReg |
distReg := operands at: 0.
destReg := operands at: 1.
self machineCodeAt: 0 put: (self sravR: destReg R: destReg R: distReg).
^machineCodeSize := 4
]
{ #category : #'generate machine code' }
CogMIPSELCompiler >> concretizeAt: actualAddress [
"Generate concrete machine code for the instruction at actualAddress,
setting machineCodeSize, and answer the following address."
self assert: actualAddress \\ 4 = 0.
^super concretizeAt: actualAddress
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 4.
leftReg := operands at: 1.
rightReg := operands at: 2.
self machineCodeAt: 0 put: (self beqR: leftReg R: rightReg offset: offset).
self machineCodeAt: 4 put: (self nop). "Delay slot"
^machineCodeSize := 8
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrLongEqualRR [
| jumpTargetInstruction jumpTargetAddr leftReg rightReg |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
self flag: #todo. "Check not crossing 256MB block."
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF.
leftReg := operands at: 1.
rightReg := operands at: 2.
self machineCodeAt: 0 put: (self bneR: leftReg R: rightReg offset: 12).
self machineCodeAt: 4 put: (self nop). "Delay slot"
self machineCodeAt: 8 put: (self jA: jumpTargetAddr).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrLongNotEqualRR [
| jumpTargetInstruction jumpTargetAddr leftReg rightReg |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
self flag: #todo. "Check not crossing 256MB block."
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger bitAnd: 16rFFFFFFF.
leftReg := operands at: 1.
rightReg := operands at: 2.
self machineCodeAt: 0 put: (self beqR: leftReg R: rightReg offset: 12).
self machineCodeAt: 4 put: (self nop). "Delay slot"
self machineCodeAt: 8 put: (self jA: jumpTargetAddr).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrNotEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 4.
leftReg := operands at: 1.
rightReg := operands at: 2.
self machineCodeAt: 0 put: (self bneR: leftReg R: rightReg offset: offset).
self machineCodeAt: 4 put: (self nop). "Delay slot"
^machineCodeSize := 8
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrSignedGreaterEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrSignedGreaterRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrSignedLessEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrSignedLessRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrUnsignedGreaterEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrUnsignedGreaterRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrUnsignedLessEqualRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: rightReg R: leftReg).
self machineCodeAt: 4 put: (self beqR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeBrUnsignedLessRR [
| offset leftReg rightReg |
offset := self computeJumpTargetOffsetPlus: 8. "Relative to delay slot"
leftReg := operands at: 1.
rightReg := operands at: 2.
self assert: leftReg ~= BranchTemp.
self assert: rightReg ~= BranchTemp.
self machineCodeAt: 0 put: (self sltuR: BranchTemp R: leftReg R: rightReg).
self machineCodeAt: 4 put: (self bneR: BranchTemp R: ZR offset: offset).
self machineCodeAt: 8 put: (self nop). "Delay slot"
^machineCodeSize := 12
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeCall [
"Call is used only for calls within code-space, See CallFull for general anywhere in address space calling"
"Relative branches in MIPS have a displacement of +/- 131kB (signed 18 bits), which is too small to cover
the method zone."
^self concretizeCallFull
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeCallFull [
| jumpTargetInstruction jumpTargetAddr |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger.
self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTargetAddr)).
self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTargetAddr)).
self machineCodeAt: 8 put: (self jalR: TargetReg).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeCmpCqR [
^self concretizeCmpCwR
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeCmpCwR [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeCmpRR [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeDivRR [
| dividendReg divisorReg |
dividendReg := operands at: 0.
divisorReg := operands at: 1.
self machineCodeAt: 0 put: (self divR: dividendReg R: divisorReg).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeFill32 [
"fill with operand 0 according to the processor's endianness.
You might think this is bogus and we should fill with stop instrurctions instead,
but this is used to leave room for a CMBlock header before the code for a block;
the gaps get filled in by fillInBlockHeadersAt: after code has been generated."
self machineCodeAt: 0 put: (operands at: 0).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJump [
| offset |
offset := self computeJumpTargetOffsetPlus: 4.
self flag: #BranchRange.
self machineCodeAt: 0 put: (self beqR: ZR R: ZR offset: offset).
self machineCodeAt: 4 put: self nop. "Delay slot"
^machineCodeSize := 8
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpFull [
| jumpTargetInstruction jumpTargetAddr |
<var: #jumpTargetInstruction type: #'AbstractInstruction *'>
jumpTargetInstruction := self longJumpTargetAddress.
jumpTargetAddr := jumpTargetInstruction asUnsignedInteger.
self machineCodeAt: 0 put: (self luiR: TargetReg C: (self high16BitsOf: jumpTargetAddr)).
self machineCodeAt: 4 put: (self oriR: TargetReg R: TargetReg C: (self low16BitsOf: jumpTargetAddr)).
self machineCodeAt: 8 put: (self jR: TargetReg).
self machineCodeAt: 12 put: self nop. "Delay slot"
^machineCodeSize := 16
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpLong [
^self concretizeJumpFull
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpLongNonZero [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpLongZero [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpNoOverflow [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpNonZero [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpOverflow [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpR [
| reg |
self flag: #OABI. "Does this ever target C code? If so we should move the target into TargetReg first."
reg := operands at: 0.
self machineCodeAt: 0 put: (self jR: reg).
self machineCodeAt: 4 put: self nop. "Delay slot"
^machineCodeSize := 8
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpSignedGreaterEqual [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpSignedGreaterThan [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpSignedLessEqual [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpSignedLessThan [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpUnsignedGreaterEqual [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpUnsignedGreaterThan [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpUnsignedLessEqual [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpUnsignedLessThan [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeJumpZero [
self unreachable. "Should have been rewritten by noteFollowingConditionalBranch:"
^0
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeLoadEffectiveAddressMwrR [
<var: #offset type: #sqInt>
| baseReg offset destReg |
offset := operands at: 0.
baseReg := operands at: 1.
destReg := operands at: 2.
(self isShortOffset: offset) ifTrue:
[self machineCodeAt: 0 put: (self addiuR: destReg R: baseReg C: offset).
^machineCodeSize := 4].
self machineCodeAt: 0 put: (self luiR: AT C: (self high16BitsOf: offset)).
self machineCodeAt: 4 put: (self oriR: AT R: AT C: (self low16BitsOf: offset)).
self machineCodeAt: 8 put: (self adduR: destReg R: baseReg R: AT).
^machineCodeSize := 12.
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeLogicalShiftLeftCqR [
| distance reg |
distance := (operands at: 0) min: 31.
reg := operands at: 1.
self machineCodeAt: 0 put: (self sllR: reg R: reg C: distance).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeLogicalShiftLeftRR [
| destReg distReg |
distReg := operands at: 0.
destReg := operands at: 1.
self machineCodeAt: 0 put: (self sllvR: destReg R: destReg R: distReg).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogMIPSELCompiler >> concretizeLogicalShiftRightCqR [
| distance reg |
distance := (operands at: 0) min: 31.