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CogX64Compiler.class.st
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CogX64Compiler.class.st
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"
I generate x64 (x86-64) instructions from CogAbstractInstructions. For reference see
1. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M
2. IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, N-Z
http://www.intel.com/products/processor/manuals/
or
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions
AMD64 Architecture Programmer's Manual Volume 4: 128-bit Media Instructions
AMD64 Architecture Programmer's Manual Volume 5: 64-bit Media and x87 Floating Point Instructions
http://developer.amd.com/resources/documentation-articles/developer-guides-manuals/
(® is supposed to be the Unicode ""registered sign"").
"
Class {
#name : #CogX64Compiler,
#superclass : #CogAbstractInstruction,
#classVars : [
'CDQ',
'CLD',
'CMPXCHGAwR',
'CMPXCHGMwrR',
'CPUID',
'IDIVR',
'IMULRR',
'LFENCE',
'LOCK',
'MFENCE',
'MOVSB',
'MOVSQ',
'ModReg',
'ModRegInd',
'ModRegIndDisp32',
'ModRegIndSIB',
'ModRegRegDisp32',
'ModRegRegDisp8',
'R10',
'R11',
'R12',
'R13',
'R14',
'R15',
'R8',
'R9',
'RAX',
'RBP',
'RBX',
'RCX',
'RDI',
'RDX',
'REP',
'RSI',
'RSP',
'SFENCE',
'SIB1',
'SIB2',
'SIB4',
'SIB8',
'SysV',
'XCHGAwR',
'XCHGMwrR',
'XCHGRR',
'XMM0L',
'XMM10L',
'XMM11L',
'XMM12L',
'XMM13L',
'XMM14L',
'XMM15L',
'XMM1L',
'XMM2L',
'XMM3L',
'XMM4L',
'XMM5L',
'XMM6L',
'XMM7L',
'XMM8L',
'XMM9L'
],
#category : #'VMMaker-JIT'
}
{ #category : #translation }
CogX64Compiler class >> ISA [
^#X64
]
{ #category : #accessing }
CogX64Compiler class >> VarBaseReg [
"Answer the number of the reg we use to hold the base address of CoInterpreter variables"
^RBX
]
{ #category : #translation }
CogX64Compiler class >> defaultCompilerClass [
^CogInLineLiteralsX64Compiler
]
{ #category : #translation }
CogX64Compiler class >> identifyingPredefinedMacros [
^#('x86_64' '__amd64' '__x86_64' '__amd64__' '__x86_64__' '_M_AMD64' '_M_X64')
]
{ #category : #translation }
CogX64Compiler class >> ifTranslateableAddWithOptionsTo: aCollection [
"Override to create cogitX64.c and cogitX64Win64.c"
(self wordSize = Cogit objectMemoryClass wordSize
and: [self identifyingPredefinedMacros notNil]) ifTrue:
[aCollection
"SysV must preceed _WIN64; see Cogit class>>#generateCodeStringForCogitDotC"
add: {self. {#ISA. self ISA. #ABI. #SysV}};
add: {self. {#ISA. self ISA. #ABI. #'_WIN64'}}]
]
{ #category : #'class initialization' }
CogX64Compiler class >> initialize [
"Initialize various x64 instruction-related constants.
[1] IA-32 Intel® Architecture Software Developer's Manual Volume 2A: Instruction Set Reference, A-M"
"CogX64Compiler initialize"
self ~~ CogX64Compiler ifTrue: [^self].
(self initializationOptions ifNil: [Dictionary new])
at: #ABI
ifPresent: [:abi| SysV := abi asUppercase ~= #WIN64 and: [abi asUppercase ~= #'_WIN64']]
ifAbsent: [SysV := true]. "Default ABI; set to true for SysV, false for WIN64/_WIN64"
RAX := 0.
RCX := 1. "Were they completely mad or simply sadistic?"
RDX := 2.
RBX := 3.
RSP := 4.
RBP := 5.
RSI := 6.
RDI := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12.
R13 := 13.
R14 := 14.
R15 := 15.
XMM0L := 0.
XMM1L := 1.
XMM2L := 2.
XMM3L := 3.
XMM4L := 4.
XMM5L := 5.
XMM6L := 6.
XMM7L := 7.
XMM8L := 8.
XMM9L := 9.
XMM10L := 10.
XMM11L := 11.
XMM12L := 12.
XMM13L := 13.
XMM14L := 14.
XMM15L := 15.
"Mod R/M Mod fields. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-2"
ModRegInd := 0.
ModRegIndSIB := 4.
ModRegIndDisp32 := 5.
ModRegRegDisp8 := 1.
ModRegRegDisp32 := 2.
ModReg := 3.
"SIB Scaled Index modes. See [1] Sec 2.4, 2.5 & 2.6 & Table 2-3"
SIB1 := 0.
SIB2 := 1.
SIB4 := 2.
SIB8 := 3.
"Specific instructions"
self
initializeSpecificOpcodes: #(CDQ IDIVR IMULRR CPUID LFENCE MFENCE SFENCE LOCK CMPXCHGAwR CMPXCHGMwrR XCHGAwR XCHGMwrR XCHGRR CLD REP MOVSB MOVSQ)
in: thisContext method
]
{ #category : #'class initialization' }
CogX64Compiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"[1] Figure 3.4 Register Usage in
System V Application Binary Interface
AMD64 Architecture Processor Supplement"
super initializeAbstractRegisters.
"N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for
receiver/result since these are written in all normal sends."
SysV
ifTrue: [self initializeAbstractRegistersSysV]
ifFalse: [self initializeAbstractRegistersWin64].
NumRegisters := 16.
DPFPReg0 := XMM0L.
DPFPReg1 := XMM1L.
DPFPReg2 := XMM2L.
DPFPReg3 := XMM3L.
DPFPReg4 := XMM4L.
DPFPReg5 := XMM5L.
DPFPReg6 := XMM6L.
DPFPReg7 := XMM7L.
DPFPReg8 := XMM8L.
DPFPReg9 := XMM9L.
DPFPReg10 := XMM10L.
DPFPReg11 := XMM11L.
DPFPReg12 := XMM12L.
DPFPReg13 := XMM13L.
DPFPReg14 := XMM14L.
DPFPReg15 := XMM15L.
NumFloatRegisters := 16.
VReg0 := XMM0L.
VReg1 := XMM1L.
VReg2 := XMM2L.
VReg3 := XMM3L.
VReg4 := XMM4L.
VReg5 := XMM5L.
VReg6 := XMM6L.
VReg7 := XMM7L.
]
{ #category : #'class initialization' }
CogX64Compiler class >> initializeAbstractRegistersSysV [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"[1] Figure 3.4 Register Usage in
System V Application Binary Interface
AMD64 Architecture Processor Supplement"
"N.B. RAX RCX & RDX are caller-save (scratch) registers. Hence we use RCX for class and RDX for
receiver/result since these are written in all normal sends."
CallerSavedRegisterMask := self
registerMaskFor: RAX
and: RCX
and: RDX
and: RSI
and: RDI
and: R8
and: R9
and: R10
and: R11.
TempReg := RAX.
ClassReg := RCX.
ReceiverResultReg := RDX.
SendNumArgsReg := R9.
SPReg := RSP.
FPReg := RBP.
Arg0Reg := RDI. "So as to agree with C ABI arg 0"
Arg1Reg := RSI. "So as to agree with C ABI arg 1"
VarBaseReg := RBX. "Must be callee saved"
"R8 is either RISCTempReg or Extra6Reg depending on subclass."
Extra0Reg := R10.
Extra1Reg := R11.
Extra2Reg := R12.
Extra3Reg := R13.
Extra4Reg := R14.
Extra5Reg := R15
]
{ #category : #'class initialization' }
CogX64Compiler class >> initializeAbstractRegistersWin64 [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
"N.B. Since receiver/result are written in all normal sends,
it's better to use scratch registers for them (those which are caller-saved).
In Win64 ABI, this does not let that many choices:
- RAX is TempReg (overwritten by result etc...)
- RCX and RDX are used for first 2 args (see genMarshallNArgs:arg:arg:arg:arg:)
- it remains R8,R9,R10 & R11 : we choose the first two"
CallerSavedRegisterMask := self
registerMaskFor: RAX
and: RCX
and: RDX
and: R8
and: R9
and: R10
and: R11.
TempReg := RAX.
ClassReg := R8.
ReceiverResultReg := R9.
SendNumArgsReg := R10.
SPReg := RSP.
FPReg := RBP.
Arg0Reg := RCX. "So as to agree with C ABI arg 0"
Arg1Reg := RDX. "So as to agree with C ABI arg 1"
VarBaseReg := RBX. "Must be callee saved"
"R11 is either RISCTempReg or Extra6Reg depending on subclass."
Extra0Reg := RDI.
Extra1Reg := RSI.
Extra2Reg := R12.
Extra3Reg := R13.
Extra4Reg := R14.
Extra5Reg := R15
]
{ #category : #testing }
CogX64Compiler class >> isAbstract [
^self == CogX64Compiler
]
{ #category : #accessing }
CogX64Compiler class >> isSysV [
"Answer true is ABI is SysV, false otherwise (for WIN64)"
^SysV
]
{ #category : #translation }
CogX64Compiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array."
^{#'unsigned char'. '[', self basicNew machineCodeBytes printString, ']'}
]
{ #category : #translation }
CogX64Compiler class >> moduleName [
"CogAbstractInstruction subclasses collect: [:ea| ea moduleName]"
^'cogit', self ISA, ((self initializationOptions at: #ABI ifAbsent: ['']) copyWithout: $_)
]
{ #category : #translation }
CogX64Compiler class >> wordSize [
"This is a 64-bit ISA"
^8
]
{ #category : #'register allocation' }
CogX64Compiler >> availableRegisterOrNoneFor: liveRegsMask [
"Answer an unused abstract register in the liveRegMask.
Subclasses with more registers can override to answer them.
N.B. Do /not/ allocate TempReg."
<returnTypeC: #sqInt>
(cogit register: Extra5Reg isInMask: liveRegsMask) ifFalse:
[^Extra5Reg].
(cogit register: Extra4Reg isInMask: liveRegsMask) ifFalse:
[^Extra4Reg].
(cogit register: Extra3Reg isInMask: liveRegsMask) ifFalse:
[^Extra3Reg].
(cogit register: Extra2Reg isInMask: liveRegsMask) ifFalse:
[^Extra2Reg].
(cogit register: Extra1Reg isInMask: liveRegsMask) ifFalse:
[^Extra1Reg].
(cogit register: Extra0Reg isInMask: liveRegsMask) ifFalse:
[^Extra0Reg].
^super availableRegisterOrNoneFor: liveRegsMask
]
{ #category : #abi }
CogX64Compiler >> cFloatResultToRd: reg [
XMM0L ~= reg ifTrue: [
cogit MoveRd: XMM0L Rd: reg
].
]
{ #category : #abi }
CogX64Compiler >> cFloatResultToRs: reg [
XMM0L ~= reg ifTrue: [
cogit MoveRs: XMM0L Rs: reg
].
]
{ #category : #accessing }
CogX64Compiler >> cResultRegister [
"Answer the register through which C functions return integral results."
<inline: true>
^RAX
]
{ #category : #accessing }
CogX64Compiler >> cResultRegisterHigh [
"Answer the register through which C functions return the high part of big integral results."
<inline: true>
^ RDX
]
{ #category : #accessing }
CogX64Compiler >> cStackPointer [
^ RSP
]
{ #category : #'full transfer run-time support' }
CogX64Compiler >> callFullTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the full call immediately preceding callSiteReturnAddress will jump to."
^self sixtyFourBitLiteralBefore: callSiteReturnAddress - 2
]
{ #category : #accessing }
CogX64Compiler >> callInstructionByteSize [
^5
]
{ #category : #'inline cacheing' }
CogX64Compiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address the call immediately preceding callSiteReturnAddress will jump to."
| callDistance |
callDistance := self literal32BeforeFollowingAddress: callSiteReturnAddress.
^callSiteReturnAddress + callDistance signedIntFromLong
]
{ #category : #testing }
CogX64Compiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogX64Compiler >> canMulRR [
^true
]
{ #category : #testing }
CogX64Compiler >> canSignExtend [
"x64 has native SignExtend8RR, SignExtend16RR, & SignExtend32RR."
<inline: true>
^true
]
{ #category : #testing }
CogX64Compiler >> canZeroExtend [
"x64 has native ZeroExtend8RR, ZeroExtend16RR, & ZeroExtend32RR."
<inline: true>
^true
]
{ #category : #accessing }
CogX64Compiler >> cmpC32RTempByteSize [
^5
]
{ #category : #accessing }
CogX64Compiler >> codeGranularity [
^1
]
{ #category : #'generate machine code' }
CogX64Compiler >> computeMaximumSize [
"Compute the maximum size for each opcode. This allows jump offsets to
be determined, provided that all backward branches are long branches."
"N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[AlignmentNops] -> [^(operands at: 0) - 1].
[Fill32] -> [^4].
[Nop] -> [^1].
"Specific Control/Data Movement"
[CDQ] -> [^2].
[IDIVR] -> [^3].
[IMULRR] -> [^4].
[CPUID] -> [^2].
[CMPXCHGAwR] -> [^8].
[CMPXCHGMwrR] -> [^9].
[LFENCE] -> [^3].
[MFENCE] -> [^3].
[SFENCE] -> [^3].
[LOCK] -> [^1].
[XCHGAwR] -> [^6].
[XCHGMwrR] -> [^7].
[XCHGRR] -> [^((operands at: 0) = RAX
or: [(operands at: 1) = RAX])
ifTrue: [2]
ifFalse: [3]].
[REP] -> [^1].
[CLD] -> [^1].
[MOVSB] -> [^1].
[MOVSQ] -> [^2].
"Control"
[CallFull] -> [^12].
[Call] -> [^5].
[CallR] -> [^3].
[JumpR] -> [^3].
[JumpFull] -> [self resolveJumpTarget. ^12].
[JumpLong] -> [self resolveJumpTarget. ^5].
[Jump] -> [self resolveJumpTarget. ^5].
[JumpZero] -> [self resolveJumpTarget. ^6].
[JumpNonZero] -> [self resolveJumpTarget. ^6].
[JumpNegative] -> [self resolveJumpTarget. ^6].
[JumpNonNegative] -> [self resolveJumpTarget. ^6].
[JumpOverflow] -> [self resolveJumpTarget. ^6].
[JumpNoOverflow] -> [self resolveJumpTarget. ^6].
[JumpCarry] -> [self resolveJumpTarget. ^6].
[JumpNoCarry] -> [self resolveJumpTarget. ^6].
[JumpLess] -> [self resolveJumpTarget. ^6].
[JumpGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpGreater] -> [self resolveJumpTarget. ^6].
[JumpLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpBelow] -> [self resolveJumpTarget. ^6].
[JumpAboveOrEqual] -> [self resolveJumpTarget. ^6].
[JumpAbove] -> [self resolveJumpTarget. ^6].
[JumpBelowOrEqual] -> [self resolveJumpTarget. ^6].
[JumpLongZero] -> [self resolveJumpTarget. ^6].
[JumpLongNonZero] -> [self resolveJumpTarget. ^6].
[JumpFPEqual] -> [self resolveJumpTarget. ^6].
[JumpFPNotEqual] -> [self resolveJumpTarget. ^6].
[JumpFPLess] -> [self resolveJumpTarget. ^6].
[JumpFPGreaterOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPGreater] -> [self resolveJumpTarget. ^6].
[JumpFPLessOrEqual] -> [self resolveJumpTarget. ^6].
[JumpFPOrdered] -> [self resolveJumpTarget. ^6].
[JumpFPUnordered] -> [self resolveJumpTarget. ^6].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [1] ifFalse: [3]].
[Stop] -> [^1].
"Arithmetic"
[AddCqR] -> [^self computeSizeOfArithCqR].
[AddcCqR] -> [^self computeSizeOfArithCqR].
[AndCqR] -> [^self computeSizeOfArithCqR].
[CmpCqR] -> [^self computeSizeOfArithCqR].
[OrCqR] -> [^self computeSizeOfArithCqR].
[SubCqR] -> [^self computeSizeOfArithCqR].
[SubbCqR] -> [^self computeSizeOfArithCqR].
[TstCqR] -> [^self computeSizeOfArithCqR].
[AddCwR] -> [^self computeSizeOfArithCwR].
[AndCwR] -> [^self computeSizeOfArithCwR].
[CmpCwR] -> [^self computeSizeOfArithCwR].
[CmpC32R] -> [^(operands at: 1) <= 7
ifTrue: [(operands at: 1) = RAX
ifTrue: [5]
ifFalse: [6]]
ifFalse: [7]].
[OrCwR] -> [^self computeSizeOfArithCwR].
[SubCwR] -> [^self computeSizeOfArithCwR].
[XorCwR] -> [^self computeSizeOfArithCwR].
[AddRR] -> [^3].
[AddcRR] -> [^3].
[AndRR] -> [^3].
[CmpRR] -> [^3].
[OrRR] -> [^3].
[XorRR] -> [^3].
[SubRR] -> [^3].
[SubbRR] -> [^3].
[NegateR] -> [^3].
[LoadEffectiveAddressMwrR]
-> [^((self isQuick: (operands at: 0))
ifTrue: [4]
ifFalse: [7])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[LogicalShiftLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]].
[LogicalShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]].
[ArithmeticShiftRightCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]].
[RotateRightCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]].
[RotateLeftCqR] -> [^(operands at: 0) = 1 ifTrue: [3] ifFalse: [4]].
[LogicalShiftLeftRR] -> [^self computeShiftRRSize].
[LogicalShiftRightRR] -> [^self computeShiftRRSize].
[ArithmeticShiftRightRR] -> [^self computeShiftRRSize].
[AddRdRd] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[CmpRdRd] -> [^ 4
+ ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[SubRdRd] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MulRdRd] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[DivRdRd] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[SqrtRd] -> [^ 4 + (((operands at: 0) > 7)
ifTrue: [1]
ifFalse: [0])].
[XorRdRd] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[AddRsRs] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[CmpRsRs] -> [^ 3 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[SubRsRs] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MulRsRs] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[DivRsRs] -> [^ 4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[SqrtRs] -> [^ 4 + (((operands at: 0) > 7)
ifTrue: [1]
ifFalse: [0])].
[XorRsRs] -> [^ 3 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
"Data Movement"
[MoveCqR] -> [^(operands at: 0) = 0
ifTrue: [3]
ifFalse:
[(self is32BitSignedImmediate: (operands at: 0))
ifTrue: [7]
ifFalse: [self moveCwRByteSize - 1]]].
[MoveCwR] -> [^(self inCurrentCompilation: (operands at: 0))
ifTrue: [7]
ifFalse: [self moveCwRByteSize]].
[MoveC32R] -> [^7]. "N.B. Always inlined."
[MoveRR] -> [^3].
[MoveRdRd] -> [^4
+((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveRsRs] -> [^4
+ ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveRRd] -> [^5].
[MoveRdR] -> [^5].
[MoveAwR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [7]
ifFalse: [(operands at: 1) = RAX ifTrue: [10] ifFalse: [14]]].
[MoveA32R] -> [^(operands at: 1) = RAX ifTrue: [9] ifFalse: [13]].
[MoveRAw] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [7]
ifFalse: [(operands at: 0) = RAX ifTrue: [10] ifFalse: [14]]].
[MoveRA32] -> [^(operands at: 0) = RAX ifTrue: [9] ifFalse: [13]].
[MoveAbR] -> [^(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [7]
ifFalse: [(operands at: 1) = RAX ifTrue: [10] ifFalse: [14]]].
[MoveRAb] -> [^(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [7]
ifFalse: [(operands at: 0) = RAX ifTrue: [10] ifFalse: [14]]].
[MoveRMwr] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)).
^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 2) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 2) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveRM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 2) bitAnd: 6) ~= RSP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((((operands at: 2) bitAnd: 7) = RSP and: [(operands at: 1) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 2) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveRsM32r] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 2) bitAnd: 6) ~= RSP])
ifTrue: [4]
ifFalse: [5]]
ifFalse: [8])
+ ((((operands at: 2) bitAnd: 7) = RSP and: [(operands at: 1) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 2) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveRdM64r] -> [^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 2) bitAnd: 6) ~= RSP])
ifTrue: [4]
ifFalse: [5]]
ifFalse: [8])
+ ((((operands at: 2) bitAnd: 7) = RSP and: [(operands at: 1) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 2) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveMbrR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)).
^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveRMbr] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)).
^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 0) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 2) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveM8rR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)).
^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveMs8rR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)).
^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveRM8r] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)).
^((self isQuick: (operands at: 1))
ifTrue: [((operands at: 1) = 0
and: [((operands at: 0) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 2) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveM16rR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)).
^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 7) ~= RBP])
ifTrue: [4]
ifFalse: [5]]
ifFalse: [8])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveRM16r] -> [self assert: (self is32BitSignedImmediate: (operands at: 1)).
^((self isQuick: (operands at: 1))
ifTrue: [4]
ifFalse: [7])
+ (((operands at: 2) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])
+ (((operands at: 0) > 7 or: [(operands at: 2) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveM32rR] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 6) ~= RSP])
ifTrue: [2]
ifFalse: [3]]
ifFalse: [6])
+ ((((operands at: 1) bitAnd: 7) = RSP and: [(operands at: 0) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 1) > 7) or: [(operands at: 2) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveM32rRs] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 6) ~= RSP])
ifTrue: [4]
ifFalse: [5]]
ifFalse: [8])
+ ((((operands at: 1) bitAnd: 7) = RSP and: [(operands at: 0) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 1) > 7) or: [(operands at: 2) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveM64rRd] -> [^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 6) ~= RSP])
ifTrue: [4]
ifFalse: [5]]
ifFalse: [8])
+ ((((operands at: 1) bitAnd: 7) = RSP and: [(operands at: 0) ~= 0])
ifTrue: [1]
ifFalse: [0])
+ ((((operands at: 1) > 7) or: [(operands at: 2) > 7])
ifTrue: [1]
ifFalse: [0])].
[MoveMwrR] -> [self assert: (self is32BitSignedImmediate: (operands at: 0)).
^((self isQuick: (operands at: 0))
ifTrue: [((operands at: 0) = 0
and: [((operands at: 1) bitAnd: 7) ~= RBP])
ifTrue: [3]
ifFalse: [4]]
ifFalse: [7])
+ (((operands at: 1) bitAnd: 7) = RSP
ifTrue: [1]
ifFalse: [0])].
[MoveXbrRR] -> [self assert: (operands at: 0) ~= RSP.
^((operands at: 1) bitAnd: 7) = RBP
ifTrue: [5]
ifFalse: [4]].
[MoveRXbrR] -> [self assert: (operands at: 1) ~= RSP.
^(((operands at: 0) > 3
or: [(operands at: 1) > 7
or: [(operands at: 2) > 7]])
ifTrue: [4]
ifFalse: [3])
+ (((operands at: 2) bitAnd: 7) = RBP
ifTrue: [1]
ifFalse: [0])].
[MoveXwrRR] -> [self assert: (operands at: 0) ~= RSP.
^((operands at: 1) = RBP
or: [(operands at: 1) = R13])
ifTrue: [5]
ifFalse: [4]].
[MoveRXwrR] -> [self assert: (operands at: 1) ~= RSP.
^((operands at: 2) = RBP
or: [(operands at: 2) = R13])
ifTrue: [5]
ifFalse: [4]].
[MoveX32rRR] -> [self assert: (operands at: 0) ~= RSP.
^(((operands at: 1) = RBP
or: [(operands at: 1) = R13])
ifTrue: [7]
ifFalse: [6])
+ (((operands at: 0) > 7
or: [(operands at: 1) > 7
or: [(operands at: 2) > 7]])
ifTrue: [1]
ifFalse: [0])].
[MoveRX32rR] -> [self assert: (operands at: 1) ~= RSP.
^(((operands at: 2) = RBP
or: [(operands at: 2) = R13])
ifTrue: [4]
ifFalse: [3])
+ (((operands at: 0) > 7
or: [(operands at: 1) > 7
or: [(operands at: 2) > 7]])
ifTrue: [1]
ifFalse: [0])].
[PopR] -> [^(operands at: 0) < 8 ifTrue: [1] ifFalse: [2]].
[PushR] -> [^(operands at: 0) < 8 ifTrue: [1] ifFalse: [2]].
[PushCq] -> [^(self isQuick: (operands at: 0))
ifTrue: [2]
ifFalse:
[(self is32BitSignedImmediate: (operands at: 0))
ifTrue: [5]
ifFalse: [self computeSizeOfPushCw]]].
[PushCw] -> [^self computeSizeOfPushCw].
[PrefetchAw] -> [^(self isAddressRelativeToVarBase: (operands at: 0)) ifTrue: [7] ifFalse: [0]].
"Conversion"
[ConvertRRd] -> [^5].
[ConvertRdR] -> [^5].
[ConvertRRs] -> [^4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[ConvertRsR] -> [^4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[ConvertRsRd] -> [^4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[ConvertRdRs] -> [^4 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
[SignExtend8RR] -> [^4].
[SignExtend16RR] -> [^4].
[SignExtend32RR] -> [^4].
[ZeroExtend8RR] -> [^4].
[ZeroExtend16RR] -> [^4].
[ZeroExtend32RR] -> [^2 + ((((operands at: 1) > 7) or: [(operands at: 0) > 7])
ifTrue: [1]
ifFalse: [0])].
"This is a fixed size instruction using a patcheable literal. This takes ALWAYS 7 bytes"
[MovePatcheableC32R] -> [ ^ 7 ].
"SIMD instructions"
[DupRVr] -> [^9].
[St1VrRMw] -> [^9].
[Ld1VrRMw] -> [^9].
[AlignedSt1VrRMw ] -> [ ^9 ].
[FaddSRvRvRv] -> [ ^10 ].
[FsubSRvRvRv] -> [ ^10 ].
}.
^0 "to keep C compiler quiet"
]
{ #category : #'generate machine code' }
CogX64Compiler >> computeShiftRRSize [
"On the x86 the only instructions that shift by the value of a
register require the shift count to be in %ecx. So we may
have to use swap instructions to get the count into ecx."
| shiftCountReg |
shiftCountReg := operands at: 0.
^shiftCountReg = RCX
ifTrue: [3]
ifFalse:
[shiftCountReg = RAX
ifTrue: [2 "XCHG RAX,r2" + 3 "Sxx" + 2 "XCHG RAX,r2"]
ifFalse: [3 "XCHG r1,r2" + 3 "Sxx" + 3 "XCHG r1,r2"]]
]
{ #category : #'generate machine code' }
CogX64Compiler >> computeSizeOfArithCqR [
self subclassResponsibility
]
{ #category : #'generate machine code' }
CogX64Compiler >> computeSizeOfArithCwR [
"The implementation depends on in-line or out-of-line literals."
^self subclassResponsibility
]
{ #category : #'generate machine code' }
CogX64Compiler >> computeSizeOfPushCw [
^(self inCurrentCompilation: (operands at: 0))
ifTrue: [9]
ifFalse: [self pushCwByteSize]
]
{ #category : #'generate machine code - support' }
CogX64Compiler >> concretizeAlignedSt1VrRMw [
<inline: true>
| srcReg destReg size offset |
size := operands at: 0.
srcReg := operands at: 1.
destReg := operands at: 2.
offset := operands at: 3.
size = 64 ifFalse: [ ^ self notYetImplemented ].
"This instruction stores in the current value of the destReg and updates it with the offset. It performs a post-increment.
It Requires that the address is aligned 16bytes (128bits).
To do so, in X64 we need two instructions (Intel Notation, destination on the left).
1) MOVDQA xmm2/m128, xmm1 : Move aligned packed integer values from xmm1 to xmm2/m128.
2) ADD r/m64, imm8 : Add sign-extended imm8 to r/m64. With the post increment"
machineCode
at: 0 put: 16r66;
at: 1 put: (self rexw: true r: srcReg x: 0 b: destReg);
at: 2 put: 16r0F;
at: 3 put: 16r7F;
at: 4 put: (self mod: ModRegInd RM: destReg RO: srcReg).
machineCode
at: 5 put: (self rexw: true r: destReg x: 0 b: destReg);
at: 6 put: 16r83;
at: 7 put: (self mod: ModReg RM: destReg RO: 0);
at: 8 put: (offset bitAnd: 16rFF).
^ machineCodeSize := 9
]
{ #category : #'generate machine code' }
CogX64Compiler >> concretizeAlignmentNops [
<inline: true>
self flag: 'if performance is an issue generate longer nops'.
0 to: machineCodeSize - 1 do:
[:i|
machineCode at: i put: 16r90]
]
{ #category : #'generate machine code' }
CogX64Compiler >> concretizeArithCqRWithRO: regOpcode raxOpcode: raxOpcode [
"Will get inlined into concretizeAt: switch."
<inline: false>
| value reg |
value := operands at: 0.
reg := operands at: 1.
machineCode
at: 0 put: (self rexR: 0 x: 0 b: reg).
(self isQuick: value) ifTrue:
[machineCode
at: 1 put: 16r83;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);
at: 3 put: (value bitAnd: 16rFF).
^machineCodeSize := 4].
(self is32BitSignedImmediate: value) ifTrue:
[reg = RAX ifTrue:
[machineCode
at: 1 put: raxOpcode;
at: 2 put: (value bitAnd: 16rFF);
at: 3 put: (value >> 8 bitAnd: 16rFF);
at: 4 put: (value >> 16 bitAnd: 16rFF);
at: 5 put: (value >> 24 bitAnd: 16rFF).
^machineCodeSize := 6].
machineCode
at: 1 put: 16r81;
at: 2 put: (self mod: ModReg RM: reg RO: regOpcode);