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CogARMv8Compiler.class.st
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CogARMv8Compiler.class.st
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Class {
#name : #CogARMv8Compiler,
#superclass : #CogAbstractInstruction,
#instVars : [
'conditionOrNil'
],
#classVars : [
'AL',
'AddOpcode',
'AndOpcode',
'BicOpcode',
'CArg0Reg',
'CArg1Reg',
'CArg2Reg',
'CArg3Reg',
'CC',
'CMPMULOverflow',
'CMPSMULL',
'CPSRReg',
'CS',
'CmpNotOpcode',
'CmpOpcode',
'ConcreteIPReg',
'ConcreteIPReg2',
'ConcretePCReg',
'ConcreteVarBaseReg',
'D0',
'D1',
'D2',
'D3',
'D4',
'D5',
'D6',
'D7',
'EQ',
'GE',
'GT',
'HI',
'LDMFD',
'LE',
'LR',
'LS',
'LT',
'MI',
'MRS',
'MSR',
'MSUB',
'MUL',
'MoveNotOpcode',
'MoveOpcode',
'NE',
'OrOpcode',
'OverflowFlag',
'PC',
'PL',
'R0',
'R1',
'R10',
'R11',
'R12',
'R16',
'R17',
'R19',
'R2',
'R20',
'R21',
'R22',
'R23',
'R24',
'R25',
'R26',
'R27',
'R3',
'R4',
'R5',
'R6',
'R7',
'R8',
'R9',
'RsbOpcode',
'SDIV',
'SMLALOpcode',
'SMULH',
'SMULL',
'SP',
'STMFD',
'SubOpcode',
'TstOpcode',
'V0',
'V1',
'V2',
'V3',
'V4',
'V5',
'V6',
'V7',
'VC',
'VS',
'XorOpcode'
],
#category : #'VMMaker-JIT'
}
{ #category : #accessing }
CogARMv8Compiler class >> IPReg [
"Answer the number of the general temp reg in the ARM APCS convention, IP"
^ConcreteIPReg
]
{ #category : #translation }
CogARMv8Compiler class >> ISA [
"Answer the name of the ISA the receiver implements."
^#aarch64
]
{ #category : #accessing }
CogARMv8Compiler class >> PCReg [
^ConcretePCReg
]
{ #category : #accessing }
CogARMv8Compiler class >> VarBaseReg [
"Answer the number of the reg we use to hold the base address of CoInterpreter variables"
^ConcreteVarBaseReg
]
{ #category : #translation }
CogARMv8Compiler class >> defaultCompilerClass [
^CogOutOfLineLiteralsARMv8Compiler
]
{ #category : #translation }
CogARMv8Compiler class >> filteredInstVarNames [
"Edit such that conditionOrNil is amongst the char size vars opcode machineCodeSize and maxSize."
^(super filteredInstVarNames copyWithout: 'conditionOrNil')
copyReplaceFrom: 5 to: 4 with: #('conditionOrNil')
]
{ #category : #translation }
CogARMv8Compiler class >> identifyingPredefinedMacros [
^#('__aarch64__' '_M_ARM64')
]
{ #category : #'class initialization' }
CogARMv8Compiler class >> initialize [
"Initialize various ARM instruction-related constants."
"CogARMCompiler initialize"
super initialize.
self ~~ CogARMv8Compiler ifTrue: [^self].
"ARM general registers"
R0 := 0.
R1 := 1.
R2 := 2.
R3 := 3.
R4 := 4.
R5 := 5.
R6 := 6.
R7 := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12.
R16 := 16.
R17 := 17.
R19 := 19.
R20 := 20.
R21 := 21.
R22 := 22.
R23 := 23.
R24 := 24.
R25 := 25.
R26 := 26.
R27 := 27.
SP := 31.
LR := 30.
PC := 15.
"ARM VFP Double precision floating point registers"
D0 := 0.
D1 := 1.
D2 := 2.
D3 := 3.
D4 := 4.
D5 := 5.
D6 := 6.
D7 := 7.
"ARM 128-bit SIMD registers"
V0 := 0.
V1 := 1.
V2 := 2.
V3 := 3.
V4 := 4.
V5 := 5.
V6 := 6.
V7 := 7.
CArg0Reg := 0.
CArg1Reg := 1.
CArg2Reg := 2.
CArg3Reg := 3.
ConcreteVarBaseReg := R24.
"X16 and X17 are the Intra procedural scratch registers"
ConcreteIPReg := R16.
ConcreteIPReg2 := R17.
"C3.1.1 Conditional branch
Conditional branches change the flow of execution depending on the current state of the Condition flags or the value in a general-purpose register."
"C1.2.4 Condition code
The A64 ISA has some instructions that set Condition flags or test Condition codes or both.
"
EQ := 0. "Equal"
NE := 1. "Not equal"
CS := 2. "Carry set"
CC := 3. "Carry clear"
MI := 4. "Minus, negative"
PL := 5. "Plus, positive or zero"
VS := 6. "Overflow"
VC := 7. "No overflow"
HI := 8. "Unsigned higher"
LS := 9. "Unsigned lower or same"
GE := 10. "Signed greater than or equal"
LT := 11. "Signed less than"
GT := 12. "Signed greater than"
LE := 13. "Signed less than or equal"
AL := 14. "Always"
"Table A3-2 in sec A3.4 Data-processing instructions of the AARM."
AddOpcode := 4.
AndOpcode := 0.
BicOpcode := 14.
CmpOpcode := 10.
CmpNotOpcode := 11.
MoveOpcode := 13.
MoveNotOpcode := 15.
OrOpcode := 12.
RsbOpcode := 3.
SMLALOpcode := 7.
SubOpcode := 2.
TstOpcode := 8.
XorOpcode := 1.
CPSRReg := 16.
OverflowFlag := 1 << 28.
"Specific instructions"
self
initializeSpecificOpcodes: #(MUL SMULH CMPMULOverflow SMULL MSR MRS LDMFD STMFD CMPSMULL SDIV MSUB)
in: thisContext method
]
{ #category : #'class initialization' }
CogARMv8Compiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
super initializeAbstractRegisters.
"According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1:
A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).
SP = r13, so the callee-saved regs are r4-r8 & r10-r12.
The caller-saved registers are those that are not callee-saved and not reserved for hardware/abi uses,
Caller saved Registers:
X0 - X7 are to pass arguments.
X8 is indirect return address.
X9 - X15 general purpose.
X16 - X17 - Intra procedure scratch register.
Callee saved registers:
X18 is caller saved but platform specific (user programs should not use it).
X19 - X29 are callee saved.
X30 is LR.
X31 is SP.
We exclude registers 0 & 1 (TempReg/CArg0Reg & CArg1Reg) from the CallerSavedRegisterMask because we only
use them for argument passing and so never want to save and restore them. In fact restoring TempReg/CArg0Reg
would overwrite function results, so it shouldn't be included under any circumstances."
CallerSavedRegisterMask := self registerMaskFor: 3 and: 4.
TempReg := R1.
ClassReg := R22.
ReceiverResultReg := R23.
SendNumArgsReg := R25.
SPReg := 28. "X28 is used to manage the Smalltalk stack".
FPReg := 29. "X29"
Arg0Reg := R3. "overlaps with last C arg reg"
Arg1Reg := R4.
Extra0Reg := R19. "These are callee saved registers"
Extra1Reg := R20.
Extra2Reg := R21.
Extra3Reg := R26.
Extra4Reg := R27.
VarBaseReg := R24. "Must be callee saved" self assert: ConcreteVarBaseReg = R24.
RISCTempReg := R16. "a.k.a. IP" self assert: ConcreteIPReg = R16.
LinkReg := LR. "X30"
PCReg := PC. "R15"
NumRegisters := 16.
DPFPReg0 := D0.
DPFPReg1 := D1.
DPFPReg2 := D2.
DPFPReg3 := D3.
DPFPReg4 := D4.
DPFPReg5 := D5.
DPFPReg6 := D6.
DPFPReg7 := D7.
VReg0 := V0.
VReg1 := V1.
VReg2 := V2.
VReg3 := V3.
VReg4 := V4.
VReg5 := V5.
VReg6 := V6.
VReg7 := V7.
NumFloatRegisters := 8
]
{ #category : #testing }
CogARMv8Compiler class >> isAbstract [
^self == CogARMv8Compiler
]
{ #category : #testing }
CogARMv8Compiler class >> isRISCTempRegister: reg [
"For tests to filter-out bogus values left in the RISCTempRegister, if any."
^reg = ConcreteIPReg
]
{ #category : #translation }
CogARMv8Compiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array.
ARM instructions are 32-bits in length."
^{#'unsigned int'. '[', self basicNew machineCodeWords printString, ']'}
]
{ #category : #accessing }
CogARMv8Compiler class >> orOpcode [
^OrOpcode
]
{ #category : #'class initialization' }
CogARMv8Compiler class >> specificOpcodes [
"Answer the processor-specific opcodes for this class.
They're all in an Array literal in the initialize method."
^(self class >> #initialize) literals detect: [:l| l isArray and: [l includes: #LDMFD]]
]
{ #category : #translation }
CogARMv8Compiler class >> wordSize [
"This is a 64-bit ISA"
^8
]
{ #category : #'ARM convenience instructions' }
CogARMv8Compiler >> add: destReg rn: srcReg imm: immediate ror: rot [
self assert: rot = 0.
^ self
addSize: 1
sourceRegister: srcReg
shift: 0
immediate12: immediate
destinationRegister: destReg
]
{ #category : #assembler }
CogARMv8Compiler >> addSize: is64Bits sourceRegister: sourceRegister shift: shift immediate12: immediate12bitValue destinationRegister: destinationRegister [
"C6.2.4 ADD (immediate)
Add (immediate) adds a register value and an optionally-shifted immediate value, and writes the result to the destination register.
ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
if shift = 1 the immediate will be shifted by 12
"
^ is64Bits << 31
bitOr: (2r00100010 << 23
bitOr: ((shift bitAnd: 2r1) << 22
bitOr: (immediate12bitValue << 10
bitOr: ((sourceRegister bitAnd: 2r11111) << 5
bitOr: (destinationRegister bitAnd: 2r11111)))))
]
{ #category : #adding }
CogARMv8Compiler >> addT: t q: q term1: vectorReg1 term2: vectorReg2 dest: vectorRegSum [
"
C7.2.49 FADD (vector)
FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register.
All the values in this instruction are floating-point values."
^ q << 30
bitOr: (2r01110 << 24
bitOr: ((t bitAnd: 1) << 22
bitOr: (1 << 21
bitOr: ((vectorReg2 bitAnd: 2r11111) << 16
bitOr: (2r110101 << 10
bitOr: ((vectorReg1 bitAnd: 2r11111) << 5
bitOr: (vectorRegSum bitAnd: 2r11111)))))))
]
{ #category : #assembler }
CogARMv8Compiler >> addsExtendedSize: is64Bits leftRegisterMaybeSP: leftRegister shiftedRightRegister: rightRegister option: option shiftOffset: immediate3bitValue destinationRegister: destinationRegister [
"C6.2.7 ADDS (extended register)
Add (extended register), setting flags, adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.
ADDS <Xd>, <Xn|SP>, <R><m>{, <extend> {#<amount>}}"
^ is64Bits << 31
bitOr: (2r0101011001 << 21
bitOr: ((rightRegister bitAnd: 16r1f) << 16
bitOr: ((option bitAnd: 2r11) << 13
bitOr: ((immediate3bitValue bitAnd: 2r111) << 10
bitOr: ((leftRegister bitAnd: 16r1f) << 5
bitOr: (destinationRegister bitAnd: 16r1f))))))
]
{ #category : #assembler }
CogARMv8Compiler >> addsSize: is64Bits leftRegister: leftRegister shiftedRightRegister: rightRegister shiftType: shiftType shiftOffset: immediate6bitValue destinationRegister: destinationRegister [
"C6.2.9 ADDS (shifted register)
Add (shifted register), setting flags, adds a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.
ADDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
LSL when shift = 00
LSR when shift = 01
ASR when shift = 10"
^ self
arithmeticShiftedRegisterSize: is64Bits
isSubstraction: 0
setFlags: 1
leftRegister: leftRegister
shiftedRightRegister: rightRegister
shiftType: shiftType
shiftOffset: immediate6bitValue
destinationRegister: destinationRegister
]
{ #category : #'as yet unclassified' }
CogARMv8Compiler >> addsSize: is64Bits sourceRegister: leftRegister immediate12BitValue: immediate12BitValue shifted: shiftedFlag destinationRegister: destinationRegister [
"C6.2.8 ADDS (immediate)
Add (immediate), setting flags, adds a register value and an optionally-shifted immediate value, and writes the result to the destination register. It updates the condition flags based on the result.
ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}"
^ self
arithmeticImmediateSize: is64Bits
isSubstraction: 0
setFlags: 1
sourceRegister: leftRegister
immediate12BitValue: immediate12BitValue
shifted: shiftedFlag destinationRegister: destinationRegister
]
{ #category : #'as yet unclassified' }
CogARMv8Compiler >> adrSignedImmediate21BitsValue: signedImmediate21bitValue destinationRegister: destinationRegister [
"C6.2.10 ADR
Form PC-relative address adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register.
ADR <Xd>, <label>
signedImmediate21bitValue - Is the program label whose address is to be calculated. Its offset from the address of this instruction, in the range +/-1MB, is encoded in
immhi:immlo"
| twoComplement immhi immlo |
twoComplement := signedImmediate21bitValue < 0
ifTrue: [ 16r1fffff - signedImmediate21bitValue abs + 1 ]
ifFalse: [ signedImmediate21bitValue ].
immhi := twoComplement >> 2.
immlo := twoComplement bitAnd: 2r11.
^ immlo << 29
bitOr: (2r10000 << 24
bitOr: (immhi << 5
bitOr: (destinationRegister bitAnd: 16r1f)))
]
{ #category : #assembler }
CogARMv8Compiler >> andSetFlagsSize: is64Bits immediate13bitValue: logicalEncodedImmediate13BitValue sourceRegister: sourceRegister destinationRegister: destinationRegister [
"C6.2.14 ANDS (immediate)
Bitwise AND (immediate), setting flags, performs a bitwise AND of a register value and an immediate value, and writes the result to the destination
register. It updates the condition flags based on the result. This instruction is used by the alias TST (immediate). See Alias conditions for details of
when each alias is preferred.
ANDS <Xd|SP>, <Xn>, #<imm>"
^ self
logicalImmediate: is64Bits
opcode: 2r11
immediate13bitValue: logicalEncodedImmediate13BitValue
sourceRegister: sourceRegister
destinationRegister: destinationRegister
]
{ #category : #assembler }
CogARMv8Compiler >> andSetFlagsSize: is64Bits shiftedRegister: shiftedRegister shiftType: shiftType shiftValue: immediate6bitValue withRegister: sourceRegister2 destinationRegister: destinationRegister [
"C6.2.15 ANDS (shifted register)
Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the
result to the destination register. It updates the condition flags based on the result.
This instruction is used by the alias TST (shifted register). See Alias conditions for details of when each alias is preferred.
ANDS <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
LSL when shift = 00 LSR when shift = 01 ASR when shift = 10 ROR when shift = 11"
^ is64Bits << 31
bitOr: (2r1101010 << 24
bitOr: ((shiftType bitAnd: 2r11) << 22
bitOr: ((shiftedRegister bitAnd: 2r11111) << 16
bitOr: ((immediate6bitValue bitAnd: 2r111111) << 10
bitOr: ((sourceRegister2 bitAnd: 2r11111) << 5
bitOr: (destinationRegister bitAnd: 2r11111))))))
]
{ #category : #assembler }
CogARMv8Compiler >> andSize: is64Bits immediate13bitValue: logicalEncodedImmediate13BitValue sourceRegister: sourceRegister destinationRegister: destinationRegister [
"C6.2.12 AND (immediate)
Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.
AND <Xd|SP>, <Xn>, #<imm>"
^ is64Bits << 31
bitOr: (2r00100100 << 23
bitOr: ((logicalEncodedImmediate13BitValue bitAnd: 16r1fff)
bitOr: ((sourceRegister bitAnd: 16r1f) << 5
bitOr: (destinationRegister bitAnd: 16r1f))))
]
{ #category : #assembler }
CogARMv8Compiler >> andSize: is64Bits shiftedRegister: shiftedRegister shiftType: shiftType shiftValue: immediate6bitValue withRegister: sourceRegister2 destinationRegister: destinationRegister [
"C6.2.13 AND (shifted register)
Bitwise AND (shifted register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.
AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
LSL when shift = 00 LSR when shift = 01 ASR when shift = 10 ROR when shift = 11"
^ is64Bits << 31
bitOr: (2r0001010 << 24
bitOr: ((shiftType bitAnd: 2r11) << 22
bitOr: ((shiftedRegister bitAnd: 2r11111) << 16
bitOr: ((immediate6bitValue bitAnd: 2r111111) << 10
bitOr: ((sourceRegister2 bitAnd: 2r11111) << 5
bitOr: (destinationRegister bitAnd: 2r11111))))))
]
{ #category : #assembler }
CogARMv8Compiler >> arithmeticImmediateSize: is64Bits isSubstraction: substractionFlag setFlags: setFlagsFlag sourceRegister: sourceRegister immediate12BitValue: immediate12BitValue shifted: shiftedFlag destinationRegister: destinationRegister [
"C4.1.2 Data Processing -- Immediate
C3.3.1 Arithmetic (immediate)
The Arithmetic (immediate) instructions accept a 12-bit unsigned immediate value, optionally shifted left by 12 bits.
The Arithmetic (immediate) instructions that do not set Condition flags can read from and write to the current stack pointer. The flag setting instructions can read from the stack pointer, but they cannot write to it.
- is64Bits: single bit indicating if the registers should be interpreted as 64bit (X) or 32bit (W) registers.
- substractionFlag: single bit indicating if the instruction is a SUB or ADD
- setFlagsFlag: single bit indicating if the instruction should set flags (SUBS vs SUB, ADDS vs ADD)
- shiftedFlag: single bit indicating if the immediate value should be shifted 12 bits
LSL when shiftType = 00
LSR when shiftType = 01
ASR when shiftType = 10"
^ (is64Bits bitAnd: 1) << 31
bitOr: ((substractionFlag bitAnd: 1) << 30
bitOr: ((setFlagsFlag bitAnd: 1) << 29
bitOr: (2r100010 << 23
bitOr: ((shiftedFlag bitAnd: 2r1) << 22
bitOr: ((immediate12BitValue bitAnd: 16rfff) << 10
bitOr: ((sourceRegister bitAnd: 2r11111) << 5
bitOr: (destinationRegister bitAnd: 2r11111)))))))
]
{ #category : #assembler }
CogARMv8Compiler >> arithmeticShiftRightSize: is64bits sourceRegister: sourceRegister shiftRegister: shiftRegister destinationRegister: destinationRegister [
"C6.2.16 ASR (register)
Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.
ASR <Xd>, <Xn>, <Xm>
"
^ is64bits << 31
bitOr: (2r11010110 << 21
bitOr: ((shiftRegister bitAnd: 16r1f) << 16
bitOr: (2r1010 << 10
bitOr: ((sourceRegister bitAnd: 16r1f) << 5
bitOr: (destinationRegister bitAnd: 16r1f)))))
]
{ #category : #'as yet unclassified' }
CogARMv8Compiler >> arithmeticShiftRightSize: is64Bits sourceRegister: sourceRegister shiftValue: shiftValue destinationRegister: destinationRegister [
"C6.2.17 ASR (immediate)
Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of the sign bit in the upper bits and zeros in the lower bits, and writes the result to the destination register.
ASR <Xd>, <Xn>, #<shift>"
^ is64Bits << 31
bitOr: (2r00100110 << 23
bitOr: ((is64Bits bitAnd: 1) << 22
bitOr: ((shiftValue bitAnd: 16r3f) << 16
bitOr: (16r3f << 10
bitOr: ((sourceRegister bitAnd: 16r1f) << 5
bitOr: (destinationRegister bitAnd: 16r1f))))))
]
{ #category : #assembler }
CogARMv8Compiler >> arithmeticShiftedRegisterSize: is64Bits isSubstraction: substractionFlag setFlags: setFlagsFlag leftRegister: leftRegister shiftedRightRegister: rightRegister shiftType: shiftType shiftOffset: immediate6bitValue destinationRegister: destinationRegister [
"C4.1.5 Data Processing -- Register
- is64Bits: single bit indicating if the registers should be interpreted as 64bit (X) or 32bit (W) registers.
- substractionFlag: single bit indicating if the instruction is a SUB or ADD
- setFlagsFlag: single bit indicating if the instruction should set flags (SUBS vs SUB, ADDS vs ADD)
LSL when shiftType = 00
LSR when shiftType = 01
ASR when shiftType = 10"
^ (is64Bits bitAnd: 1) << 31
bitOr: ((substractionFlag bitAnd: 1) << 30
bitOr: ((setFlagsFlag bitAnd: 1) << 29
bitOr: (2r01011 << 24
bitOr: ((shiftType bitAnd: 2r11) << 22
bitOr: ((rightRegister bitAnd: 2r11111) << 16
bitOr:((immediate6bitValue bitAnd: 2r111111) << 10
bitOr: ((leftRegister bitAnd: 2r11111) << 5
bitOr: (destinationRegister bitAnd: 2r11111))))))))
]
{ #category : #'as yet unclassified' }
CogARMv8Compiler >> assembleSubCq: quickValue R: registerToUse [
| fits12Bits |
fits12Bits := (quickValue bitAnd: 16rfff) = quickValue.
fits12Bits ifTrue: [ | reg |
reg := operands at: 1.
self
machineCodeAt: 0
put:
(self
subsSize: 1
sourceRegister: reg
immediate12BitValue: quickValue
shifted: 0
destinationRegister: reg).
^ machineCodeSize := 4
].
self notYetImplemented.
^ 0
]
{ #category : #'register allocation' }
CogARMv8Compiler >> availableRegisterOrNoneFor: liveRegsMask [
"Answer an unused abstract register in the liveRegMask.
Subclasses with more registers can override to answer them.
N.B. Do /not/ allocate TempReg."
<returnTypeC: #sqInt>
(cogit register: Extra0Reg isInMask: liveRegsMask) ifFalse:
[^Extra0Reg].
(cogit register: Extra1Reg isInMask: liveRegsMask) ifFalse:
[^Extra1Reg].
(cogit register: Extra2Reg isInMask: liveRegsMask) ifFalse:
[^Extra2Reg].
^super availableRegisterOrNoneFor: liveRegsMask
]
{ #category : #assembler }
CogARMv8Compiler >> b: immediate26bitValue [
"C6.2.26 B
Branch causes an unconditional branch to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.
26-bit signed PC-relative branch offset variant
BL <label>
<label> Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as imm26 times 4."
^ self b: immediate26bitValue withLink: false
]
{ #category : #assembler }
CogARMv8Compiler >> b: immediate26bitValue withLink: aBoolean [
| twoComplement multiplier |
"Branch optionally with Link branches to a PC-relative offset, setting the register X30 to PC+4. It provides a hint that this is a subroutine call.
26-bit signed PC-relative branch offset variant
BL <label>
<label> Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as imm26 times 4."
self seeAlso: #b:.
self seeAlso: #bl:.
multiplier := immediate26bitValue / 4.
twoComplement := multiplier > 0
ifTrue: [ multiplier ]
ifFalse: [ 2r11111111111111111111111111 - multiplier abs + 1 ].
^ (aBoolean ifTrue: [1]ifFalse: [0]) << 31
bitOr: (2r00101 << 26
bitOr: twoComplement)
]
{ #category : #assembler }
CogARMv8Compiler >> bl: immediate26bitValue [
"C6.2.33 BL
Branch with Link branches to a PC-relative offset, setting the register X30 to PC+4. It provides a hint that this is a subroutine call.
26-bit signed PC-relative branch offset variant
BL <label>
<label> Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as imm26 times 4."
^ self b: immediate26bitValue withLink: true
]
{ #category : #assembler }
CogARMv8Compiler >> blr: registerToUse [
"C6.2.34 BLR
Branch with Link to Register calls a subroutine at an address in a register, setting register X30 to PC+4.
BLR <Xn>"
^ self br: registerToUse withLink: 1
]
{ #category : #'ARM convenience instructions' }
CogARMv8Compiler >> blx: targetReg [
"Branch&link to the address in targetReg. Return address is in LR
BLX targetReg - ARM_ARM v7 DDI10406 pp. A8-60-1"
<inline: true>
^self cond: AL bx: 1 target: targetReg
]
{ #category : #assembler }
CogARMv8Compiler >> br: registerToUse [
"C6.2.36 BR
Branch to Register branches unconditionally to an address in a register, with a hint that this is not a subroutine return.
BR <Xn>"
^ self br: registerToUse withLink: 0
]
{ #category : #assembler }
CogARMv8Compiler >> br: registerToUse withLink: withLink [
"Branch optionally with Link branches to Register calls a subroutine at an address in a register, setting register X30 to PC+4.
BRL Xn
"
^ 2r110101100 << 23
bitOr: ((withLink bitAnd: 2r11) << 21
bitOr: (2r11111 << 16
bitOr: (registerToUse bitAnd: 16r1f) << 5))
]
{ #category : #assembler }
CogARMv8Compiler >> branchCondition: condition offset: immediate19bitValue [
"C6.2.25 B.cond
Branch conditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.
B.<cond> <label>
"
| multiplier twoComplement |
"Precondition:
the jump target can be encoded as an immediate of 19 bits multiplied by 4"
self assert: (immediate19bitValue >> 2 << 2 = immediate19bitValue).
self assert: (16r3ffff allMask: immediate19bitValue abs >> 2).
multiplier := immediate19bitValue >> 2.
twoComplement := multiplier < 0
ifTrue: [ 2r1111111111111111111 - multiplier abs + 1 ]
ifFalse: [ multiplier ].
^ 2r01010100 << 24
bitOr: ((twoComplement bitAnd: 2r1111111111111111111) << 5
bitOr: (condition bitAnd: 16rf))
]
{ #category : #testing }
CogARMv8Compiler >> byteReadsZeroExtend [
^true
]
{ #category : #abi }
CogARMv8Compiler >> cResultRegister [
"Answer the register through which C funcitons return integral results."
<inline: true>
^R0
]
{ #category : #accessing }
CogARMv8Compiler >> cStackPointer [
^ SP
]
{ #category : #accessing }
CogARMv8Compiler >> callInstructionByteSize [
"ARM calls and jumps span +/- 32 mb, more than enough for intra-zone calls and jumps."
^4
]
{ #category : #'inline cacheing' }
CogARMv8Compiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address that the call immediately preceding callSiteReturnAddress will jump to."
"this is also used by #jumpLongTargetBeforeFollowingAddress:."
| callDistance callInstruction callAddress |
callAddress := self instructionAddressBefore: callSiteReturnAddress.
callInstruction := objectMemory long32At: callAddress.
self assert: ((self instructionIsB: callInstruction) or: [self instructionIsBL: callInstruction]).
callDistance := self extractOffsetFromBL: callInstruction.
"this is the pc's offset at the branch"
^callAddress + callDistance signedIntFromLong
]
{ #category : #testing }
CogARMv8Compiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogARMv8Compiler >> canMulRR [
"we can do a MulRR be we can't simulate it correctly for some reason. More bug-fixing in the simulator one day"
^true
]
{ #category : #assembler }
CogARMv8Compiler >> cmnSize: is64bits immediate12BitValue: immediate12BitValue shiftFlag: shiftFlag register: registerToUse [
"C6.2.58 CMN (immediate)
Compare Negative (immediate) adds a register value and an optionally-shifted immediate value. It updates the condition flags based on the result, and discards the result.
CMN <Xn|SP>, #<imm>{, <shift>}
- shiftFlag: single bit indicating if the immediate value should be shifted 12 bits or not"
^ self
addsSize: is64bits
sourceRegister: registerToUse
immediate12BitValue: immediate12BitValue
shifted: shiftFlag
destinationRegister: 2r11111
]
{ #category : #assembler }
CogARMv8Compiler >> cmpExtendedRegisterSize: is64Bits leftRegisterMaybeSP: leftRegister option: option shiftOffset: immediate3bitValue destinationRegister: destinationRegister [
"C6.2.60 CMP (extended register)
Compare (extended register) subtracts a sign or zero-extended register value, followed by an optional left shift amount, from a register value. The argument that is extended from the <Rm> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result, and discards the result.
CMP <Xn|SP>, <R><m>{, <extend> {#<amount>}}
"
^ self
subsExtendedSize: is64Bits
leftRegisterMaybeSP: leftRegister
shiftedRightRegister: destinationRegister
option: option
shiftOffset: immediate3bitValue
destinationRegister: 2r11111
]
{ #category : #assembler }
CogARMv8Compiler >> cmpSize: is64bits immediate12BitValue: immediate12BitValue shiftFlag: shiftFlag register: registerToUse [
"C6.2.61 CMP (immediate)
Compare (immediate) subtracts an optionally-shifted immediate value from a register value. It updates the condition flags based on the result, and discards the result.
CMP <Xn|SP>, #<imm>{, <shift>}
- shiftFlag: single bit indicating if the immediate value should be shifted 12 bits or not"
^ self
subsSize: is64bits
sourceRegister: registerToUse
immediate12BitValue: immediate12BitValue
shifted: shiftFlag
destinationRegister: 2r11111
]
{ #category : #assembler }
CogARMv8Compiler >> cmpSize: is64bits shiftedRegister: register1 shiftType: shiftType shiftValue: immediate6BitShiftValue secondRegister: register2 [
"C6.2.62 CMP (shifted register)
Compare (shifted register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result.
CMP <Xn>, <Xm>{, <shift> #<amount>}
LSL when shift = 00
LSR when shift = 01
ASR when shift = 10"
^ is64bits << 31
bitOr: (2r1101011 << 24
bitOr: ((shiftType bitAnd: 2r11) << 22
bitOr: ((register1 bitAnd: 16r1f) << 16
bitOr: ((immediate6BitShiftValue bitAnd: 16r3f) << 10
bitOr: ((register2 bitAnd: 16r1f) << 5
bitOr: 2r11111)))))
]
{ #category : #accessing }
CogARMv8Compiler >> codeGranularity [
"Answer the size in bytes of a unit of machine code."
<inline: true>
^4
]
{ #category : #'generate machine code' }
CogARMv8Compiler >> computeMaximumSize [
"Because we don't use Thumb, each ARM instruction has 4 bytes. Many
abstract opcodes need more than one instruction. Instructions that refer
to constants and/or literals depend on literals being stored in-line or out-of-line.
N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
| offset |
<var: #offset type: #'sqInt'>
opcode
caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[Literal] -> [^8].