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CogARMCompiler.class.st
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CogARMCompiler.class.st
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"
I generate ARM instructions from CogAbstractInstructions. For reference see
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.architecture/index.html
The Architecture Reference Manual used is that of version 5, which includes some version 6 instructions. Of those, only pld is used(for PrefetchAw).
This class does not take any special action to flush the instruction cache on instruction-modification.
"
Class {
#name : #CogARMCompiler,
#superclass : #CogAbstractInstruction,
#instVars : [
'conditionOrNil'
],
#classVars : [
'AL',
'AddOpcode',
'AndOpcode',
'BicOpcode',
'CArg0Reg',
'CArg1Reg',
'CArg2Reg',
'CArg3Reg',
'CC',
'CMPSMULL',
'CPSRReg',
'CS',
'CmpNotOpcode',
'CmpOpcode',
'ConcreteIPReg',
'ConcretePCReg',
'ConcreteVarBaseReg',
'D0',
'D1',
'D2',
'D3',
'D4',
'D5',
'D6',
'D7',
'EQ',
'GE',
'GT',
'HI',
'LDMFD',
'LE',
'LR',
'LS',
'LT',
'MI',
'MRS',
'MSR',
'MoveNotOpcode',
'MoveOpcode',
'NE',
'OrOpcode',
'OverflowFlag',
'PC',
'PL',
'PopLDM',
'PushSTM',
'R0',
'R1',
'R10',
'R11',
'R12',
'R2',
'R3',
'R4',
'R5',
'R6',
'R7',
'R8',
'R9',
'RsbOpcode',
'SMLALOpcode',
'SMULL',
'SP',
'STMFD',
'SubOpcode',
'TstOpcode',
'VC',
'VS',
'XorOpcode'
],
#category : #'VMMaker-JIT'
}
{ #category : #accessing }
CogARMCompiler class >> IPReg [
"Answer the number of the general temp reg in the ARM APCS convention, IP"
^ConcreteIPReg
]
{ #category : #translation }
CogARMCompiler class >> ISA [
"Answer the name of the ISA the receiver implements."
^#ARMv5
]
{ #category : #accessing }
CogARMCompiler class >> PCReg [
^ConcretePCReg
]
{ #category : #accessing }
CogARMCompiler class >> VarBaseReg [
"Answer the number of the reg we use to hold the base address of CoInterpreter variables"
^ConcreteVarBaseReg
]
{ #category : #translation }
CogARMCompiler class >> defaultCompilerClass [
^CogOutOfLineLiteralsARMCompiler
]
{ #category : #translation }
CogARMCompiler class >> filteredInstVarNames [
"Edit such that conditionOrNil is amongst the char size vars opcode machineCodeSize and maxSize."
^(super filteredInstVarNames copyWithout: 'conditionOrNil')
copyReplaceFrom: 5 to: 4 with: #('conditionOrNil')
]
{ #category : #translation }
CogARMCompiler class >> identifyingPredefinedMacros [
^#('__ARM_ARCH_5__' '__ARM_ARCH_6__' '__ARM_ARCH_7__' '__arm__' '__arm32__' 'ARM32' '_M_ARM')
]
{ #category : #'class initialization' }
CogARMCompiler class >> initialize [
"Initialize various ARM instruction-related constants."
"CogARMCompiler initialize"
super initialize.
self ~~ CogARMCompiler ifTrue: [^self].
"ARM general registers"
R0 := 0.
R1 := 1.
R2 := 2.
R3 := 3.
R4 := 4.
R5 := 5.
R6 := 6.
R7 := 7.
R8 := 8.
R9 := 9.
R10 := 10.
R11 := 11.
R12 := 12.
SP := 13.
LR := 14.
PC := 15.
"ARM VFP Double precision floating point registers"
D0 := 0.
D1 := 1.
D2 := 2.
D3 := 3.
D4 := 4.
D5 := 5.
D6 := 6.
D7 := 7.
CArg0Reg := 0.
CArg1Reg := 1.
CArg2Reg := 2.
CArg3Reg := 3.
ConcreteVarBaseReg := 10.
ConcreteIPReg := 12. "IP, The Intra-Procedure-call scratch register."
ConcretePCReg := 15.
"Condition Codes. Note that cc=16rF is NOT ALLOWED as a condition; it specifies an extension instruction. See e.g.ARM_ARM v5 DDI01001.pdf A3.2.1"
EQ := 0.
NE := 1.
CS := 2.
CC := 3.
MI := 4.
PL := 5.
VS := 6.
VC := 7.
HI := 8.
LS := 9.
GE := 10.
LT := 11.
GT := 12.
LE := 13.
AL := 14.
"Table A3-2 in sec A3.4 Data-processing instructions of the AARM."
AddOpcode := 4.
AndOpcode := 0.
BicOpcode := 14.
CmpOpcode := 10.
CmpNotOpcode := 11.
MoveOpcode := 13.
MoveNotOpcode := 15.
OrOpcode := 12.
RsbOpcode := 3.
SMLALOpcode := 7.
SubOpcode := 2.
TstOpcode := 8.
XorOpcode := 1.
CPSRReg := 16.
OverflowFlag := 1 << 28.
"Specific instructions"
self
initializeSpecificOpcodes: #(SMULL MSR MRS PopLDM PushSTM LDMFD STMFD CMPSMULL)
in: thisContext method
]
{ #category : #'class initialization' }
CogARMCompiler class >> initializeAbstractRegisters [
"Assign the abstract registers with the identities/indices of the relevant concrete registers."
super initializeAbstractRegisters.
"According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1:
A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).
SP = r13, so the callee-saved regs are r4-r8 & r10-r12.
The caller-saved registers are those that are not callee-saved and not reserved for hardware/abi uses,
i..e r0-r3, r9 & r12.
We exclude registers 0 & 1 (TempReg/CArg0Reg & CArg1Reg) from the CallerSavedRegisterMask because we only
use them for argument passing and so never want to save and restore them. In fact restoring TempReg/CArg0Reg
would overwrite function results, so it shouldn't be included under any circumstances."
CallerSavedRegisterMask := self registerMaskFor: 0 and: 1 and: 2 and: 3 and: 9 and: 12.
TempReg := R2.
ClassReg := R8.
ReceiverResultReg := R5.
SendNumArgsReg := R6.
SPReg := SP. "a.k.a. R13" self assert: SP = 13.
FPReg := R11.
Arg0Reg := R3. "overlaps with last C arg reg"
Arg1Reg := R4.
Extra0Reg := R7. "These are callee saved registers"
Extra1Reg := R0.
Extra2Reg := R9.
VarBaseReg := R10. "Must be callee saved" self assert: ConcreteVarBaseReg = R10.
RISCTempReg := R12. "a.k.a. IP" self assert: ConcreteIPReg = R12.
LinkReg := LR. "R14"
PCReg := PC. "R15"
NumRegisters := 16.
DPFPReg0 := D0.
DPFPReg1 := D1.
DPFPReg2 := D2.
DPFPReg3 := D3.
DPFPReg4 := D4.
DPFPReg5 := D5.
DPFPReg6 := D6.
DPFPReg7 := D7.
"These registers are undefined"
VReg0 := -1.
VReg1 := -1.
VReg2 := -1.
VReg3 := -1.
VReg4 := -1.
VReg5 := -1.
VReg6 := -1.
VReg7 := -1.
NumFloatRegisters := 8
]
{ #category : #testing }
CogARMCompiler class >> isAbstract [
^self == CogARMCompiler
]
{ #category : #testing }
CogARMCompiler class >> isRISCTempRegister: reg [
"For tests to filter-out bogus values left in the RISCTempRegister, if any."
^reg = ConcreteIPReg
]
{ #category : #translation }
CogARMCompiler class >> machineCodeDeclaration [
"Answer the declaration for the machineCode array.
ARM instructions are 32-bits in length."
^{#'unsigned int'. '[', self basicNew machineCodeWords printString, ']'}
]
{ #category : #accessing }
CogARMCompiler class >> orOpcode [
^OrOpcode
]
{ #category : #'class initialization' }
CogARMCompiler class >> specificOpcodes [
"Answer the processor-specific opcodes for this class.
They're all in an Array literal in the initialize method."
^(self class >> #initialize) literals detect: [:l| l isArray and: [l includes: #LDMFD]]
]
{ #category : #translation }
CogARMCompiler class >> wordSize [
"This is a 32-bit ISA"
^4
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> add: destReg rn: srcReg imm: immediate ror: rot [
"Remember the ROR is doubled by the cpu so use 30>>1 etc.
ADD destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-23"
^self type: 1 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> add: destReg rn: srcReg rm: addReg [
"return an ADD destReg, srcReg, addReg instruction
ADD destReg, srcReg, addReg - ARM_ARM v7 DDI10406 p. A8-24"
^self type: 0 op: AddOpcode set: 0 rn: srcReg rd: destReg shifterOperand: addReg
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> adds: destReg rn: srcReg imm: immediate ror: rot [
"Remember the ROR is doubled by the cpu so use 30>>1 etc
ADDS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-23"
^self type: 1 op: AddOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)
]
{ #category : #simulation }
CogARMCompiler >> aeabiDiv: dividend Mod: divisor [
"simulate the __aeabi_idivmod call"
<doNotGenerate>
| proc result dividendAsInteger divisorAsInteger|
proc := cogit processor.
dividendAsInteger := proc convertInternalToInteger: dividend.
divisorAsInteger := proc convertInternalToInteger: divisor.
proc r0: (result := proc convertIntegerToInternal: (dividendAsInteger quo: divisorAsInteger)).
proc r1: (proc convertIntegerToInternal: (dividendAsInteger rem: divisorAsInteger)).
^result
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> aeabiDivModFunctionAddr [
"Answer the address of the __aeabi_idivmod() call provided by the ARM low level libs to do an integer divide that returns the quo in R0 and rem in R1.
A word on the somewhat strange usage of idivmod herein; we need a declaration for the _aeabi_idivmod helper function, despite the fact that in a simple C program test, you don't.
To get that declaration we need a variable to hang it off; thus the non-existent var idivmod, and in simulation we need to simulate it, which is what aeabiDiv:Mod: does."
| idivmod | "This variable should be in here to be able to be translated"
<returnTypeC: #usqInt>
<var: #idivmod declareC: 'extern void __aeabi_idivmod(int dividend, int divisor)'>
^self cCode: '(usqInt)__aeabi_idivmod' inSmalltalk:[#aeabiDiv:Mod:]
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> and: destReg rn: srcReg imm: immediate ror: rot [
"Remember the ROR is doubled by the cpu so use 30>>1 etc
AND destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-34"
^self type: 1 op: AndOpcode set: 0 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> ands: destReg rn: srcReg imm: immediate ror: rot [
"Remember the ROR is doubled by the cpu so use 30>>1 etc
ANDS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 p. A8-34"
^self type: 1 op: AndOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)
]
{ #category : #'register allocation' }
CogARMCompiler >> availableRegisterOrNoneFor: liveRegsMask [
"Answer an unused abstract register in the liveRegMask.
Subclasses with more registers can override to answer them.
N.B. Do /not/ allocate TempReg."
<returnTypeC: #sqInt>
(cogit register: Extra0Reg isInMask: liveRegsMask) ifFalse:
[^Extra0Reg].
(cogit register: Extra1Reg isInMask: liveRegsMask) ifFalse:
[^Extra1Reg].
(cogit register: Extra2Reg isInMask: liveRegsMask) ifFalse:
[^Extra2Reg].
^super availableRegisterOrNoneFor: liveRegsMask
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> b: offset [
"return a B offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range
B offset - ARM_ARM v7 DDI10406 pp. A8-44-5"
^self cond: AL br: 0 offset: offset
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> bics: destReg rn: srcReg imm: immediate ror: rot [
"Remember the ROR is doubled by the cpu so use 30>>1 etc
BICS destReg, srcReg, #immediate ROR #rot - ARM_ARM v7 DDI10406 pp. A8-50-1"
^self type: 1 op: BicOpcode set: 1 rn: srcReg rd: destReg shifterOperand: ((rot>>1) <<8 bitOr: immediate)
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> bl: offset [
"return a BL offset instruction; offset is signed 24bits of WORD offset, so +_32Mbyte range. Return address is in LR
BL offset - ARM_ARM v7 DDI10406 pp. A8-58-9"
^self cond: AL br: 1 offset: offset
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> blx: targetReg [
"Branch&link to the address in targetReg. Return address is in LR
BLX targetReg - ARM_ARM v7 DDI10406 pp. A8-60-1"
<inline: true>
^self cond: AL bx: 1 target: targetReg
]
{ #category : #'ARM convenience instructions' }
CogARMCompiler >> bx: targetReg [
"Branch to address in targetReg. BX targetReg
BX targetReg - ARM_ARM v7 DDI10406 pp. A8-62-3"
<inline: true>
^self cond: AL bx: 0 target: targetReg
]
{ #category : #testing }
CogARMCompiler >> byteReadsZeroExtend [
^true
]
{ #category : #abi }
CogARMCompiler >> cResultRegister [
"Answer the register through which C funcitons return integral results."
<inline: true>
^R0
]
{ #category : #accessing }
CogARMCompiler >> cStackPointer [
^ SP
]
{ #category : #accessing }
CogARMCompiler >> callInstructionByteSize [
"ARM calls and jumps span +/- 32 mb, more than enough for intra-zone calls and jumps."
^4
]
{ #category : #'inline cacheing' }
CogARMCompiler >> callTargetFromReturnAddress: callSiteReturnAddress [
"Answer the address that the call immediately preceding callSiteReturnAddress will jump to."
"this is also used by #jumpLongTargetBeforeFollowingAddress:."
| callDistance call |
call := self instructionBeforeAddress: callSiteReturnAddress.
self assert: ((self instructionIsB: call) or: [self instructionIsBL: call]).
callDistance := self extractOffsetFromBL: call.
"this is the pc's +8 offset, - the 4 byte correction for the previous instruction address"
^callSiteReturnAddress + 4 + callDistance signedIntFromLong
]
{ #category : #testing }
CogARMCompiler >> canDivQuoRem [
^true
]
{ #category : #testing }
CogARMCompiler >> canMulRR [
"we can do a MulRR be we can't simulate it correctly for some reason. More bug-fixing in the simulator one day"
^true
]
{ #category : #testing }
CogARMCompiler >> canPushPopMultipleRegisters [
<inline: true>
^true
]
{ #category : #accessing }
CogARMCompiler >> codeGranularity [
"Answer the size in bytes of a unit of machine code."
<inline: true>
^4
]
{ #category : #'generate machine code' }
CogARMCompiler >> computeMaximumSize [
"Because we don't use Thumb, each ARM instruction has 4 bytes. Many
abstract opcodes need more than one instruction. Instructions that refer
to constants and/or literals depend on literals being stored in-line or out-of-line.
N.B. The ^N forms are to get around the bytecode compiler's long branch
limits which are exceeded when each case jumps around the otherwise."
opcode
caseOf: {
"Noops & Pseudo Ops"
[Label] -> [^0].
[Literal] -> [^4].
[AlignmentNops] -> [^(operands at: 0) - 4].
[Fill32] -> [^4].
[Nop] -> [^4].
"Control"
[Call] -> [^4].
[CallFull] -> [^self literalLoadInstructionBytes + 4].
[JumpR] -> [^4].
[Jump] -> [^4].
[JumpFull] -> [^self literalLoadInstructionBytes + 4].
[JumpLong] -> [^4].
[JumpZero] -> [^4].
[JumpNonZero] -> [^4].
[JumpNegative] -> [^4].
[JumpNonNegative] -> [^4].
[JumpOverflow] -> [^4].
[JumpNoOverflow] -> [^4].
[JumpCarry] -> [^4].
[JumpNoCarry] -> [^4].
[JumpLess] -> [^4].
[JumpGreaterOrEqual] -> [^4].
[JumpGreater] -> [^4].
[JumpLessOrEqual] -> [^4].
[JumpBelow] -> [^4].
[JumpAboveOrEqual] -> [^4].
[JumpAbove] -> [^4].
[JumpBelowOrEqual] -> [^4].
[JumpLongZero] -> [^4].
[JumpLongNonZero] -> [^4].
[JumpFPEqual] -> [^8].
[JumpFPNotEqual] -> [^8].
[JumpFPLess] -> [^8].
[JumpFPGreaterOrEqual]-> [^8].
[JumpFPGreater] -> [^8].
[JumpFPLessOrEqual] -> [^8].
[JumpFPOrdered] -> [^8].
[JumpFPUnordered] -> [^8].
[RetN] -> [^(operands at: 0) = 0 ifTrue: [4] ifFalse: [8]].
[Stop] -> [^4].
"Arithmetic"
[AddCqR] -> [self rotateable8bitSignedImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[AndCqR] -> [self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse:
[self literalLoadInstructionBytes = 4
ifTrue: [^ 8]
ifFalse:
[1 << (operands at: 0) highBit = ((operands at: 0) + 1)
ifTrue: [^ 8]
ifFalse: [^ self literalLoadInstructionBytes + 4]]]].
[AndCqRR] -> [self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse:
[self literalLoadInstructionBytes = 4
ifTrue: [^ 8]
ifFalse:
[1 << (operands at: 0) highBit = ((operands at: 0) + 1)
ifTrue: [^ 8]
ifFalse: [^ self literalLoadInstructionBytes + 4]]]].
[CmpCqR] -> [self rotateable8bitSignedImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[OrCqR] -> [self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[SubCqR] -> [self rotateable8bitSignedImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[TstCqR] -> [self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[XorCqR] -> [self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse:
[self literalLoadInstructionBytes = 4
ifTrue: [^ 8]
ifFalse:
[1 << (operands at: 0) highBit = ((operands at: 0) + 1)
ifTrue: [^ 8]
ifFalse: [^ self literalLoadInstructionBytes + 4]]]].
[AddCwR] -> [^self literalLoadInstructionBytes + 4].
[AndCwR] -> [^self literalLoadInstructionBytes + 4].
[CmpCwR] -> [^self literalLoadInstructionBytes + 4].
[OrCwR] -> [^self literalLoadInstructionBytes + 4].
[SubCwR] -> [^self literalLoadInstructionBytes + 4].
[XorCwR] -> [^self literalLoadInstructionBytes + 4].
[AddRR] -> [^4].
[AndRR] -> [^4].
[CmpRR] -> [^4].
[OrRR] -> [^4].
[XorRR] -> [^4].
[SubRR] -> [^4].
[NegateR] -> [^4].
[LoadEffectiveAddressMwrR]
-> [self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[LogicalShiftLeftCqR] -> [^4].
[LogicalShiftRightCqR] -> [^4].
[ArithmeticShiftRightCqR] -> [^4].
[LogicalShiftLeftRR] -> [^4].
[LogicalShiftRightRR] -> [^4].
[ArithmeticShiftRightRR] -> [^4].
[AddRdRd] -> [^4].
[CmpRdRd] -> [^4].
[SubRdRd] -> [^4].
[MulRdRd] -> [^4].
[DivRdRd] -> [^4].
[SqrtRd] -> [^4].
"ARM Specific Arithmetic"
[SMULL] -> [^4].
[MSR] -> [^4].
[CMPSMULL] -> [^4]. "special compare for genMulR:R: usage"
"ARM Specific Data Movement"
[PopLDM] -> [^4].
[PushSTM] -> [^4].
"Data Movement"
[MoveCqR] -> [self literalLoadInstructionBytes = 4
ifTrue: [^ self literalLoadInstructionBytes]
ifFalse:
[self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes]]].
[MoveCwR] -> [self literalLoadInstructionBytes = 4
ifTrue: [^ self literalLoadInstructionBytes]
ifFalse:
[(self inCurrentCompilation: (operands at: 0))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes]]].
[MoveRR] -> [^4].
[MoveRdRd] -> [^4].
[MoveAwR] -> [(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRAw] -> [(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveAbR] -> [(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRAb] -> [(self isAddressRelativeToVarBase: (operands at: 1))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRMwr] -> [self is12BitValue: (operands at: 1)
ifTrue: [:u :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRdM64r] -> [^ 4].
[MoveMbrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [:u :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRMbr] -> [self is12BitValue: (operands at: 1)
ifTrue: [:u :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveRM16r] -> [self is12BitValue: (operands at: 1)
ifTrue: [:u :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveM16rR] -> [self rotateable8bitImmediate: (operands at: 0)
ifTrue: [:r :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveM64rRd] -> [^self literalLoadInstructionBytes + 4].
[MoveMwrR] -> [self is12BitValue: (operands at: 0)
ifTrue: [:u :i| ^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
[MoveXbrRR] -> [^4].
[MoveRXbrR] -> [^4].
[MoveXwrRR] -> [^4].
[MoveRXwrR] -> [^4].
[PopR] -> [^4].
[PushR] -> [^4].
[PushCw] -> [self literalLoadInstructionBytes = 4
ifTrue: [^ self literalLoadInstructionBytes + 4]
ifFalse:
[(self inCurrentCompilation: (operands at: 0))
ifTrue: [^ 8]
ifFalse:
[self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 8]
ifFalse: [^ self literalLoadInstructionBytes + 4]]]].
[PushCq] -> [self literalLoadInstructionBytes = 4
ifTrue: [^ self literalLoadInstructionBytes + 4]
ifFalse:
[self rotateable8bitBitwiseImmediate: (operands at: 0)
ifTrue: [:r :i :n| ^ 8]
ifFalse: [^ self literalLoadInstructionBytes + 4]]].
[PrefetchAw] -> [(self isAddressRelativeToVarBase: (operands at: 0))
ifTrue: [^ 4]
ifFalse: [^ self literalLoadInstructionBytes + 4]].
"Conversion"
[ConvertRRd] -> [^8].
"This is a fixed size instruction using a literal. We need exactly 1 instructions to move a literal from a PC relative position, so this takes ALWAYS 1 instruction of 4 bytes"
[MovePatcheableC32R] -> [ ^ 4 ]
}.
^0 "to keep C compiler quiet"
]
{ #category : #accessing }
CogARMCompiler >> concreteCalleeSavedRegisterMask [
"According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1:
A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).
SP = r13, so..."
^2r0000110111110000
]
{ #category : #accessing }
CogARMCompiler >> concreteCallerSavedRegisterMask [
"According to IHI0042E ARM Architecture Procedure Calling Standard, in section 5.1.1:
A subroutine must preserve the contents of the registers r4-r8, r10, r11 and SP (and r9 in PCS variants that designate r9 as v6).
SP = r13, so the callee-saved regs are r4-r8 & r10-r12.
The caller-saved registers are those that are not callee-saved and not reserved for hardware/abi uses,
i..e r0-r3, r9 & r12."
^2r1001000001111
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeAddRdRd [
"Will get inlined into concretizeAt: switch."
<inline: true>
"Add FP regRHS to FP regLHS and stick result in FP regLHS"
| regLHS regRHS |
regRHS := operands at: 0.
regLHS := operands at: 1.
machineCode at: 0 put:(self faddd: regLHS with: regRHS).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeAlignmentNops [
<inline: true>
"fill any slots with NOPs - in this case mov r0, r0 - which is the NOP I always used to use"
self assert: machineCodeSize \\ 4 = 0.
0 to: machineCodeSize - 1 by: 4 do:
[:p| self machineCodeAt: p put: 16rE1A00000]
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeAndCqRR [
"Will get inlined into concretizeAt: switch."
"AND is very important since it's used to mask all sorts of flags in the jit. We take special care to try to find compact ways to make the masks"
<inline: true>
| val srcReg dstReg |
val := operands at: 0.
srcReg := operands at: 1.
dstReg := operands at: 2.
self rotateable8bitBitwiseImmediate: val
ifTrue:
[:rot :immediate :invert|
self machineCodeAt: 0 put: (invert
ifTrue: [self bics: dstReg rn: srcReg imm: immediate ror: rot]
ifFalse: [self ands: dstReg rn: srcReg imm: immediate ror: rot]).
^machineCodeSize := 4]
ifFalse: "let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
[| hb |
hb := (operands at: 0) highBit.
1 << hb = (val +1)
ifTrue: "MVN temp reg, 0, making 0xffffffff"
[self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then AND reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put: (self dataOpType: AndOpcode rd: dstReg rn: srcReg rm: ConcreteIPReg lsr: 32 - hb).
^machineCodeSize := 8]
ifFalse:
[^self concretizeDataOperationCwR: AndOpcode]].
^0 "to keep Slang happy"
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeArithmeticShiftRightCqR [
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, ASR #distance"
<inline: true>
| distance reg |
distance := (operands at: 0) min: 31.
reg := operands at: 1.
"cond 000 1101 0 0000 dest dist -100 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: reg
shifterOperand: (distance << 7 bitOr: (64 "flag for arithmetic" bitOr: reg))).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeArithmeticShiftRightRR [
"Will get inlined into concretizeAt: switch."
"this is an unfortunate waste of an instruction in most cases since the shift can usually be done in a subsequent arithmetic instruction.
Handle for now with a MOVS reg, reg, ASR distReg"
<inline: true>
| destReg distReg |
distReg := operands at: 0.
destReg := operands at: 1.
"cond 000 1101 0 0000 destR distR 0101 srcR"
self machineCodeAt: 0 put: (self type: 0 op: MoveOpcode set: 1 rn: 0 rd: destReg
shifterOperand: (distReg << 8 bitOr: (80 bitOr: destReg))).
^machineCodeSize := 4
]
{ #category : #'generate machine code' }
CogARMCompiler >> concretizeAt: actualAddress [
"Generate concrete machine code for the instruction at actualAddress,
setting machineCodeSize, and answer the following address."
self assert: actualAddress \\ 4 = 0.
^super concretizeAt: actualAddress
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeCMPSMULL [
"Generate a CMP a, b, ASR #31 instruction, specifically for comparing the resutls of SMULLs in genMulR:R:"
| hiReg loReg |
hiReg := operands at: 0.
loReg := operands at: 1.
self machineCodeAt: 0
put: (self type: 0 op: CmpOpcode set: 1 rn: hiReg rd: 0)
+ (31<<7) "the shift amount"
+ (2<<5) "the shift type - ASR"
+ loReg.
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeCall [
"Will get inlined into concretizeAt: switch."
<inline: true>
"Call is used only for calls within code-space, See CallFull for general anywhere in address space calling"
| offset |
self assert: (operands at: 0) ~= 0.
self assert: (operands at: 0) \\ 4 = 0.
offset := (operands at: 0) signedIntFromLong - (address + 8 "normal pc offset") signedIntFromLong.
self assert: (self isInImmediateJumpRange: offset). "+- 24Mb is plenty of range in code space"
self machineCodeAt: 0 put: (self bl: offset).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeCallFull [
"Will get inlined into concretizeAt: switch."
"Sizing/generating calls.
Jump targets can be to absolute addresses or other abstract instructions.
Generating initial trampolines instructions may have no maxSize and be to absolute addresses.
Otherwise instructions must have a machineCodeSize which must be kept to."
<inline: true>
| jumpTarget instrOffset|
<var: #jumpTarget type: #'AbstractInstruction *'>
jumpTarget := self longJumpTargetAddress.
instrOffset := self moveCw: jumpTarget intoR: ConcreteIPReg.
"blx ConcreteIPReg"
self machineCodeAt: instrOffset put: (self blx: ConcreteIPReg).
self assert: instrOffset = self literalLoadInstructionBytes.
^machineCodeSize := instrOffset + 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeCmpRdRd [
"Will get inlined into concretizeAt: switch."
<inline: true>
"Compare FP regB with FP regA and leave the FP status reg ready to be transferred back to ARM with next instruction"
| regB regA |
regA := operands at:0.
regB := operands at: 1.
machineCode at: 0 put:(self fcmpFrom: regB to: regA).
^machineCodeSize := 4
]
{ #category : #'generate machine code' }
CogARMCompiler >> concretizeConditionalInstruction [
"Concretize the current instruction, but with a condition."
<returnTypeC: #void>
| savedCond |
self assert: conditionOrNil notNil.
savedCond := conditionOrNil.
conditionOrNil := nil.
self dispatchConcretize.
conditionOrNil := savedCond.
0 to: machineCodeSize-1 by: 4 do:
[:i| | instr |
instr := (self machineCodeAt: i) bitClear: 16rF<<28.
self machineCodeAt: i put: (instr bitOr: (conditionOrNil bitAnd: 16rF)<<28)]
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeConditionalJump: conditionCode [
"Will get inlined into concretizeAt: switch."
"Sizing/generating jumps.
Jump targets can be to absolute addresses or other abstract instructions.
Generating initial trampolines instructions may have no maxSize and be to absolute addresses.
Otherwise instructions must have a machineCodeSize which must be kept to."
<inline: true>
| offset |
offset := self computeJumpTargetOffsetPlus: 8.
self assert: (self isInImmediateJumpRange: offset).
self machineCodeAt: 0 put: (self cond: conditionCode br: 0 offset: offset). "B offset"
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeConvertRRd [
"Will get inlined into concretizeAt: switch."
<inline: true>
| srcReg destReg |
srcReg := operands at:0.
destReg := operands at: 1.
machineCode at: 0 put:(self fmsrFrom: srcReg to: 9).
machineCode at: 1 put: (self fsitodFrom: 9 to: destReg). "probably not quite right"
^machineCodeSize := 8
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeDataOperationCqR: armOpcode [
"Will get inlined into concretizeAt: switch."
"4 == Add, 2 == Sub, Xor == 1, And == 0, Or == 12, Bic == 14"
<inline: true>
|val rd rn |
val := operands at: 0.
rn := operands at: 1.
rd := opcode = CmpOpcode ifTrue: [0] ifFalse:[rn]. "Extra note - if ever a version of this code wants to NOT set the Set flag - Cmp must always have it set or it will pretend to be a SMALALBT and Very Bad Things might happen"
self rotateable8bitImmediate: val
ifTrue: [:rot :immediate |
self machineCodeAt: 0 put: (self type: 1 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ((rot>>1)"in this usage we have to halve the rot value" << 8 bitOr: immediate)).
^machineCodeSize := 4]
ifFalse: ["let's try to see if the constant can be made from a simple shift of 0xFFFFFFFF"
val > 0 ifTrue: [
|hb |
hb := val highBit.
1 << hb = (val +1)
ifTrue: [ "MVN temp, #0, making 0xffffffff"
self machineCodeAt: 0 put:(self mvn: ConcreteIPReg imm: 0 ror: 0).
"Then armOpcode reg, temp reg, lsr #(32-hb)"
self machineCodeAt: 4 put:(self dataOpType: armOpcode rd: rd rn: rn rm: ConcreteIPReg lsr: (32-hb)).
^machineCodeSize :=8]].
^self concretizeDataOperationCwR: armOpcode].
^0 "to keep Slang happy"
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeDataOperationCwR: armOpcode [
"Will get inlined into concretizeAt: switch."
"Load the word into the RISCTempReg, then cmp R, RISCTempReg"
<inline: true>
| constant rn rd instrOffset|
constant := operands at: 0.
rn := operands at: 1.
rd := armOpcode = CmpOpcode ifTrue: [0] ifFalse:[rn].
instrOffset := self moveCw: constant intoR: ConcreteIPReg.
self machineCodeAt: instrOffset
put: (self type: 0 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: ConcreteIPReg).
^machineCodeSize := instrOffset + 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeDataOperationRR: armOpcode [
"Will get inlined into concretizeAt: switch."
"Load the word into the RISCTempReg, then op R, RISCTempReg"
<inline: true>
| rn rd srcReg |
srcReg := operands at: 0.
rn := operands at: 1.
rd := armOpcode = CmpOpcode ifTrue: [0] ifFalse: [rn].
self machineCodeAt: 0
put: (self type: 0 op: armOpcode set: 1 rn: rn rd: rd shifterOperand: srcReg).
^machineCodeSize := 4.
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeDivRdRd [
"Will get inlined into concretizeAt: switch."
<inline: true>
"FP divide regLHS by regRHS and stick result in regLHS"
| regLHS regRHS |
regRHS := operands at: 0.
regLHS := operands at: 1.
machineCode at: 0 put:(self fdivd: regLHS by: regRHS).
^machineCodeSize := 4
]
{ #category : #'generate machine code - concretize' }
CogARMCompiler >> concretizeFPConditionalJump: conditionCode [
"Will get inlined into concretizeAt: switch."
<inline: true>
| offset |
"transfer the FP status to ARM cpsr and then jump accordingly"
offset := self computeJumpTargetOffsetPlus: 8+4 "pc is always 2 instr ahead plus add another to refer to the actual branch".
self assert: (self isInImmediateJumpRange: offset).