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Fix result operand undef for ARM JIT as well
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Same change as 6de8b08.
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nikic committed Sep 15, 2021
1 parent 0d8bcfe commit 24082d5
Showing 1 changed file with 13 additions and 2 deletions.
15 changes: 13 additions & 2 deletions ext/opcache/jit/zend_jit_arm64.dasc
Original file line number Diff line number Diff line change
Expand Up @@ -829,6 +829,17 @@ static bool logical_immediate_p(uint64_t value, uint32_t reg_size)
| SET_Z_TYPE_INFO REG0, IS_UNDEF, tmp_reg
|.endmacro

|.macro UNDEF_OPLINE_RESULT_IF_USED, tmp_reg1, tmp_reg2
| ldr REG0, EX->opline
| ldrb tmp_reg1, OP:REG0->result_type
| TST_32_WITH_CONST tmp_reg1, (IS_TMP_VAR|IS_VAR), tmp_reg2
| beq >1
| ldr REG0w, OP:REG0->result.var
| add REG0, FP, REG0
| SET_Z_TYPE_INFO REG0, IS_UNDEF, tmp_reg1
|1:
|.endmacro

/* Floating-point comparison between register 'reg' and value from memory 'addr'.
* Note: the equivalent macros in JIT/x86 are SSE_AVX_OP and SSE_OP. */
|.macro DOUBLE_CMP, reg, addr, tmp_reg, fp_tmp_reg
Expand Down Expand Up @@ -2106,7 +2117,7 @@ static int zend_jit_undefined_function_stub(dasm_State **Dst)
static int zend_jit_negative_shift_stub(dasm_State **Dst)
{
|->negative_shift:
| UNDEF_OPLINE_RESULT TMP1w
| UNDEF_OPLINE_RESULT_IF_USED TMP1w, TMP2w
| LOAD_ADDR CARG1, zend_ce_arithmetic_error
| LOAD_ADDR CARG2, "Bit shift by negative number"
| EXT_CALL zend_throw_error, REG0
Expand All @@ -2117,7 +2128,7 @@ static int zend_jit_negative_shift_stub(dasm_State **Dst)
static int zend_jit_mod_by_zero_stub(dasm_State **Dst)
{
|->mod_by_zero:
| UNDEF_OPLINE_RESULT TMP1w
| UNDEF_OPLINE_RESULT_IF_USED TMP1w, TMP2w
| LOAD_ADDR CARG1, zend_ce_division_by_zero_error
| LOAD_ADDR CARG2, "Modulo by zero"
| EXT_CALL zend_throw_error, REG0
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