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Cleanup and automatic reset generation
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@pkerling
pkerling committed Aug 8, 2015
1 parent a9bc4b5 commit 8a9b7c3
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Showing 19 changed files with 552 additions and 410 deletions.
19 changes: 7 additions & 12 deletions Makefile
View file
@@ -1,23 +1,18 @@
# Set ISE_DIR to ISE installation directory. Example: .../14.7/ISE_DS/ISE

OPTS=--std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic
# --no-vital-checks

all:
ghdl -i --work=ethernet_mac --workdir=ghdl $(OPTS) *.vhd xilinx/*.vhd xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd
ghdl -m --work=ethernet_mac --workdir=ghdl -Pghdl/unisim -Pghdl/xilinxcorelib $(OPTS) ethernet_mac_tb

sim_posttranslate:
ghdl -i --work=ethernet_mac --workdir=ghdl $(OPTS) *_types.vhd crc32.vhd utility.vhd ethernet_mac_tb.vhd xilinx/test_wrapper_spartan6.vhd
ghdl -i --work=ethernet_mac --workdir=ghdl $(OPTS) netgen/translate/*.vhd
ghdl -m --work=ethernet_mac --workdir=ghdl -Pghdl/simprim -Pghdl/unisim -Pghdl/xilinxcorelib $(OPTS) ethernet_mac_tb

sim_postpar:
ghdl -i --work=ethernet_mac --workdir=ghdl $(OPTS) *_types.vhd crc32.vhd utility.vhd ethernet_mac_tb.vhd xilinx/test_wrapper_spartan6.vhd
ghdl -i --work=ethernet_mac --workdir=ghdl $(OPTS) netgen/par/*.vhd
ghdl -m --work=ethernet_mac --workdir=ghdl -Pghdl/simprim -Pghdl/unisim -Pghdl/xilinxcorelib $(OPTS) ethernet_mac_tb

check: all
./ethernet_mac_tb --stack-max-size=20M --ieee-asserts=disable

prepare:
mkdir -p ghdl/unisim ghdl/xilinxcorelib ghdl/simprim
mkdir -p ghdl/unisim ghdl/xilinxcorelib #ghdl/simprim
ghdl -i --work=unisim --workdir=ghdl/unisim $(OPTS) $(ISE_DIR)/vhdl/src/unisims/*.vhd
ghdl -i --work=unisim --workdir=ghdl/unisim $(OPTS) $(ISE_DIR)/vhdl/src/unisims/primitive/*.vhd
ghdl -i --work=XilinxCoreLib --workdir=ghdl/xilinxcorelib $(OPTS) $(ISE_DIR)/vhdl/src/XilinxCoreLib/*.vhd
ghdl -i --work=simprim --workdir=ghdl/simprim $(OPTS) $(ISE_DIR)/vhdl/src/simprims/simprim_Vcomponents.vhd $(ISE_DIR)/vhdl/src/simprims/simprim_Vpackage.vhd $(ISE_DIR)/vhdl/src/simprims/primitive/other/*.vhd
#ghdl -i --work=simprim --workdir=ghdl/simprim $(OPTS) $(ISE_DIR)/vhdl/src/simprims/simprim_Vcomponents.vhd $(ISE_DIR)/vhdl/src/simprims/simprim_Vpackage.vhd $(ISE_DIR)/vhdl/src/simprims/primitive/other/*.vhd
145 changes: 98 additions & 47 deletions ethernet.vhd
View file
Expand Up @@ -16,11 +16,18 @@ entity ethernet is
MIIM_PHY_ADDRESS : t_phy_address := (others => '0');
MIIM_RESET_WAIT_TICKS : natural := 0;
MIIM_POLL_WAIT_TICKS : natural := DEFAULT_POLL_WAIT_TICKS;
MIIM_CLOCK_DIVIDER : positive := 50
MIIM_CLOCK_DIVIDER : positive := 50;
-- You need to supply the current speed via speed_override when MIIM is disabled
MIIM_DISABLE : boolean := FALSE
);
port(
clock_125_i : in std_ulogic;
-- Reset input synchronous to miim_clock_i
reset_i : in std_ulogic;
-- Asynchronous reset output
-- Reset may be asserted when the speed changes to get the system
-- back to a defined state (glitches might occur on the clock)
reset_o : out std_ulogic;

-- MII (Media-independent interface)
mii_tx_clk_i : in std_ulogic;
Expand Down Expand Up @@ -50,13 +57,17 @@ entity ethernet is

-- TX from client logic
tx_clock_o : out std_ulogic;
-- Asynchronous reset that deasserts synchronously to tx_clock_o
tx_reset_o : out std_ulogic;
tx_enable_i : in std_ulogic;
tx_data_i : in t_ethernet_data;
tx_byte_sent_o : out std_ulogic;
tx_busy_o : out std_ulogic;

-- RX to client logic
rx_clock_o : out std_ulogic;
-- Asynchronous reset that deasserts synchronously to rx_clock_o
rx_reset_o : out std_ulogic;
rx_frame_o : out std_ulogic;
rx_data_o : out t_ethernet_data;
rx_byte_received_o : out std_ulogic;
Expand All @@ -68,6 +79,10 @@ architecture rtl of ethernet is
signal tx_clock : std_ulogic;
signal rx_clock : std_ulogic;

signal reset : std_ulogic := '1';
signal rx_reset : std_ulogic;
signal tx_reset : std_ulogic;

-- Interface between mii_gmii and framing
signal mac_tx_enable : std_ulogic := '0';
signal mac_tx_data : t_ethernet_data;
Expand All @@ -94,25 +109,58 @@ architecture rtl of ethernet is
signal miim_ack : std_ulogic;
signal miim_wr_en : std_ulogic;
signal miim_speed : t_ethernet_speed;
signal speed_select : t_ethernet_speed;
signal speed : t_ethernet_speed;
signal link_up : std_ulogic;
begin
tx_clock_o <= tx_clock;
rx_clock_o <= rx_clock;
reset_o <= reset;
rx_reset_o <= rx_reset;
tx_reset_o <= tx_reset;
tx_clock_o <= tx_clock;
rx_clock_o <= rx_clock;

link_up_o <= link_up;
speed_o <= speed_select;
speed_o <= speed;
miim_phy_address_sig <= MIIM_PHY_ADDRESS;
-- Errors are never transmitted in full-duplex mode
mii_tx_er_o <= '0';

with speed_override_i select speed_select <=
with speed_override_i select speed <=
miim_speed when SPEED_UNSPECIFIED,
speed_override_i when others;

-- Generate MAC reset if necessary
reset_generator_inst : entity work.reset_generator
port map(
clock_i => miim_clock_i,
speed_i => speed,
reset_i => reset_i,
reset_o => reset
);

-- Bring reset into RX and TX clock domains, using:
-- * Asynchronous assertion of reset to guarantee resetting even when the MII clock is not running
-- * Synchronous deassertion of reset to guarantee meeting the reset recovery time of the flip flops
sync_rx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => rx_clock,
preset_i => reset,
signal_i => '0',
signal_o => rx_reset
);

sync_tx_reset_inst : entity work.single_signal_synchronizer
port map(
clock_target_i => tx_clock,
preset_i => reset,
signal_i => '0',
signal_o => tx_reset
);

mii_gmii_inst : entity work.mii_gmii
port map(
reset_i => reset_i,
rx_reset_i => rx_reset,
rx_clock_i => rx_clock,
tx_reset_i => tx_reset,
tx_clock_i => tx_clock,

-- MII (Media-independent interface)
Expand All @@ -127,7 +175,7 @@ begin
rgmii_rx_ctl_i => '0',

-- Interface control signals
speed_select_i => speed_select,
speed_select_i => speed,
tx_enable_i => mac_tx_enable,
tx_data_i => mac_tx_data,
tx_byte_sent_o => mac_tx_byte_sent,
Expand All @@ -143,7 +191,7 @@ begin
clock_125_i => clock_125_i,
clock_tx_o => tx_clock,
clock_rx_o => rx_clock,
speed_select_i => speed_select,
speed_select_i => speed,
mii_tx_clk_i => mii_tx_clk_i,
mii_tx_en_o => mii_tx_en_o,
mii_txd_o => mii_txd_o,
Expand All @@ -161,8 +209,9 @@ begin

framing_inst : entity work.framing
port map(
reset_i => reset_i,
rx_reset_i => rx_reset,
tx_clock_i => tx_clock,
tx_reset_i => tx_reset,
rx_clock_i => rx_clock,
tx_enable_i => tx_enable_i,
tx_data_i => tx_data_i,
Expand All @@ -182,43 +231,45 @@ begin
mii_rx_error_i => mac_rx_error
);

miim_inst : entity work.miim
generic map(
CLOCK_DIVIDER => MIIM_CLOCK_DIVIDER
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
register_address_i => miim_register_address,
phy_address_i => miim_phy_address_sig,
data_read_o => miim_data_read,
data_write_i => miim_data_write,
req_i => miim_req,
ack_o => miim_ack,
wr_en_i => miim_wr_en,
mdc_o => mdc_o,
mdio_io => mdio_io
);
miim_gen : if MIIM_DISABLE = FALSE generate
miim_inst : entity work.miim
generic map(
CLOCK_DIVIDER => MIIM_CLOCK_DIVIDER
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
register_address_i => miim_register_address,
phy_address_i => miim_phy_address_sig,
data_read_o => miim_data_read,
data_write_i => miim_data_write,
req_i => miim_req,
ack_o => miim_ack,
wr_en_i => miim_wr_en,
mdc_o => mdc_o,
mdio_io => mdio_io
);

miim_control_inst : entity work.miim_control
generic map(
RESET_WAIT_TICKS => MIIM_RESET_WAIT_TICKS,
POLL_WAIT_TICKS => MIIM_POLL_WAIT_TICKS,
DEBUG_OUTPUT => FALSE
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
miim_register_address_o => miim_register_address,
miim_data_read_i => miim_data_read,
miim_data_write_o => miim_data_write,
miim_req_o => miim_req,
miim_ack_i => miim_ack,
miim_we_o => miim_wr_en,
link_up_o => link_up,
speed_o => miim_speed,
debug_fifo_we_o => open,
debug_fifo_write_data_o => open
);
miim_control_inst : entity work.miim_control
generic map(
RESET_WAIT_TICKS => MIIM_RESET_WAIT_TICKS,
POLL_WAIT_TICKS => MIIM_POLL_WAIT_TICKS,
DEBUG_OUTPUT => FALSE
)
port map(
reset_i => reset_i,
clock_i => miim_clock_i,
miim_register_address_o => miim_register_address,
miim_data_read_i => miim_data_read,
miim_data_write_o => miim_data_write,
miim_req_o => miim_req,
miim_ack_i => miim_ack,
miim_we_o => miim_wr_en,
link_up_o => link_up,
speed_o => miim_speed,
debug_fifo_we_o => open,
debug_fifo_write_data_o => open
);
end generate;
end architecture;

44 changes: 26 additions & 18 deletions ethernet_mac.xise
View file
Expand Up @@ -26,11 +26,11 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ethernet.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="ethernet_mac_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
Expand All @@ -40,32 +40,32 @@
<association xil_pn:name="Implementation" xil_pn:seqID="2" xil_pn:seqIDinc="5"/>
</file>
<file xil_pn:name="ethernet_with_fifos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="framing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="framing_common.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="mii_gmii.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="mii_gmii_io.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="miim.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="miim_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="miim_registers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
Expand All @@ -76,8 +76,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="1" xil_pn:seqIDinc="14"/>
</file>
<file xil_pn:name="rx_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="tx_fifo_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
Expand All @@ -100,12 +100,12 @@
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="xilinx/tx_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="xilinx/test_instance_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="xilinx/test_instance_spartan6.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
Expand All @@ -128,6 +128,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="reset_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="test_mirror.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="110"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
Expand Down

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