Implement RISC-V instruction fusion as optimization.

[lvella]

There are several common instruction sequences in RISC-V that can be optimized in the micro-architecture by "fusing" them as a single optimized implementation.

This seems a good opportunity to reduce the number of rows of powdr assembly programs translated from RISC-V. I can think of a few lui uses (also works for auipc) that could be fused:

• lui A, <address>
addi B, A, <address>
• lui A, <address>
l{w,h,b} B, <address>(A)
• lui A, <address>
s{w,h,b} B, <address>(A)

But certainly there are more, as this is RISC-V talked topic. Reference links:

• https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf
• https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-130.pdf
• https://reviews.llvm.org/D73643