Implementation is failed #82
Comments
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Huh, this is strange. Can you check the other logs (vivado.log, protosyn_logs/) under build/genesys2/system/? Did the synthesis run actually start? Which Vivado version are you using? |
thanks, the synthesis has already run, and the Vivado version is 2018.3.the vivado.log and protosyn_logs have reported the warning : |
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Did you by any chance change Vivado version while you've been trying to get protosyn to work? I'd suggest deleting |
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thanks ,the vivado version didn't change ,and I try to run by deleting build/genesys2,but it still can not work ,so the file under piton/design/chipset/xilinx/genesys2/ip_cores/clk_mmcm is as follows： |
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Hmm ok. Could you try the following: It looks kind of like Vivado created the synthesis jobs for the mmcm, brams, fifos, etc but then didn't actually run them to successful completion. I've been able to get a bit more success from it in the past when I removed any .xml and .dcp files from the genesys2/ip_cores/ subdirectories before. Let me know if this helps! |
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thanks, I try to remove this xml and .dcp files many times, but it still donsen't work . |
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Ok could you give it a try on a clean clone of the repo? Now that you have the other dependencies set up maybe that would help? It really looks like it doesn't run the synthesis jobs for the IPs. One thing you could also try is to open the genesys2_system.xpr in the Vivado GUI and run synthesis of the IPs as out-of-context jobs yourself. |
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thanks, the problem have been found when i open the genesys2_system.xpr in the Vivado GUI. the IP license has expired, so I apply the new license,and the Implementation is passed. |
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Ah that's interesting. Good to note for future! I'll close this for now :) |
when i run protosyn -b genesys2 -d system --core=ariane --uart-dmw ddr which crashes with the following output:
[INFO] protosyn,2.5:702: ----- System Configuration -----
[INFO] protosyn,2.5:720: x_tiles = 1
[INFO] protosyn,2.5:721: y_tiles = 1
[INFO] protosyn,2.5:722: num_tiles = 1
[INFO] protosyn,2.5:729: core = ariane
[INFO] protosyn,2.5:732: defining RTL_TILE0
[INFO] protosyn,2.5:762: setenv RTL_ARIANE0
[INFO] protosyn,2.5:780: network = 2dmesh_config
[INFO] protosyn,2.5:784: l15 size = 8192
[INFO] protosyn,2.5:785: l15 assoc = 4
[INFO] protosyn,2.5:786: l1d size = 8192
[INFO] protosyn,2.5:787: l1d assoc = 4
[INFO] protosyn,2.5:788: l1i size = 16384
[INFO] protosyn,2.5:789: l1i assoc = 4
[INFO] protosyn,2.5:790: l2 size = 65536
[INFO] protosyn,2.5:791: l2 assoc = 4
[INFO] protosyn,2.5:805: ---- Additional RTL Defines ----
[INFO] protosyn,2.5:808: NO_RTL_CSM
[INFO] protosyn,2.5:808: PITON_FPGA_MC_DDR3
[INFO] protosyn,2.5:808: PITONSYS_MEM_ZEROER
[INFO] protosyn,2.5:808: PITON_FPGA_SD_BOOT
[INFO] protosyn,2.5:808: PITONSYS_UART_BOOT
[INFO] protosyn,2.5:808: PITON_NO_CHIP_BRIDGE
[INFO] protosyn,2.5:808: PITON_UART16550
[INFO] protosyn,2.5:808: PITON_FPGA_ETHERNETLITE
[INFO] protosyn,2.5:810: --------------------------------
[INFO] protosyn,2.5:879: Generating UART init sequence
[INFO] protosyn,2.5:631: Using core clock frequency: 66.667 MHz
[INFO] protosyn,2.5:285: Building a project for design 'system' on board 'genesys2'
[INFO] protosyn,2.5:330: Running FPGA implementation down to bitstream generation
[INFO] protosyn,2.5:932: Checking Project Build results
[INFO] fpga_lib.py:348: Project was build successfully!
[INFO] protosyn,2.5:939: Checking Project Implementation results
Traceback (most recent call last):
File "/home/shancheng/PITON_ROOT/piton/tools/src/proto/protosyn,2.5", line 949, in
main()
File "/home/shancheng/PITON_ROOT/piton/tools/src/proto/protosyn,2.5", line 940, in main
if not implFlowSuccess(rc_dir.log, rc_dir.run):
File "/home/shancheng/PITON_ROOT/piton/tools/src/proto/fpga_lib.py", line 365, in implFlowSuccess
if not strInFile(fpath, ["synth_design completed successfully"]):
File "/home/shancheng/PITON_ROOT/piton/tools/src/proto/fpga_lib.py", line 330, in strInFile
f = open(fpath, 'r')
FileNotFoundError: [Errno 2] No such file or directory: '/home/shancheng/PITON_ROOT/build/genesys2/system/genesys2_system/genesys2_system.runs/synth_1/runme.log'
so i dont konw why runme.log was deleted, how to find the reason， if anyone has an idea, please help me .
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