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vlapic.c
2526 lines (2153 loc) · 57.1 KB
/
vlapic.c
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/*-
* Copyright (c) 2011 NetApp, Inc.
* Copyright (c) 2017 Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#define pr_prefix "vlapic: "
#include <hypervisor.h>
#include "instr_emul.h"
#include "vlapic_priv.h"
#include "vlapic.h"
#define VLAPIC_VERBOS 0
#define PRIO(x) ((x) >> 4)
#define VLAPIC_VERSION (16U)
#define APICBASE_RESERVED 0x000002ffU
#define APICBASE_BSP 0x00000100U
#define APICBASE_X2APIC 0x00000400U
#define APICBASE_ENABLED 0x00000800U
#define ACRN_DBG_LAPIC 6U
#if VLAPIC_VERBOS
static inline void vlapic_dump_irr(struct acrn_vlapic *vlapic, char *msg)
{
uint32_t i;
struct lapic_reg *irrptr = &(vlapic)->apic_page->irr[0];
for (i = 0U; i < 8U; i++)
dev_dbg(ACRN_DBG_LAPIC, "%s irr%u 0x%08x",
msg, i, irrptr[i].val);
}
static inline void vlapic_dump_isr(struct acrn_vlapic *vlapic, char *msg)
{
uint32_t i;
struct lapic_reg *isrptr = &(vlapic)->apic_page->isr[0];
for (i = 0U; i < 8U; i++) {
dev_dbg(ACRN_DBG_LAPIC, "%s isr%u 0x%08x",
msg, i, isrptr[0].val);
}
}
#else
#define vlapic_dump_irr(vlapic, msg)
#define vlapic_dump_isr(vlapic, msg)
#endif
/*APIC-v APIC-access address */
static void *apicv_apic_access_addr;
static int
apicv_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level);
static int
apicv_pending_intr(struct acrn_vlapic *vlapic, __unused uint32_t *vecptr);
static void
apicv_set_tmr(struct acrn_vlapic *vlapic, uint32_t vector, bool level);
static void
apicv_batch_set_tmr(struct acrn_vlapic *vlapic);
/*
* Post an interrupt to the vcpu running on 'hostcpu'. This will use a
* hardware assist if available (e.g. Posted Interrupt) or fall back to
* sending an 'ipinum' to interrupt the 'hostcpu'.
*/
static void vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask);
static int vlapic_timer_expired(void *data);
static struct acrn_vlapic *
vm_lapic_from_vcpu_id(struct vm *vm, uint16_t vcpu_id)
{
struct vcpu *vcpu;
vcpu = vcpu_from_vid(vm, vcpu_id);
ASSERT(vcpu != NULL, "vm%d, vcpu%hu", vm->vm_id, vcpu_id);
return vcpu->arch_vcpu.vlapic;
}
struct acrn_vlapic *
vm_lapic_from_pcpuid(struct vm *vm, uint16_t pcpu_id)
{
struct vcpu *vcpu;
vcpu = vcpu_from_pid(vm, pcpu_id);
ASSERT(vcpu != NULL, "vm%d, pcpu%hu", vm->vm_id, pcpu_id);
return vcpu->arch_vcpu.vlapic;
}
static uint16_t vm_apicid2vcpu_id(struct vm *vm, uint8_t lapicid)
{
uint16_t i;
struct vcpu *vcpu;
foreach_vcpu(i, vm, vcpu) {
struct acrn_vlapic *vlapic = vcpu->arch_vcpu.vlapic;
if (vlapic_get_apicid(vlapic) == lapicid) {
return vcpu->vcpu_id;
}
}
pr_err("%s: bad lapicid %hhu", __func__, lapicid);
return phys_cpu_num;
}
static uint64_t
vm_active_cpus(struct vm *vm)
{
uint64_t dmask = 0UL;
uint16_t i;
struct vcpu *vcpu;
foreach_vcpu(i, vm, vcpu) {
bitmap_set_lock(vcpu->vcpu_id, &dmask);
}
return dmask;
}
uint32_t
vlapic_get_id(struct acrn_vlapic *vlapic)
{
uint32_t id = vlapic->apic_page->id;
return id;
}
uint8_t
vlapic_get_apicid(struct acrn_vlapic *vlapic)
{
uint32_t apicid = vlapic->apic_page->id >> APIC_ID_SHIFT;
return (uint8_t)apicid;
}
static inline uint32_t
vlapic_build_id(struct acrn_vlapic *vlapic)
{
struct vcpu *vcpu = vlapic->vcpu;
uint8_t vlapic_id;
uint32_t lapic_regs_id;
if (is_vm0(vcpu->vm)) {
/* Get APIC ID sequence format from cpu_storage */
vlapic_id = per_cpu(lapic_id, vcpu->vcpu_id);
} else {
vlapic_id = (uint8_t)vcpu->vcpu_id;
}
lapic_regs_id = vlapic_id << APIC_ID_SHIFT;
dev_dbg(ACRN_DBG_LAPIC, "vlapic APIC PAGE ID : 0x%08x", lapic_regs_id);
return lapic_regs_id;
}
static void
vlapic_dfr_write_handler(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic;
lapic = vlapic->apic_page;
lapic->dfr &= APIC_DFR_MODEL_MASK;
lapic->dfr |= APIC_DFR_RESERVED;
if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_FLAT) {
dev_dbg(ACRN_DBG_LAPIC, "vlapic DFR in Flat Model");
} else if ((lapic->dfr & APIC_DFR_MODEL_MASK) == APIC_DFR_MODEL_CLUSTER) {
dev_dbg(ACRN_DBG_LAPIC, "vlapic DFR in Cluster Model");
} else {
dev_dbg(ACRN_DBG_LAPIC, "DFR in Unknown Model %#x", lapic->dfr);
}
}
static void
vlapic_ldr_write_handler(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic;
lapic = vlapic->apic_page;
lapic->ldr &= ~APIC_LDR_RESERVED;
dev_dbg(ACRN_DBG_LAPIC, "vlapic LDR set to %#x", lapic->ldr);
}
static void
vlapic_id_write_handler(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic;
/*
* We don't allow the ID register to be modified so reset it back to
* its default value.
*/
lapic = vlapic->apic_page;
lapic->id = vlapic_get_id(vlapic);
}
static inline uint32_t
vlapic_timer_divisor_shift(uint32_t dcr)
{
uint32_t val;
val = ((dcr & 0x3U) | ((dcr & 0x8U) >> 1U));
return ((val + 1U) & 0x7U);
}
static inline bool
vlapic_lvtt_oneshot(struct acrn_vlapic *vlapic)
{
return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
== APIC_LVTT_TM_ONE_SHOT);
}
static inline bool
vlapic_lvtt_period(struct acrn_vlapic *vlapic)
{
return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
== APIC_LVTT_TM_PERIODIC);
}
static inline bool
vlapic_lvtt_tsc_deadline(struct acrn_vlapic *vlapic)
{
return ((vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_TM)
== APIC_LVTT_TM_TSCDLT);
}
static inline bool
vlapic_lvtt_masked(struct acrn_vlapic *vlapic)
{
return (vlapic->apic_page->lvt[APIC_LVT_TIMER].val & APIC_LVTT_M) != 0U;
}
static void vlapic_create_timer(struct acrn_vlapic *vlapic)
{
struct vlapic_timer *vtimer;
if (vlapic == NULL) {
return;
}
vtimer = &vlapic->vtimer;
(void)memset(vtimer, 0U, sizeof(struct vlapic_timer));
initialize_timer(&vtimer->timer,
vlapic_timer_expired, vlapic->vcpu,
0UL, 0, 0UL);
}
static void vlapic_reset_timer(struct acrn_vlapic *vlapic)
{
struct hv_timer *timer;
if (vlapic == NULL) {
return;
}
timer = &vlapic->vtimer.timer;
del_timer(timer);
timer->mode = 0;
timer->fire_tsc = 0UL;
timer->period_in_cycle = 0UL;
}
static bool
set_expiration(struct acrn_vlapic *vlapic)
{
uint64_t now = rdtsc();
uint64_t delta;
struct vlapic_timer *vtimer;
struct hv_timer *timer;
uint32_t tmicr, divisor_shift;
vtimer = &vlapic->vtimer;
tmicr = vtimer->tmicr;
divisor_shift = vtimer->divisor_shift;
if (!tmicr || (divisor_shift > 8U)) {
return false;
}
delta = tmicr << divisor_shift;
timer = &vtimer->timer;
if (vlapic_lvtt_period(vlapic)) {
timer->period_in_cycle = delta;
}
timer->fire_tsc = now + delta;
return true;
}
static void vlapic_update_lvtt(struct acrn_vlapic *vlapic,
uint32_t val)
{
uint32_t timer_mode = val & APIC_LVTT_TM;
struct vlapic_timer *vtimer = &vlapic->vtimer;
if (vtimer->mode != timer_mode) {
struct hv_timer *timer = &vtimer->timer;
/*
* A write to the LVT Timer Register that changes
* the timer mode disarms the local APIC timer.
*/
del_timer(timer);
timer->mode = (timer_mode == APIC_LVTT_TM_PERIODIC) ?
TICK_MODE_PERIODIC: TICK_MODE_ONESHOT;
timer->fire_tsc = 0UL;
timer->period_in_cycle = 0UL;
vtimer->mode = timer_mode;
}
}
static uint32_t vlapic_get_ccr(struct acrn_vlapic *vlapic)
{
uint64_t now = rdtsc();
uint32_t remain_count = 0U;
struct vlapic_timer *vtimer;
vtimer = &vlapic->vtimer;
if (vtimer->tmicr && !vlapic_lvtt_tsc_deadline(vlapic)) {
uint64_t fire_tsc = vtimer->timer.fire_tsc;
if (now < fire_tsc) {
uint32_t divisor_shift = vtimer->divisor_shift;
uint64_t shifted_delta =
(fire_tsc - now) >> divisor_shift;
remain_count = (uint32_t)shifted_delta;
}
}
return remain_count;
}
static void vlapic_dcr_write_handler(struct acrn_vlapic *vlapic)
{
uint32_t divisor_shift;
struct vlapic_timer *vtimer;
struct lapic_regs *lapic = vlapic->apic_page;
vtimer = &vlapic->vtimer;
divisor_shift = vlapic_timer_divisor_shift(lapic->dcr_timer);
vtimer->divisor_shift = divisor_shift;
}
static void vlapic_icrtmr_write_handler(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic;
struct vlapic_timer *vtimer;
if (vlapic_lvtt_tsc_deadline(vlapic)) {
return;
}
lapic = vlapic->apic_page;
vtimer = &vlapic->vtimer;
vtimer->tmicr = lapic->icr_timer;
del_timer(&vtimer->timer);
if (set_expiration(vlapic)) {
add_timer(&vtimer->timer);
}
}
static uint64_t vlapic_get_tsc_deadline_msr(struct acrn_vlapic *vlapic)
{
if (!vlapic_lvtt_tsc_deadline(vlapic)) {
return 0;
}
return (vlapic->vtimer.timer.fire_tsc == 0UL) ? 0UL :
vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE];
}
static void vlapic_set_tsc_deadline_msr(struct acrn_vlapic *vlapic,
uint64_t val_arg)
{
struct hv_timer *timer;
uint64_t val = val_arg;
if (!vlapic_lvtt_tsc_deadline(vlapic)) {
return;
}
vlapic->vcpu->guest_msrs[IDX_TSC_DEADLINE] = val;
timer = &vlapic->vtimer.timer;
del_timer(timer);
if (val != 0UL) {
struct vcpu_arch *arch = &vlapic->vcpu->arch_vcpu;
/* transfer guest tsc to host tsc */
val -= exec_vmread64(VMX_TSC_OFFSET_FULL);
timer->fire_tsc = val;
add_timer(timer);
} else {
timer->fire_tsc = 0UL;
}
}
static void
vlapic_esr_write_handler(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic;
lapic = vlapic->apic_page;
lapic->esr = vlapic->esr_pending;
vlapic->esr_pending = 0U;
}
/*
* Returns 1 if the vcpu needs to be notified of the interrupt and 0 otherwise.
*/
static int
vlapic_set_intr_ready(struct acrn_vlapic *vlapic, uint32_t vector, bool level)
{
struct lapic_regs *lapic;
struct lapic_reg *irrptr, *tmrptr;
uint32_t mask;
uint32_t idx;
ASSERT(vector <= NR_MAX_VECTOR,
"invalid vector %u", vector);
lapic = vlapic->apic_page;
if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
dev_dbg(ACRN_DBG_LAPIC,
"vlapic is software disabled, ignoring interrupt %u",
vector);
return 0;
}
if (vector < 16U) {
vlapic_set_error(vlapic, APIC_ESR_RECEIVE_ILLEGAL_VECTOR);
dev_dbg(ACRN_DBG_LAPIC,
"vlapic ignoring interrupt to vector %u", vector);
return 1;
}
if (vlapic->ops.apicv_set_intr_ready_fn != NULL) {
return vlapic->ops.apicv_set_intr_ready_fn
(vlapic, vector, level);
}
idx = vector / 32U;
mask = 1U << (vector % 32U);
irrptr = &lapic->irr[0];
/* If the interrupt is set, don't try to do it again */
if (bitmap32_test_and_set_lock((uint16_t)(vector % 32U), &irrptr[idx].val)) {
return 0;
}
/*
* Verify that the trigger-mode of the interrupt matches with
* the vlapic TMR registers.
*/
tmrptr = &lapic->tmr[0];
if ((tmrptr[idx].val & mask) != (level ? mask : 0U)) {
dev_dbg(ACRN_DBG_LAPIC,
"vlapic TMR[%u] is 0x%08x but interrupt is %s-triggered",
idx, tmrptr[idx].val, level ? "level" : "edge");
}
vlapic_dump_irr(vlapic, "vlapic_set_intr_ready");
return 1;
}
static inline uint32_t
lvt_off_to_idx(uint32_t offset)
{
uint32_t index = ~0U;
switch (offset) {
case APIC_OFFSET_CMCI_LVT:
index = APIC_LVT_CMCI;
break;
case APIC_OFFSET_TIMER_LVT:
index = APIC_LVT_TIMER;
break;
case APIC_OFFSET_THERM_LVT:
index = APIC_LVT_THERMAL;
break;
case APIC_OFFSET_PERF_LVT:
index = APIC_LVT_PMC;
break;
case APIC_OFFSET_LINT0_LVT:
index = APIC_LVT_LINT0;
break;
case APIC_OFFSET_LINT1_LVT:
index = APIC_LVT_LINT1;
break;
case APIC_OFFSET_ERROR_LVT:
index = APIC_LVT_ERROR;
break;
default:
/*
* For the offset that is not handled (an invalid offset of
* Local Vector Table), its index is assigned to a default
* value, which indicates an invalid index.
* The index will be checked later to guarantee the validity.
*/
break;
}
ASSERT(index <= VLAPIC_MAXLVT_INDEX,
"%s: invalid lvt index %u for offset %#x",
__func__, index, offset);
return index;
}
static inline uint32_t *
vlapic_get_lvtptr(struct acrn_vlapic *vlapic, uint32_t offset)
{
struct lapic_regs *lapic = vlapic->apic_page;
uint32_t i;
switch (offset) {
case APIC_OFFSET_CMCI_LVT:
return &lapic->lvt_cmci;
case APIC_OFFSET_TIMER_LVT:
case APIC_OFFSET_THERM_LVT:
case APIC_OFFSET_PERF_LVT:
case APIC_OFFSET_LINT0_LVT:
case APIC_OFFSET_LINT1_LVT:
case APIC_OFFSET_ERROR_LVT:
i = lvt_off_to_idx(offset);
return &(lapic->lvt[i].val);
default:
panic("vlapic_get_lvt: invalid LVT\n");
}
}
static inline uint32_t
vlapic_get_lvt(struct acrn_vlapic *vlapic, uint32_t offset)
{
uint32_t idx, val;
idx = lvt_off_to_idx(offset);
val = atomic_load32(&vlapic->lvt_last[idx]);
return val;
}
static void
vlapic_lvt_write_handler(struct acrn_vlapic *vlapic, uint32_t offset)
{
uint32_t *lvtptr, mask, val, idx;
struct lapic_regs *lapic;
lapic = vlapic->apic_page;
lvtptr = vlapic_get_lvtptr(vlapic, offset);
val = *lvtptr;
idx = lvt_off_to_idx(offset);
if ((lapic->svr & APIC_SVR_ENABLE) == 0U) {
val |= APIC_LVT_M;
}
mask = APIC_LVT_M | APIC_LVT_DS | APIC_LVT_VECTOR;
switch (offset) {
case APIC_OFFSET_TIMER_LVT:
mask |= APIC_LVTT_TM;
break;
case APIC_OFFSET_ERROR_LVT:
break;
case APIC_OFFSET_LINT0_LVT:
case APIC_OFFSET_LINT1_LVT:
mask |= APIC_LVT_TM | APIC_LVT_RIRR | APIC_LVT_IIPP;
/* FALLTHROUGH */
default:
mask |= APIC_LVT_DM;
break;
}
val &= mask;
/* vlapic mask/unmask LINT0 for ExtINT? */
if ((offset == APIC_OFFSET_LINT0_LVT) &&
((val & APIC_LVT_DM) == APIC_LVT_DM_EXTINT)) {
uint32_t last = vlapic_get_lvt(vlapic, offset);
/* mask -> unmask: may from every vlapic in the vm */
if (((last & APIC_LVT_M) != 0U) && ((val & APIC_LVT_M) == 0U)) {
if ((vlapic->vm->wire_mode == VPIC_WIRE_INTR) ||
(vlapic->vm->wire_mode == VPIC_WIRE_NULL)) {
vlapic->vm->wire_mode = VPIC_WIRE_LAPIC;
dev_dbg(ACRN_DBG_LAPIC,
"vpic wire mode -> LAPIC");
} else {
pr_err("WARNING:invalid vpic wire mode change");
return;
}
/* unmask -> mask: only from the vlapic LINT0-ExtINT enabled */
} else if (((last & APIC_LVT_M) == 0U) && ((val & APIC_LVT_M) != 0U)) {
if (vlapic->vm->wire_mode == VPIC_WIRE_LAPIC) {
vlapic->vm->wire_mode = VPIC_WIRE_NULL;
dev_dbg(ACRN_DBG_LAPIC,
"vpic wire mode -> NULL");
}
} else {
/* APIC_LVT_M unchanged. No action required. */
}
} else if (offset == APIC_OFFSET_TIMER_LVT) {
vlapic_update_lvtt(vlapic, val);
} else {
/* No action required. */
}
*lvtptr = val;
atomic_store32(&vlapic->lvt_last[idx], val);
}
static void
vlapic_mask_lvts(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic = vlapic->apic_page;
lapic->lvt_cmci |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_CMCI_LVT);
lapic->lvt[APIC_LVT_TIMER].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_TIMER_LVT);
lapic->lvt[APIC_LVT_THERMAL].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_THERM_LVT);
lapic->lvt[APIC_LVT_PMC].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_PERF_LVT);
lapic->lvt[APIC_LVT_LINT0].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT0_LVT);
lapic->lvt[APIC_LVT_LINT1].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_LINT1_LVT);
lapic->lvt[APIC_LVT_ERROR].val |= APIC_LVT_M;
vlapic_lvt_write_handler(vlapic, APIC_OFFSET_ERROR_LVT);
}
static int
vlapic_fire_lvt(struct acrn_vlapic *vlapic, uint32_t lvt)
{
uint32_t vec, mode;
struct vcpu *vcpu = vlapic->vcpu;
if ((lvt & APIC_LVT_M) != 0U) {
return 0;
}
vec = lvt & APIC_LVT_VECTOR;
mode = lvt & APIC_LVT_DM;
switch (mode) {
case APIC_LVT_DM_FIXED:
if (vec < 16U) {
vlapic_set_error(vlapic, APIC_ESR_SEND_ILLEGAL_VECTOR);
return 0;
}
if (vlapic_set_intr_ready(vlapic, vec, false) != 0) {
vcpu_make_request(vcpu, ACRN_REQUEST_EVENT);
}
break;
case APIC_LVT_DM_NMI:
vcpu_inject_nmi(vcpu);
break;
case APIC_LVT_DM_EXTINT:
vcpu_inject_extint(vcpu);
break;
default:
/* Other modes ignored */
return 0;
}
return 1;
}
static void
dump_isrvec_stk(struct acrn_vlapic *vlapic)
{
uint32_t i;
struct lapic_reg *isrptr;
isrptr = &vlapic->apic_page->isr[0];
for (i = 0U; i < 8U; i++) {
printf("ISR%u 0x%08x\n", i, isrptr[i].val);
}
for (i = 0U; i <= vlapic->isrvec_stk_top; i++) {
printf("isrvec_stk[%u] = %hhu\n", i, vlapic->isrvec_stk[i]);
}
}
/*
* Algorithm adopted from section "Interrupt, Task and Processor Priority"
* in Intel Architecture Manual Vol 3a.
*/
static void
vlapic_update_ppr(struct acrn_vlapic *vlapic)
{
uint32_t top_isrvec;
uint32_t tpr, ppr;
/*
* Note that the value on the stack at index 0 is always 0.
*
* This is a placeholder for the value of ISRV when none of the
* bits is set in the ISRx registers.
*/
top_isrvec = (uint32_t)vlapic->isrvec_stk[vlapic->isrvec_stk_top];
tpr = vlapic->apic_page->tpr;
/* update ppr */
{
int32_t lastprio, curprio;
struct lapic_reg *isrptr;
uint32_t i, idx, vector;
uint32_t isrvec;
if ((vlapic->isrvec_stk_top == 0U) && (top_isrvec != 0U)) {
panic("isrvec_stk is corrupted: %u", top_isrvec);
}
/*
* Make sure that the priority of the nested interrupts is
* always increasing.
*/
lastprio = -1;
for (i = 1U; i <= vlapic->isrvec_stk_top; i++) {
isrvec = (uint32_t)vlapic->isrvec_stk[i];
curprio = (int32_t)PRIO(isrvec);
if (curprio <= lastprio) {
dump_isrvec_stk(vlapic);
panic("isrvec_stk does not satisfy invariant");
}
lastprio = curprio;
}
/*
* Make sure that each bit set in the ISRx registers has a
* corresponding entry on the isrvec stack.
*/
i = 1U;
isrptr = &vlapic->apic_page->isr[0];
for (vector = 0U; vector < 256U; vector++) {
idx = vector / 32U;
if ((isrptr[idx].val & (1U << (vector % 32U))) != 0U) {
isrvec = (uint32_t)vlapic->isrvec_stk[i];
if ((i > vlapic->isrvec_stk_top) ||
((i < ISRVEC_STK_SIZE) &&
(isrvec != vector))) {
dump_isrvec_stk(vlapic);
panic("ISR and isrvec_stk out of sync");
}
i++;
}
}
}
if (PRIO(tpr) >= PRIO(top_isrvec)) {
ppr = tpr;
} else {
ppr = top_isrvec & 0xf0U;
}
vlapic->apic_page->ppr = ppr;
dev_dbg(ACRN_DBG_LAPIC, "%s 0x%02x", __func__, ppr);
}
static void
vlapic_process_eoi(struct acrn_vlapic *vlapic)
{
struct lapic_regs *lapic = vlapic->apic_page;
struct lapic_reg *isrptr, *tmrptr;
uint32_t i, vector, bitpos;
isrptr = &lapic->isr[0];
tmrptr = &lapic->tmr[0];
/* i ranges effectively from 7 to 0 */
for (i = 8U; i > 0U; ) {
i--;
bitpos = (uint32_t)fls32(isrptr[i].val);
if (bitpos != INVALID_BIT_INDEX) {
if (vlapic->isrvec_stk_top == 0U) {
panic("invalid vlapic isrvec_stk_top %u",
vlapic->isrvec_stk_top);
}
isrptr[i].val &= ~(1U << bitpos);
vector = (i * 32U) + bitpos;
dev_dbg(ACRN_DBG_LAPIC, "EOI vector %u", vector);
vlapic_dump_isr(vlapic, "vlapic_process_eoi");
vlapic->isrvec_stk_top--;
vlapic_update_ppr(vlapic);
if ((tmrptr[i].val & (1U << bitpos)) != 0U) {
/* hook to vIOAPIC */
vioapic_process_eoi(vlapic->vm, vector);
}
return;
}
}
dev_dbg(ACRN_DBG_LAPIC, "Gratuitous EOI");
}
static void
vlapic_set_error(struct acrn_vlapic *vlapic, uint32_t mask)
{
uint32_t lvt;
vlapic->esr_pending |= mask;
if (vlapic->esr_firing != 0) {
return;
}
vlapic->esr_firing = 1;
/* The error LVT always uses the fixed delivery mode. */
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT);
vlapic_fire_lvt(vlapic, lvt | APIC_LVT_DM_FIXED);
vlapic->esr_firing = 0;
}
static int
vlapic_trigger_lvt(struct acrn_vlapic *vlapic, uint32_t vector)
{
uint32_t lvt;
struct vcpu *vcpu = vlapic->vcpu;
if (vlapic_enabled(vlapic) == false) {
/*
* When the local APIC is global/hardware disabled,
* LINT[1:0] pins are configured as INTR and NMI pins,
* respectively.
*/
switch (vector) {
case APIC_LVT_LINT0:
vcpu_inject_extint(vcpu);
break;
case APIC_LVT_LINT1:
vcpu_inject_nmi(vcpu);
break;
default:
/*
* Only LINT[1:0] pins will be handled here.
* Gracefully return if prior case clauses have not
* been met.
*/
break;
}
return 0;
}
switch (vector) {
case APIC_LVT_LINT0:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT0_LVT);
break;
case APIC_LVT_LINT1:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_LINT1_LVT);
break;
case APIC_LVT_TIMER:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
lvt |= APIC_LVT_DM_FIXED;
break;
case APIC_LVT_ERROR:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_ERROR_LVT);
lvt |= APIC_LVT_DM_FIXED;
break;
case APIC_LVT_PMC:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_PERF_LVT);
break;
case APIC_LVT_THERMAL:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_THERM_LVT);
break;
case APIC_LVT_CMCI:
lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_CMCI_LVT);
break;
default:
return -EINVAL;
}
vlapic_fire_lvt(vlapic, lvt);
return 0;
}
/*
* This function populates 'dmask' with the set of vcpus that match the
* addressing specified by the (dest, phys, lowprio) tuple.
*/
static void
vlapic_calcdest(struct vm *vm, uint64_t *dmask, uint32_t dest,
bool phys, bool lowprio)
{
struct acrn_vlapic *vlapic;
struct acrn_vlapic *target = NULL;
uint32_t dfr, ldr, ldest, cluster;
uint32_t mda_flat_ldest, mda_cluster_ldest, mda_ldest, mda_cluster_id;
uint64_t amask;
uint16_t vcpu_id;
if (dest == 0xffU) {
/*
* Broadcast in both logical and physical modes.
*/
*dmask = vm_active_cpus(vm);
return;
}
if (phys) {
/*
* Physical mode: destination is LAPIC ID.
*/
*dmask = 0UL;
vcpu_id = vm_apicid2vcpu_id(vm, (uint8_t)dest);
if (vcpu_id < phys_cpu_num) {
bitmap_set_lock(vcpu_id, dmask);
}
} else {
/*
* In the "Flat Model" the MDA is interpreted as an 8-bit wide
* bitmask. This model is only available in the xAPIC mode.
*/
mda_flat_ldest = dest & 0xffU;
/*
* In the "Cluster Model" the MDA is used to identify a
* specific cluster and a set of APICs in that cluster.
*/
mda_cluster_id = (dest >> 4) & 0xfU;
mda_cluster_ldest = dest & 0xfU;
/*
* Logical mode: match each APIC that has a bit set
* in its LDR that matches a bit in the ldest.
*/
*dmask = 0UL;
amask = vm_active_cpus(vm);
for (vcpu_id = ffs64(amask); vcpu_id != INVALID_BIT_INDEX;
vcpu_id = ffs64(amask)) {
bitmap_clear_lock(vcpu_id, &amask);
vlapic = vm_lapic_from_vcpu_id(vm, vcpu_id);
dfr = vlapic->apic_page->dfr;
ldr = vlapic->apic_page->ldr;
if ((dfr & APIC_DFR_MODEL_MASK) ==
APIC_DFR_MODEL_FLAT) {
ldest = ldr >> 24;
mda_ldest = mda_flat_ldest;
} else if ((dfr & APIC_DFR_MODEL_MASK) ==
APIC_DFR_MODEL_CLUSTER) {
cluster = ldr >> 28;
ldest = (ldr >> 24) & 0xfU;
if (cluster != mda_cluster_id) {
continue;
}
mda_ldest = mda_cluster_ldest;
} else {
/*
* Guest has configured a bad logical
* model for this vcpu - skip it.
*/
dev_dbg(ACRN_DBG_LAPIC,
"CANNOT deliver interrupt");
dev_dbg(ACRN_DBG_LAPIC,