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hv: cpu: add cpu_has_cap() API
Add cpu_has_cap API for cpu feature/capability detect instead of add get_xxx_cap for each feature/capability detect. Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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5 files changed

+129
-32
lines changed

5 files changed

+129
-32
lines changed

‎hypervisor/arch/x86/cpu.c

Lines changed: 12 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -94,25 +94,20 @@ static void start_cpus(void);
9494
static void pcpu_sync_sleep(unsigned long *sync, int mask_bit);
9595
int ibrs_type;
9696

97-
static inline bool get_tsc_adjust_cap(void)
97+
inline bool cpu_has_cap(uint32_t bit)
9898
{
99-
return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EBX] & CPUID_EBX_TSC_ADJ);
100-
}
99+
int feat_idx = bit >> 5;
100+
int feat_bit = bit & 0x1f;
101101

102-
static inline bool get_ibrs_ibpb_cap(void)
103-
{
104-
return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX] &
105-
CPUID_EDX_IBRS_IBPB);
106-
}
102+
if (feat_idx >= FEATURE_WORDS)
103+
return false;
107104

108-
static inline bool get_stibp_cap(void)
109-
{
110-
return !!(boot_cpu_data.cpuid_leaves[FEAT_7_0_EDX] & CPUID_EDX_STIBP);
105+
return !!(boot_cpu_data.cpuid_leaves[feat_idx] & (1 << feat_bit));
111106
}
112107

113108
static inline bool get_monitor_cap(void)
114109
{
115-
if (boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_MONITOR) {
110+
if (cpu_has_cap(X86_FEATURE_MONITOR)) {
116111
/* don't use monitor for CPU (family: 0x6 model: 0x5c)
117112
* in hypervisor, but still expose it to the guests and
118113
* let them handle it correctly
@@ -124,11 +119,6 @@ static inline bool get_monitor_cap(void)
124119
return false;
125120
}
126121

127-
inline bool get_vmx_cap(void)
128-
{
129-
return !!(boot_cpu_data.cpuid_leaves[FEAT_1_ECX] & CPUID_ECX_VMX);
130-
}
131-
132122
static uint64_t get_address_mask(uint8_t limit)
133123
{
134124
return ((1ULL << limit) - 1) & CPU_PAGE_MASK;
@@ -198,9 +188,9 @@ static void get_cpu_capabilities(void)
198188
* should be set all the time instead of relying on retpoline
199189
*/
200190
#ifndef CONFIG_RETPOLINE
201-
if (get_ibrs_ibpb_cap()) {
191+
if (cpu_has_cap(X86_FEATURE_IBRS_IBPB)) {
202192
ibrs_type = IBRS_RAW;
203-
if (get_stibp_cap())
193+
if (cpu_has_cap(X86_FEATURE_STIBP))
204194
ibrs_type = IBRS_OPT;
205195
}
206196
#endif
@@ -470,7 +460,8 @@ void bsp_boot_init(void)
470460
pr_dbg("Core %d is up", CPU_BOOT_ID);
471461

472462
/* Warn for security feature not ready */
473-
if (!get_ibrs_ibpb_cap() && !get_stibp_cap()) {
463+
if (!cpu_has_cap(X86_FEATURE_IBRS_IBPB) &&
464+
!cpu_has_cap(X86_FEATURE_STIBP)) {
474465
pr_fatal("SECURITY WARNING!!!!!!");
475466
pr_fatal("Please apply the latest CPU uCode patch!");
476467
}
@@ -786,7 +777,7 @@ static void cpu_xsave_init(void)
786777
{
787778
uint64_t val64;
788779

789-
if (is_xsave_supported()) {
780+
if (cpu_has_cap(X86_FEATURE_XSAVE)) {
790781
CPU_CR_READ(cr4, &val64);
791782
val64 |= CR4_OSXSAVE;
792783
CPU_CR_WRITE(cr4, val64);

‎hypervisor/common/hv_main.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -152,7 +152,7 @@ int hv_main(int cpu_id)
152152
"cpu_id/tsc_aux mismatch");
153153

154154
/* Check if virtualization extensions are supported */
155-
ret = get_vmx_cap();
155+
ret = cpu_has_cap(X86_FEATURE_VMX);
156156
ASSERT(ret == 1, "VMX not supported!");
157157

158158
/* Enable virtualization extensions */

‎hypervisor/include/arch/x86/cpu.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -224,15 +224,15 @@ extern uint64_t pcpu_active_bitmap;
224224

225225
/* CPUID feature words */
226226
enum feature_word {
227-
FEAT_1_ECX, /* CPUID[1].ECX */
228-
FEAT_1_EDX, /* CPUID[1].EDX */
229-
FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
230-
FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
231-
FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
232-
FEAT_8000_0000_EAX, /* CPUID[8000_0000].EAX */
233-
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
234-
FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
235-
FEAT_8000_0008_EAX, /* CPUID[8000_0008].EAX */
227+
FEAT_1_ECX = 0, /* CPUID[1].ECX */
228+
FEAT_1_EDX = 1, /* CPUID[1].EDX */
229+
FEAT_7_0_EBX = 2, /* CPUID[EAX=7,ECX=0].EBX */
230+
FEAT_7_0_ECX = 3, /* CPUID[EAX=7,ECX=0].ECX */
231+
FEAT_7_0_EDX = 4, /* CPUID[EAX=7,ECX=0].EDX */
232+
FEAT_8000_0000_EAX = 5, /* CPUID[8000_0000].EAX */
233+
FEAT_8000_0001_ECX = 6, /* CPUID[8000_0001].ECX */
234+
FEAT_8000_0001_EDX = 7, /* CPUID[8000_0001].EDX */
235+
FEAT_8000_0008_EAX = 8, /* CPUID[8000_0008].EAX */
236236
FEATURE_WORDS,
237237
};
238238

@@ -258,8 +258,8 @@ int hv_main(int cpu_id);
258258
bool is_vapic_supported(void);
259259
bool is_vapic_intr_delivery_supported(void);
260260
bool is_vapic_virt_reg_supported(void);
261-
bool get_vmx_cap(void);
262261
bool is_xsave_supported(void);
262+
bool cpu_has_cap(uint32_t bit);
263263

264264
/* Read control register */
265265
#define CPU_CR_READ(cr, result_ptr) \

‎hypervisor/include/arch/x86/cpufeatures.h

Lines changed: 105 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,105 @@
1+
/*
2+
* Copyright (C) 2018 Intel Corporation. All rights reserved.
3+
*
4+
* Redistribution and use in source and binary forms, with or without
5+
* modification, are permitted provided that the following conditions
6+
* are met:
7+
*
8+
* * Redistributions of source code must retain the above copyright
9+
* notice, this list of conditions and the following disclaimer.
10+
* * Redistributions in binary form must reproduce the above copyright
11+
* notice, this list of conditions and the following disclaimer in
12+
* the documentation and/or other materials provided with the
13+
* distribution.
14+
* * Neither the name of Intel Corporation nor the names of its
15+
* contributors may be used to endorse or promote products derived
16+
* from this software without specific prior written permission.
17+
*
18+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19+
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20+
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21+
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22+
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23+
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24+
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25+
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26+
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27+
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29+
*/
30+
31+
#ifndef __X86_CPUFEATURES_H__
32+
#define __X86_CPUFEATURES_H__
33+
34+
/* Intel-defined CPU features, CPUID level 0x00000001 (ECX)*/
35+
#define X86_FEATURE_SSE3 ((FEAT_1_ECX << 5) + 0)
36+
#define X86_FEATURE_PCLMUL ((FEAT_1_ECX << 5) + 1)
37+
#define X86_FEATURE_DTES64 ((FEAT_1_ECX << 5) + 2)
38+
#define X86_FEATURE_MONITOR ((FEAT_1_ECX << 5) + 3)
39+
#define X86_FEATURE_DS_CPL ((FEAT_1_ECX << 5) + 4)
40+
#define X86_FEATURE_VMX ((FEAT_1_ECX << 5) + 5)
41+
#define X86_FEATURE_SMX ((FEAT_1_ECX << 5) + 6)
42+
#define X86_FEATURE_EST ((FEAT_1_ECX << 5) + 7)
43+
#define X86_FEATURE_TM2 ((FEAT_1_ECX << 5) + 8)
44+
#define X86_FEATURE_SSSE3 ((FEAT_1_ECX << 5) + 9)
45+
#define X86_FEATURE_CID ((FEAT_1_ECX << 5) + 10)
46+
#define X86_FEATURE_FMA ((FEAT_1_ECX << 5) + 12)
47+
#define X86_FEATURE_CX16 ((FEAT_1_ECX << 5) + 13)
48+
#define X86_FEATURE_ETPRD ((FEAT_1_ECX << 5) + 14)
49+
#define X86_FEATURE_PDCM ((FEAT_1_ECX << 5) + 15)
50+
#define X86_FEATURE_PCID ((FEAT_1_ECX << 5) + 17)
51+
#define X86_FEATURE_DCA ((FEAT_1_ECX << 5) + 18)
52+
#define X86_FEATURE_SSE4_1 ((FEAT_1_ECX << 5) + 19)
53+
#define X86_FEATURE_SSE4_2 ((FEAT_1_ECX << 5) + 20)
54+
#define X86_FEATURE_x2APIC ((FEAT_1_ECX << 5) + 21)
55+
#define X86_FEATURE_MOVBE ((FEAT_1_ECX << 5) + 22)
56+
#define X86_FEATURE_POPCNT ((FEAT_1_ECX << 5) + 23)
57+
#define X86_FEATURE_AES ((FEAT_1_ECX << 5) + 25)
58+
#define X86_FEATURE_XSAVE ((FEAT_1_ECX << 5) + 26)
59+
#define X86_FEATURE_OSXSAVE ((FEAT_1_ECX << 5) + 27)
60+
#define X86_FEATURE_AVX ((FEAT_1_ECX << 5) + 28)
61+
62+
/* Intel-defined CPU features, CPUID level 0x00000001 (EDX)*/
63+
#define X86_FEATURE_FPU ((FEAT_1_EDX << 5) + 0)
64+
#define X86_FEATURE_VME ((FEAT_1_EDX << 5) + 1)
65+
#define X86_FEATURE_DE ((FEAT_1_EDX << 5) + 2)
66+
#define X86_FEATURE_PSE ((FEAT_1_EDX << 5) + 3)
67+
#define X86_FEATURE_TSC ((FEAT_1_EDX << 5) + 4)
68+
#define X86_FEATURE_MSR ((FEAT_1_EDX << 5) + 5)
69+
#define X86_FEATURE_PAE ((FEAT_1_EDX << 5) + 6)
70+
#define X86_FEATURE_MCE ((FEAT_1_EDX << 5) + 7)
71+
#define X86_FEATURE_CX8 ((FEAT_1_EDX << 5) + 8)
72+
#define X86_FEATURE_APIC ((FEAT_1_EDX << 5) + 9)
73+
#define X86_FEATURE_SEP ((FEAT_1_EDX << 5) + 11)
74+
#define X86_FEATURE_MTRR ((FEAT_1_EDX << 5) + 12)
75+
#define X86_FEATURE_PGE ((FEAT_1_EDX << 5) + 13)
76+
#define X86_FEATURE_MCA ((FEAT_1_EDX << 5) + 14)
77+
#define X86_FEATURE_CMOV ((FEAT_1_EDX << 5) + 15)
78+
#define X86_FEATURE_PAT ((FEAT_1_EDX << 5) + 16)
79+
#define X86_FEATURE_PSE36 ((FEAT_1_EDX << 5) + 17)
80+
#define X86_FEATURE_PSN ((FEAT_1_EDX << 5) + 18)
81+
#define X86_FEATURE_CLF ((FEAT_1_EDX << 5) + 19)
82+
#define X86_FEATURE_DTES ((FEAT_1_EDX << 5) + 21)
83+
#define X86_FEATURE_ACPI ((FEAT_1_EDX << 5) + 22)
84+
#define X86_FEATURE_MMX ((FEAT_1_EDX << 5) + 23)
85+
#define X86_FEATURE_FXSR ((FEAT_1_EDX << 5) + 24)
86+
#define X86_FEATURE_SSE ((FEAT_1_EDX << 5) + 25)
87+
#define X86_FEATURE_SSE2 ((FEAT_1_EDX << 5) + 26)
88+
#define X86_FEATURE_SS ((FEAT_1_EDX << 5) + 27)
89+
#define X86_FEATURE_HTT ((FEAT_1_EDX << 5) + 28)
90+
#define X86_FEATURE_TM1 ((FEAT_1_EDX << 5) + 29)
91+
#define X86_FEATURE_IA64 ((FEAT_1_EDX << 5) + 30)
92+
#define X86_FEATURE_PBE ((FEAT_1_EDX << 5) + 31)
93+
94+
/* Intel-defined CPU features, CPUID level 0x00000007 (EBX)*/
95+
#define X86_FEATURE_TSC_ADJ ((FEAT_7_0_EBX << 5) + 1)
96+
#define X86_FEATURE_INVPCID ((FEAT_7_0_EBX << 5) + 10)
97+
98+
/* Intel-defined CPU features, CPUID level 0x00000007 (EDX)*/
99+
#define X86_FEATURE_IBRS_IBPB ((FEAT_7_0_EDX << 5) + 26)
100+
#define X86_FEATURE_STIBP ((FEAT_7_0_EDX << 5) + 27)
101+
102+
/* Intel-defined CPU features, CPUID level 0x80000001 (EDX)*/
103+
#define X86_FEATURE_PAGE1GB ((FEAT_8000_0001_EDX << 5) + 26)
104+
105+
#endif /*__X86_CPUFEATURES_H__*/

‎hypervisor/include/arch/x86/hv_arch.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,5 +58,6 @@
5858
#include <vioapic.h>
5959
#include <guest.h>
6060
#include <vmexit.h>
61+
#include <cpufeatures.h>
6162

6263
#endif /* HV_ARCH_H */

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