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junjiemao1lijinxia
junjiemao1
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lijinxia
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HV: ioapic: convert pins to uint8_t
Currently IOAPIC pins are represented using various types, including uint16_t, int, uint8_t and uint32_t. This patch converts all pins to uint8_t since the maximum number of interrupt input pins per IOAPIC is limited to 240. The special value IOAPIC_INVALID_PIN is defined to indicate that a valid pin cannot be found. This type clean up also has the following impacts. * The values in the ''legacy_irq_to_pin'' table are piggybacked with their trigger mode. This patch splits them as the piggyback prevents us from using a uint8_t[] for this table, and these two information are never used at the same time. * The ''offset'' parameter in ioapic_read_reg32 & ioapic_write_reg32 are promoted to uint32_t to minimize explicit type conversions and keep aligned with the type of formal parameters of mmio_(read|write)_long. Tracked-on: ccm0001001-247033 Signed-off-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
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-46
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2 files changed

+67
-46
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‎hypervisor/arch/x86/ioapic.c

Lines changed: 62 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010
#define IOAPIC_REGSEL_OFFSET 0
1111
#define IOAPIC_WINSWL_OFFSET 0x10
1212

13-
#define IOAPIC_MAX_PIN 256
13+
#define IOAPIC_MAX_PIN 240U
14+
#define IOAPIC_INVALID_PIN 0xffU
1415

1516
/* IOAPIC Redirection Table (RTE) Entry structure */
1617
struct ioapic_rte {
@@ -33,7 +34,7 @@ static struct ioapic_rte saved_rte[CONFIG_NR_IOAPICS][IOAPIC_MAX_PIN];
3334
* the irq to ioapic pin mapping should extract from ACPI MADT table
3435
* hardcoded here
3536
*/
36-
uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
37+
uint8_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
3738
2U, /* IRQ0*/
3839
1U, /* IRQ1*/
3940
0U, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
@@ -43,7 +44,7 @@ uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
4344
6U, /* IRQ6*/
4445
7U, /* IRQ7*/
4546
8U, /* IRQ8*/
46-
9U | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
47+
9U, /* IRQ9*/
4748
10U, /* IRQ10*/
4849
11U, /* IRQ11*/
4950
12U, /* IRQ12*/
@@ -52,7 +53,26 @@ uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
5253
15U, /* IRQ15*/
5354
};
5455

55-
uint16_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
56+
uint32_t legacy_irq_trigger_mode[NR_LEGACY_IRQ] = {
57+
IOAPIC_RTE_TRGREDG, /* IRQ0*/
58+
IOAPIC_RTE_TRGREDG, /* IRQ1*/
59+
IOAPIC_RTE_TRGREDG, /* IRQ2*/
60+
IOAPIC_RTE_TRGREDG, /* IRQ3*/
61+
IOAPIC_RTE_TRGREDG, /* IRQ4*/
62+
IOAPIC_RTE_TRGREDG, /* IRQ5*/
63+
IOAPIC_RTE_TRGREDG, /* IRQ6*/
64+
IOAPIC_RTE_TRGREDG, /* IRQ7*/
65+
IOAPIC_RTE_TRGREDG, /* IRQ8*/
66+
IOAPIC_RTE_TRGRLVL, /* IRQ9*/
67+
IOAPIC_RTE_TRGREDG, /* IRQ10*/
68+
IOAPIC_RTE_TRGREDG, /* IRQ11*/
69+
IOAPIC_RTE_TRGREDG, /* IRQ12*/
70+
IOAPIC_RTE_TRGREDG, /* IRQ13*/
71+
IOAPIC_RTE_TRGREDG, /* IRQ14*/
72+
IOAPIC_RTE_TRGREDG, /* IRQ15*/
73+
};
74+
75+
uint8_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
5676
2U, /* pin0*/
5777
1U, /* pin1*/
5878
0U, /* pin2*/
@@ -80,7 +100,7 @@ static void *map_ioapic(uint64_t ioapic_paddr)
80100
}
81101

82102
static inline uint32_t
83-
ioapic_read_reg32(const void *ioapic_base, const uint8_t offset)
103+
ioapic_read_reg32(const void *ioapic_base, const uint32_t offset)
84104
{
85105
uint32_t v;
86106

@@ -99,7 +119,7 @@ ioapic_read_reg32(const void *ioapic_base, const uint8_t offset)
99119

100120
static inline void
101121
ioapic_write_reg32(const void *ioapic_base,
102-
const uint8_t offset, const uint32_t value)
122+
const uint32_t offset, const uint32_t value)
103123
{
104124
spinlock_rflags;
105125

@@ -133,18 +153,20 @@ get_ioapic_base(uint8_t apic_id)
133153

134154
static inline void
135155
ioapic_get_rte_entry(void *ioapic_addr,
136-
int pin, struct ioapic_rte *rte)
156+
uint8_t pin, struct ioapic_rte *rte)
137157
{
138-
rte->lo_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x10);
139-
rte->hi_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x11);
158+
uint32_t rte_addr = (uint32_t)pin * 2U + 0x10U;
159+
rte->lo_32 = ioapic_read_reg32(ioapic_addr, rte_addr);
160+
rte->hi_32 = ioapic_read_reg32(ioapic_addr, rte_addr + 1U);
140161
}
141162

142163
static inline void
143164
ioapic_set_rte_entry(void *ioapic_addr,
144-
int pin, struct ioapic_rte *rte)
165+
uint8_t pin, struct ioapic_rte *rte)
145166
{
146-
ioapic_write_reg32(ioapic_addr, pin*2 + 0x10, rte->lo_32);
147-
ioapic_write_reg32(ioapic_addr, pin*2 + 0x11, rte->hi_32);
167+
uint32_t rte_addr = (uint32_t)pin * 2U + 0x10U;
168+
ioapic_write_reg32(ioapic_addr, rte_addr, rte->lo_32);
169+
ioapic_write_reg32(ioapic_addr, rte_addr + 1U, rte->hi_32);
148170
}
149171

150172
static inline struct ioapic_rte
@@ -158,7 +180,8 @@ create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
158180
*/
159181

160182
rte.lo_32 |= IOAPIC_RTE_INTMSET;
161-
rte.lo_32 |= (legacy_irq_to_pin[irq] & IOAPIC_RTE_TRGRLVL);
183+
184+
rte.lo_32 |= legacy_irq_trigger_mode[irq];
162185
rte.lo_32 |= DEFAULT_DEST_MODE;
163186
rte.lo_32 |= DEFAULT_DELIVERY_MODE;
164187
rte.lo_32 |= (IOAPIC_RTE_INTVEC & vr);
@@ -210,7 +233,7 @@ static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
210233
else
211234
update_irq_handler(gsi, common_handler_edge);
212235

213-
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
236+
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%x",
214237
gsi, gsi_table[gsi].pin,
215238
rte.lo_32);
216239
}
@@ -243,7 +266,7 @@ void ioapic_set_rte(uint32_t irq, uint64_t raw_rte)
243266
rte.hi_32 = raw_rte >> 32;
244267
ioapic_set_rte_entry(addr, gsi_table[irq].pin, &rte);
245268

246-
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
269+
dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%hhu rte:%x",
247270
irq, gsi_table[irq].pin,
248271
rte.lo_32);
249272
}
@@ -258,23 +281,20 @@ bool irq_is_gsi(uint32_t irq)
258281
return irq < nr_gsi;
259282
}
260283

261-
int irq_to_pin(uint32_t irq)
284+
uint8_t irq_to_pin(uint32_t irq)
262285
{
263286
if (irq_is_gsi(irq))
264287
return gsi_table[irq].pin;
265288
else
266-
return -1;
289+
return IOAPIC_INVALID_PIN;
267290
}
268291

269-
uint32_t pin_to_irq(int pin)
292+
uint32_t pin_to_irq(uint8_t pin)
270293
{
271294
uint32_t i;
272295

273-
if (pin < 0)
274-
return IRQ_INVALID;
275-
276296
for (i = 0U; i < nr_gsi; i++) {
277-
if (gsi_table[i].pin == (uint8_t) pin)
297+
if (gsi_table[i].pin == pin)
278298
return i;
279299
}
280300
return IRQ_INVALID;
@@ -284,7 +304,7 @@ void
284304
irq_gsi_mask_unmask(uint32_t irq, bool mask)
285305
{
286306
void *addr = gsi_table[irq].addr;
287-
int pin = gsi_table[irq].pin;
307+
uint8_t pin = gsi_table[irq].pin;
288308
struct ioapic_rte rte;
289309

290310
if (!irq_is_gsi(irq))
@@ -296,23 +316,24 @@ irq_gsi_mask_unmask(uint32_t irq, bool mask)
296316
else
297317
rte.lo_32 &= ~IOAPIC_RTE_INTMASK;
298318
ioapic_set_rte_entry(addr, pin, &rte);
299-
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%d rte:%x",
319+
dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%hhu rte:%x",
300320
irq, pin, rte.lo_32);
301321
}
302322

303-
static uint32_t
323+
static uint8_t
304324
ioapic_nr_pins(void *ioapic_base)
305325
{
306326
uint32_t version;
307-
uint32_t nr_pins;
327+
uint8_t nr_pins;
308328

309329
version = ioapic_read_reg32(ioapic_base, IOAPIC_VER);
310330
dev_dbg(ACRN_DBG_IRQ, "IOAPIC version: %x", version);
311331

312332
/* The 23:16 bits in the version register is the highest entry in the
313333
* I/O redirection table, which is 1 smaller than the number of
314334
* interrupt input pins. */
315-
nr_pins = (((version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT) + 1U);
335+
nr_pins = (uint8_t)
336+
(((version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT) + 1U);
316337

317338
ASSERT(nr_pins > NR_LEGACY_IRQ, "Legacy IRQ num > total GSI");
318339
ASSERT(nr_pins <= IOAPIC_MAX_PIN, "IOAPIC pins exceeding 240");
@@ -331,11 +352,11 @@ void setup_ioapic_irq(void)
331352
for (ioapic_id = 0U;
332353
ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
333354
void *addr;
334-
uint32_t pin, nr_pins;
355+
uint8_t pin, nr_pins;
335356

336357
addr = map_ioapic(get_ioapic_base(ioapic_id));
337358
nr_pins = ioapic_nr_pins(addr);
338-
for (pin = 0; pin < nr_pins; pin++) {
359+
for (pin = 0U; pin < nr_pins; pin++) {
339360
gsi_table[gsi].ioapic_id = ioapic_id;
340361
gsi_table[gsi].addr = addr;
341362

@@ -381,42 +402,42 @@ void dump_ioapic(void)
381402

382403
for (irq = 0U; irq < nr_gsi; irq++) {
383404
void *addr = gsi_table[irq].addr;
384-
int pin = gsi_table[irq].pin;
405+
uint8_t pin = gsi_table[irq].pin;
385406
struct ioapic_rte rte;
386407

387408
ioapic_get_rte_entry(addr, pin, &rte);
388-
dev_dbg(ACRN_DBG_IRQ, "DUMP: irq:%d pin:%d rte:%x",
409+
dev_dbg(ACRN_DBG_IRQ, "DUMP: irq:%d pin:%hhu rte:%x",
389410
irq, pin, rte.lo_32);
390411
}
391412
}
392413

393414
void suspend_ioapic(void)
394415
{
395-
int ioapic_id, ioapic_pin;
416+
uint8_t ioapic_id, ioapic_pin;
396417

397-
for (ioapic_id = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
418+
for (ioapic_id = 0U; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
398419
void *addr;
399-
uint32_t nr_pins;
420+
uint8_t nr_pins;
400421

401422
addr = map_ioapic(get_ioapic_base(ioapic_id));
402423
nr_pins = ioapic_nr_pins(addr);
403-
for (ioapic_pin = 0; ioapic_pin < nr_pins; ioapic_pin++)
424+
for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++)
404425
ioapic_get_rte_entry(addr, ioapic_pin,
405426
&saved_rte[ioapic_id][ioapic_pin]);
406427
}
407428
}
408429

409430
void resume_ioapic(void)
410431
{
411-
int ioapic_id, ioapic_pin;
432+
uint8_t ioapic_id, ioapic_pin;
412433

413-
for (ioapic_id = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
434+
for (ioapic_id = 0U; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
414435
void *addr;
415-
uint32_t nr_pins;
436+
uint8_t nr_pins;
416437

417438
addr = map_ioapic(get_ioapic_base(ioapic_id));
418439
nr_pins = ioapic_nr_pins(addr);
419-
for (ioapic_pin = 0; ioapic_pin < nr_pins; ioapic_pin++)
440+
for (ioapic_pin = 0U; ioapic_pin < nr_pins; ioapic_pin++)
420441
ioapic_set_rte_entry(addr, ioapic_pin,
421442
&saved_rte[ioapic_id][ioapic_pin]);
422443
}
@@ -447,7 +468,7 @@ int get_ioapic_info(char *str, int str_max_len)
447468

448469
for (irq = 0U; irq < nr_gsi; irq++) {
449470
void *addr = gsi_table[irq].addr;
450-
int pin = gsi_table[irq].pin;
471+
uint8_t pin = gsi_table[irq].pin;
451472
struct ioapic_rte rte;
452473

453474
bool irr, phys, level, mask;
@@ -459,7 +480,7 @@ int get_ioapic_info(char *str, int str_max_len)
459480
get_rte_info(&rte, &mask, &irr, &phys, &delmode, &level,
460481
&vector, &dest);
461482

462-
len = snprintf(str, size, "\r\n%03d\t%03d\t0x%08X\t0x%08X\t",
483+
len = snprintf(str, size, "\r\n%03d\t%03hhu\t0x%08X\t0x%08X\t",
463484
irq, pin, rte.hi_32, rte.lo_32);
464485
size -= len;
465486
str += len;

‎hypervisor/include/arch/x86/ioapic.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
/* IOAPIC_MAX_LINES is architecturally defined.
1111
* The usable RTEs may be a subset of the total on a per IO APIC basis.
1212
*/
13-
#define IOAPIC_MAX_LINES 120
13+
#define IOAPIC_MAX_LINES 120U
1414
#define NR_LEGACY_IRQ 16U
1515
#define NR_LEGACY_PIN NR_LEGACY_IRQ
1616
#define NR_MAX_GSI (CONFIG_NR_IOAPICS*IOAPIC_MAX_LINES)
@@ -23,8 +23,8 @@ void setup_ioapic_irq(void);
2323

2424
bool irq_is_gsi(uint32_t irq);
2525
uint32_t irq_gsi_num(void);
26-
int irq_to_pin(uint32_t irq);
27-
uint32_t pin_to_irq(int pin);
26+
uint8_t irq_to_pin(uint32_t irq);
27+
uint32_t pin_to_irq(uint8_t pin);
2828
void irq_gsi_mask_unmask(uint32_t irq, bool mask);
2929
void ioapic_set_rte(uint32_t irq, uint64_t rte);
3030
void ioapic_get_rte(uint32_t irq, uint64_t *rte);
@@ -33,8 +33,8 @@ void ioapic_get_rte(uint32_t irq, uint64_t *rte);
3333
void suspend_ioapic(void);
3434
void resume_ioapic(void);
3535

36-
extern uint16_t legacy_irq_to_pin[];
37-
extern uint16_t pic_ioapic_pin_map[];
36+
extern uint8_t legacy_irq_to_pin[];
37+
extern uint8_t pic_ioapic_pin_map[];
3838

3939
#ifdef HV_DEBUG
4040
int get_ioapic_info(char *str, int str_max_len);

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