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HV:INSTR:Rearrange register names in the enum cpu_reg_name
In the current "enum cpu_reg_name", there are 16-bit segment register names, 16-bit descriptor table register names, and 16-bit task register names. These 16-bit register names are defined among the 64 bit register names. To access these 16-bit fields in VMCS and 32 bit fields in VMCS, more condition statements need to be used. Update 16-bit register names position to simplify conditions in vm_get_register and vm_set_register since different fields size accessing in VMCS by different vmread/vmwrite opreation. Note: After checking the current implementation, the register names of the same kind of registers (general registers, control registers, segment registers etc) need to be defined in order, some code checks the range by using this order. But different kinds of register names as group, this group position can be adjusted to simplify conditions. The follwoing register names group need to be considered in current implemetation: (1) General register names group: CPU_REG_RAX~CPU_REG_RDI; (2) Non-General register names group:CPU_REG_CR0~CPU_REG_LAST; (3) segment register names group:CPU_REG_ES~CPU_REG_GS. V1-->V2: This is new part of this patch serial created in V2 to rearrange register names as needed. V2--V3: Update comment information. V3-->V4: Define CPU_REG_NATURAL_LAST and CPU_REG_64BIT_LAST to make condition more understandable. Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com>
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