hv: vtd: fix MACRO typos

ROOT_ENTRY_LOWER_CTP_MASK shall be (0xFFFFFFFFFFFFFUL << ROOT_ENTRY_LOWER_CTP_POS)
rather than (0xFFFFFFFFFFFFFUL).
Rationale:
CTP is bits 63:12 in a root entry according to Chapter 9.1 Root Entry in
VT-d spec.

Similarly, update ROOT_ENTRY_LOWER_PRESENT_MASK to keep the coding style
consistent.

CTX_ENTRY_UPPER_DID_MASK shall be (0xFFFFUL << CTX_ENTRY_UPPER_DID_POS)
rather than (0x3FUL << CTX_ENTRY_UPPER_DID_POS).
Rationale:
DID is bits 87:72 in a context entry according to Chapter 9.3 Context
Entry in VT-d spec. It takes 16 bits rather than 6 bits.

Tracked-On: #3626
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

hypervisor/arch/x86/vtd.c

@@ -31,9 +31,9 @@
 #define LEVEL_WIDTH 9U
 
 #define ROOT_ENTRY_LOWER_PRESENT_POS        (0U)
-#define ROOT_ENTRY_LOWER_PRESENT_MASK       (1UL)
+#define ROOT_ENTRY_LOWER_PRESENT_MASK       (1UL << ROOT_ENTRY_LOWER_PRESENT_POS)
 #define ROOT_ENTRY_LOWER_CTP_POS            (12U)
-#define ROOT_ENTRY_LOWER_CTP_MASK           (0xFFFFFFFFFFFFFUL)
+#define ROOT_ENTRY_LOWER_CTP_MASK           (0xFFFFFFFFFFFFFUL << ROOT_ENTRY_LOWER_CTP_POS)
 
 /* 4 iommu fault register state */
 #define	IOMMU_FAULT_REGISTER_STATE_NUM	4U
@@ -42,7 +42,7 @@
 #define CTX_ENTRY_UPPER_AW_POS          (0U)
 #define CTX_ENTRY_UPPER_AW_MASK         (0x7UL << CTX_ENTRY_UPPER_AW_POS)
 #define CTX_ENTRY_UPPER_DID_POS         (8U)
-#define CTX_ENTRY_UPPER_DID_MASK        (0x3FUL << CTX_ENTRY_UPPER_DID_POS)
+#define CTX_ENTRY_UPPER_DID_MASK        (0xFFFFUL << CTX_ENTRY_UPPER_DID_POS)
 #define CTX_ENTRY_LOWER_P_POS           (0U)
 #define CTX_ENTRY_LOWER_P_MASK          (0x1UL << CTX_ENTRY_LOWER_P_POS)
 #define CTX_ENTRY_LOWER_FPD_POS         (1U)