always @ ( * ) combinational block

[kiteloopdesign]

Hi, is there any example about how to get some combinational block? grepping on the examples I found something but it all is related to the test and not the generated RTL I believe?

veriloggen/examples$ grep  -r -e "always @(\*" * -l

simulation_verilator/test_simulation_verilator.py
thread_add_ipxact/test_thread_add_ipxact.py
thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py
thread_ipxact/test_thread_ipxact.py
thread_memcpy_ipxact/test_thread_memcpy_ipxact.py
thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

In other words, what I need to get is a block of this form.

always @ ( * ) begin
end

Ideally this block would have some more logic inside, some if-else maybe.

always @ ( * ) begin
var1 = some_other_Var
if ( var1 == yet_oher_var) begin
assign_this = 1;
end
else begin
assign_this = 0;
end
end

Is this possible?

[LucasBraganca]

Hi SiliconKite, it's possible to do this, you only need usage Always() without parameters.

from veriloggen import *

m = Module("CombModule")
a = m.Input("a")
b = m.Input("b")
c = m.OutputReg("c")

m.Always()(
  c(a ^ b)    
)

m.to_verilog("CombModule.v")

[kiteloopdesign]

it works indeed!
thanks for the quick response!