graph TD; CFG("Configuration") --> A["Level-1 PreProcessor"] A --> A1[Clear l1 stack] A1 --> B(("Main Loop <br> Source files")) B --> C("Read source file") C --- D("Processor items") D --> E("Extract polar <br> ocean segments") E --> F("Processor items") F --> F1(Add segments to l1 stack) F1 -->G{"All l1 segments <br> connected?"} G --> B G --> H("Merge connected <br> l1 segments") H --> H1["Merged l1 segments"] H1 --- I("Processor items") I --> J("Export l1p netCDF") H --> H2["Remaining l1 segments"] H2 --> H3["Reset l1 stack"] H3 --> B