/
vmx-impl.c.inc
3098 lines (2655 loc) · 109 KB
/
vmx-impl.c.inc
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/*
* translate/vmx-impl.c
*
* Altivec/VMX translation
*/
/*** Altivec vector extension ***/
/* Altivec registers moves */
static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg));
return r;
}
#define GEN_VR_LDX(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 avr; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
avr = tcg_temp_new_i64(); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
/* \
* We only need to swap high and low halves. gen_qemu_ld64_i64 \
* does necessary 64-bit byteswap already. \
*/ \
if (ctx->le_mode) { \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, false); \
tcg_gen_addi_tl(EA, EA, 8); \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, true); \
} else { \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, true); \
tcg_gen_addi_tl(EA, EA, 8); \
gen_qemu_ld64_i64(ctx, avr, EA); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(avr); \
}
#define GEN_VR_STX(name, opc2, opc3) \
static void gen_st##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_i64 avr; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
avr = tcg_temp_new_i64(); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
/* \
* We only need to swap high and low halves. gen_qemu_st64_i64 \
* does necessary 64-bit byteswap already. \
*/ \
if (ctx->le_mode) { \
get_avr64(avr, rD(ctx->opcode), false); \
gen_qemu_st64_i64(ctx, avr, EA); \
tcg_gen_addi_tl(EA, EA, 8); \
get_avr64(avr, rD(ctx->opcode), true); \
gen_qemu_st64_i64(ctx, avr, EA); \
} else { \
get_avr64(avr, rD(ctx->opcode), true); \
gen_qemu_st64_i64(ctx, avr, EA); \
tcg_gen_addi_tl(EA, EA, 8); \
get_avr64(avr, rD(ctx->opcode), false); \
gen_qemu_st64_i64(ctx, avr, EA); \
} \
tcg_temp_free(EA); \
tcg_temp_free_i64(avr); \
}
#define GEN_VR_LVE(name, opc2, opc3, size) \
static void gen_lve##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
if (size > 1) { \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_lve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
#define GEN_VR_STVE(name, opc2, opc3, size) \
static void gen_stve##name(DisasContext *ctx) \
{ \
TCGv EA; \
TCGv_ptr rs; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
if (size > 1) { \
tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
} \
rs = gen_avr_ptr(rS(ctx->opcode)); \
gen_helper_stve##name(cpu_env, rs, EA); \
tcg_temp_free(EA); \
tcg_temp_free_ptr(rs); \
}
GEN_VR_LDX(lvx, 0x07, 0x03);
/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
GEN_VR_LDX(lvxl, 0x07, 0x0B);
GEN_VR_LVE(bx, 0x07, 0x00, 1);
GEN_VR_LVE(hx, 0x07, 0x01, 2);
GEN_VR_LVE(wx, 0x07, 0x02, 4);
GEN_VR_STX(svx, 0x07, 0x07);
/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
GEN_VR_STX(svxl, 0x07, 0x0F);
GEN_VR_STVE(bx, 0x07, 0x04, 1);
GEN_VR_STVE(hx, 0x07, 0x05, 2);
GEN_VR_STVE(wx, 0x07, 0x06, 4);
static void gen_mfvscr(DisasContext *ctx)
{
TCGv_i32 t;
TCGv_i64 avr;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
avr = tcg_temp_new_i64();
tcg_gen_movi_i64(avr, 0);
set_avr64(rD(ctx->opcode), avr, true);
t = tcg_temp_new_i32();
gen_helper_mfvscr(t, cpu_env);
tcg_gen_extu_i32_i64(avr, t);
set_avr64(rD(ctx->opcode), avr, false);
tcg_temp_free_i32(t);
tcg_temp_free_i64(avr);
}
static void gen_mtvscr(DisasContext *ctx)
{
TCGv_i32 val;
int bofs;
if (unlikely(!ctx->altivec_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VPU);
return;
}
val = tcg_temp_new_i32();
bofs = avr_full_offset(rB(ctx->opcode));
#ifdef HOST_WORDS_BIGENDIAN
bofs += 3 * 4;
#endif
tcg_gen_ld_i32(val, cpu_env, bofs);
gen_helper_mtvscr(cpu_env, val);
tcg_temp_free_i32(val);
}
#define GEN_VX_VMUL10(name, add_cin, ret_carry) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_i64 t0; \
TCGv_i64 t1; \
TCGv_i64 t2; \
TCGv_i64 avr; \
TCGv_i64 ten, z; \
\
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
t0 = tcg_temp_new_i64(); \
t1 = tcg_temp_new_i64(); \
t2 = tcg_temp_new_i64(); \
avr = tcg_temp_new_i64(); \
ten = tcg_const_i64(10); \
z = tcg_const_i64(0); \
\
if (add_cin) { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
get_avr64(avr, rB(ctx->opcode), false); \
tcg_gen_andi_i64(t2, avr, 0xF); \
tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
} else { \
get_avr64(avr, rA(ctx->opcode), false); \
tcg_gen_mulu2_i64(avr, t2, avr, ten); \
set_avr64(rD(ctx->opcode), avr, false); \
} \
\
if (ret_carry) { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mulu2_i64(t0, t1, avr, ten); \
tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \
set_avr64(rD(ctx->opcode), avr, false); \
set_avr64(rD(ctx->opcode), z, true); \
} else { \
get_avr64(avr, rA(ctx->opcode), true); \
tcg_gen_mul_i64(t0, avr, ten); \
tcg_gen_add_i64(avr, t0, t2); \
set_avr64(rD(ctx->opcode), avr, true); \
} \
\
tcg_temp_free_i64(t0); \
tcg_temp_free_i64(t1); \
tcg_temp_free_i64(t2); \
tcg_temp_free_i64(avr); \
tcg_temp_free_i64(ten); \
tcg_temp_free_i64(z); \
} \
GEN_VX_VMUL10(vmul10uq, 0, 0);
GEN_VX_VMUL10(vmul10euq, 1, 0);
GEN_VX_VMUL10(vmul10cuq, 0, 1);
GEN_VX_VMUL10(vmul10ecuq, 1, 1);
#define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
\
tcg_op(vece, \
avr_full_offset(rD(ctx->opcode)), \
avr_full_offset(rA(ctx->opcode)), \
avr_full_offset(rB(ctx->opcode)), \
16, 16); \
}
/* Logical operations */
GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16);
GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17);
GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18);
GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19);
GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20);
GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26);
GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22);
GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21);
#define GEN_VXFORM(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(rd, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM_TRANS(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
trans_##name(ctx); \
}
#define GEN_VXFORM_ENV(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, ra, rb); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rd); \
}
#define GEN_VXFORM3(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr ra, rb, rc, rd; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rc = gen_avr_ptr(rC(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(rd, ra, rb, rc); \
tcg_temp_free_ptr(ra); \
tcg_temp_free_ptr(rb); \
tcg_temp_free_ptr(rc); \
tcg_temp_free_ptr(rd); \
}
/*
* Support for Altivec instruction pairs that use bit 31 (Rc) as
* an opcode bit. In general, these pairs come from different
* versions of the ISA, so we must also support a pair of flags for
* each instruction.
*/
#define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
gen_##name0(ctx); \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
gen_##name1(ctx); \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
/*
* We use this macro if one instruction is realized with direct
* translation, and second one with helper.
*/
#define GEN_VXFORM_TRANS_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1)\
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
trans_##name0(ctx); \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
gen_##name1(ctx); \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
/* Adds support to provide invalid mask */
#define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \
name1, flg1, flg2_1, inval1) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
if ((Rc(ctx->opcode) == 0) && \
((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \
!(ctx->opcode & inval0)) { \
gen_##name0(ctx); \
} else if ((Rc(ctx->opcode) == 1) && \
((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \
!(ctx->opcode & inval1)) { \
gen_##name1(ctx); \
} else { \
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
} \
}
#define GEN_VXFORM_HETRO(name, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
TCGv_ptr rb; \
if (unlikely(!ctx->altivec_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
rb = gen_avr_ptr(rB(ctx->opcode)); \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
tcg_temp_free_ptr(rb); \
}
GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0);
GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1);
GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \
vmul10ecuq, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2);
GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3);
GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16);
GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17);
GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18);
GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19);
GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0);
GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1);
GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2);
GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3);
GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4);
GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5);
GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6);
GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7);
GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8);
GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9);
GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10);
GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11);
GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12);
GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13);
GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14);
GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15);
GEN_VXFORM(vavgub, 1, 16);
GEN_VXFORM(vabsdub, 1, 16);
GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
vabsdub, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguh, 1, 17);
GEN_VXFORM(vabsduh, 1, 17);
GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
vabsduh, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguw, 1, 18);
GEN_VXFORM(vabsduw, 1, 18);
GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
vabsduw, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
GEN_VXFORM(vmrghb, 6, 0);
GEN_VXFORM(vmrghh, 6, 1);
GEN_VXFORM(vmrghw, 6, 2);
GEN_VXFORM(vmrglb, 6, 4);
GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
static void trans_vmrgew(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VA = rA(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 tmp = tcg_temp_new_i64();
TCGv_i64 avr = tcg_temp_new_i64();
get_avr64(avr, VB, true);
tcg_gen_shri_i64(tmp, avr, 32);
get_avr64(avr, VA, true);
tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
set_avr64(VT, avr, true);
get_avr64(avr, VB, false);
tcg_gen_shri_i64(tmp, avr, 32);
get_avr64(avr, VA, false);
tcg_gen_deposit_i64(avr, avr, tmp, 0, 32);
set_avr64(VT, avr, false);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(avr);
}
static void trans_vmrgow(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VA = rA(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 avr = tcg_temp_new_i64();
get_avr64(t0, VB, true);
get_avr64(t1, VA, true);
tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
set_avr64(VT, avr, true);
get_avr64(t0, VB, false);
get_avr64(t1, VA, false);
tcg_gen_deposit_i64(avr, t0, t1, 32, 32);
set_avr64(VT, avr, false);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(avr);
}
/*
* lvsl VRT,RA,RB - Load Vector for Shift Left
*
* Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
* Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
* Bytes sh:sh+15 of X are placed into vD.
*/
static void trans_lvsl(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
TCGv_i64 result = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv EA = tcg_temp_new();
/* Get sh(from description) by anding EA with 0xf. */
gen_addr_reg_index(ctx, EA);
tcg_gen_extu_tl_i64(sh, EA);
tcg_gen_andi_i64(sh, sh, 0xfULL);
/*
* Create bytes sh:sh+7 of X(from description) and place them in
* higher doubleword of vD.
*/
tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
tcg_gen_addi_i64(result, sh, 0x0001020304050607ull);
set_avr64(VT, result, true);
/*
* Create bytes sh+8:sh+15 of X(from description) and place them in
* lower doubleword of vD.
*/
tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL);
set_avr64(VT, result, false);
tcg_temp_free_i64(result);
tcg_temp_free_i64(sh);
tcg_temp_free(EA);
}
/*
* lvsr VRT,RA,RB - Load Vector for Shift Right
*
* Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31].
* Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F.
* Bytes (16-sh):(31-sh) of X are placed into vD.
*/
static void trans_lvsr(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
TCGv_i64 result = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv EA = tcg_temp_new();
/* Get sh(from description) by anding EA with 0xf. */
gen_addr_reg_index(ctx, EA);
tcg_gen_extu_tl_i64(sh, EA);
tcg_gen_andi_i64(sh, sh, 0xfULL);
/*
* Create bytes (16-sh):(23-sh) of X(from description) and place them in
* higher doubleword of vD.
*/
tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL);
tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh);
set_avr64(VT, result, true);
/*
* Create bytes (24-sh):(32-sh) of X(from description) and place them in
* lower doubleword of vD.
*/
tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh);
set_avr64(VT, result, false);
tcg_temp_free_i64(result);
tcg_temp_free_i64(sh);
tcg_temp_free(EA);
}
/*
* vsl VRT,VRA,VRB - Vector Shift Left
*
* Shifting left 128 bit value of vA by value specified in bits 125-127 of vB.
* Lowest 3 bits in each byte element of register vB must be identical or
* result is undefined.
*/
static void trans_vsl(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VA = rA(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 avr = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv_i64 carry = tcg_temp_new_i64();
TCGv_i64 tmp = tcg_temp_new_i64();
/* Place bits 125-127 of vB in 'sh'. */
get_avr64(avr, VB, false);
tcg_gen_andi_i64(sh, avr, 0x07ULL);
/*
* Save highest 'sh' bits of lower doubleword element of vA in variable
* 'carry' and perform shift on lower doubleword.
*/
get_avr64(avr, VA, false);
tcg_gen_subfi_i64(tmp, 32, sh);
tcg_gen_shri_i64(carry, avr, 32);
tcg_gen_shr_i64(carry, carry, tmp);
tcg_gen_shl_i64(avr, avr, sh);
set_avr64(VT, avr, false);
/*
* Perform shift on higher doubleword element of vA and replace lowest
* 'sh' bits with 'carry'.
*/
get_avr64(avr, VA, true);
tcg_gen_shl_i64(avr, avr, sh);
tcg_gen_or_i64(avr, avr, carry);
set_avr64(VT, avr, true);
tcg_temp_free_i64(avr);
tcg_temp_free_i64(sh);
tcg_temp_free_i64(carry);
tcg_temp_free_i64(tmp);
}
/*
* vsr VRT,VRA,VRB - Vector Shift Right
*
* Shifting right 128 bit value of vA by value specified in bits 125-127 of vB.
* Lowest 3 bits in each byte element of register vB must be identical or
* result is undefined.
*/
static void trans_vsr(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VA = rA(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 avr = tcg_temp_new_i64();
TCGv_i64 sh = tcg_temp_new_i64();
TCGv_i64 carry = tcg_temp_new_i64();
TCGv_i64 tmp = tcg_temp_new_i64();
/* Place bits 125-127 of vB in 'sh'. */
get_avr64(avr, VB, false);
tcg_gen_andi_i64(sh, avr, 0x07ULL);
/*
* Save lowest 'sh' bits of higher doubleword element of vA in variable
* 'carry' and perform shift on higher doubleword.
*/
get_avr64(avr, VA, true);
tcg_gen_subfi_i64(tmp, 32, sh);
tcg_gen_shli_i64(carry, avr, 32);
tcg_gen_shl_i64(carry, carry, tmp);
tcg_gen_shr_i64(avr, avr, sh);
set_avr64(VT, avr, true);
/*
* Perform shift on lower doubleword element of vA and replace highest
* 'sh' bits with 'carry'.
*/
get_avr64(avr, VA, false);
tcg_gen_shr_i64(avr, avr, sh);
tcg_gen_or_i64(avr, avr, carry);
set_avr64(VT, avr, false);
tcg_temp_free_i64(avr);
tcg_temp_free_i64(sh);
tcg_temp_free_i64(carry);
tcg_temp_free_i64(tmp);
}
/*
* vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword
*
* All ith bits (i in range 1 to 8) of each byte of doubleword element in source
* register are concatenated and placed into ith byte of appropriate doubleword
* element in destination register.
*
* Following solution is done for both doubleword elements of source register
* in parallel, in order to reduce the number of instructions needed(that's why
* arrays are used):
* First, both doubleword elements of source register vB are placed in
* appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for
* loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of
* byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with
* tcg_mask. For every following iteration, both avr[i] and tcg_mask variables
* have to be shifted right for 7 and 8 places, respectively, in order to get
* bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so
* shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask...
* After first 8 iteration(first loop), all the first bits are in their final
* places, all second bits but second bit from eight byte are in their places...
* only 1 eight bit from eight byte is in it's place). In second loop we do all
* operations symmetrically, in order to get other half of bits in their final
* spots. Results for first and second doubleword elements are saved in
* result[0] and result[1] respectively. In the end those results are saved in
* appropriate doubleword element of destination register vD.
*/
static void trans_vgbbd(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 tmp = tcg_temp_new_i64();
uint64_t mask = 0x8040201008040201ULL;
int i, j;
TCGv_i64 result[2];
result[0] = tcg_temp_new_i64();
result[1] = tcg_temp_new_i64();
TCGv_i64 avr[2];
avr[0] = tcg_temp_new_i64();
avr[1] = tcg_temp_new_i64();
TCGv_i64 tcg_mask = tcg_temp_new_i64();
tcg_gen_movi_i64(tcg_mask, mask);
for (j = 0; j < 2; j++) {
get_avr64(avr[j], VB, j);
tcg_gen_and_i64(result[j], avr[j], tcg_mask);
}
for (i = 1; i < 8; i++) {
tcg_gen_movi_i64(tcg_mask, mask >> (i * 8));
for (j = 0; j < 2; j++) {
tcg_gen_shri_i64(tmp, avr[j], i * 7);
tcg_gen_and_i64(tmp, tmp, tcg_mask);
tcg_gen_or_i64(result[j], result[j], tmp);
}
}
for (i = 1; i < 8; i++) {
tcg_gen_movi_i64(tcg_mask, mask << (i * 8));
for (j = 0; j < 2; j++) {
tcg_gen_shli_i64(tmp, avr[j], i * 7);
tcg_gen_and_i64(tmp, tmp, tcg_mask);
tcg_gen_or_i64(result[j], result[j], tmp);
}
}
for (j = 0; j < 2; j++) {
set_avr64(VT, result[j], j);
}
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tcg_mask);
tcg_temp_free_i64(result[0]);
tcg_temp_free_i64(result[1]);
tcg_temp_free_i64(avr[0]);
tcg_temp_free_i64(avr[1]);
}
/*
* vclzw VRT,VRB - Vector Count Leading Zeros Word
*
* Counting the number of leading zero bits of each word element in source
* register and placing result in appropriate word element of destination
* register.
*/
static void trans_vclzw(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i32 tmp = tcg_temp_new_i32();
int i;
/* Perform count for every word element using tcg_gen_clzi_i32. */
for (i = 0; i < 4; i++) {
tcg_gen_ld_i32(tmp, cpu_env,
offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4);
tcg_gen_clzi_i32(tmp, tmp, 32);
tcg_gen_st_i32(tmp, cpu_env,
offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4);
}
tcg_temp_free_i32(tmp);
}
/*
* vclzd VRT,VRB - Vector Count Leading Zeros Doubleword
*
* Counting the number of leading zero bits of each doubleword element in source
* register and placing result in appropriate doubleword element of destination
* register.
*/
static void trans_vclzd(DisasContext *ctx)
{
int VT = rD(ctx->opcode);
int VB = rB(ctx->opcode);
TCGv_i64 avr = tcg_temp_new_i64();
/* high doubleword */
get_avr64(avr, VB, true);
tcg_gen_clzi_i64(avr, avr, 64);
set_avr64(VT, avr, true);
/* low doubleword */
get_avr64(avr, VB, false);
tcg_gen_clzi_i64(avr, avr, 64);
set_avr64(VT, avr, false);
tcg_temp_free_i64(avr);
}
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
void (*gen_gvec)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
{
REQUIRE_VECTOR(ctx);
gen_gvec(vece, avr_full_offset(a->vrt), avr_full_offset(a->vra),
avr_full_offset(a->vrb), 16, 16);
return true;
}
TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv)
TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb)
{
TCGv_vec t0 = tcg_temp_new_vec_matching(vrb),
t1 = tcg_temp_new_vec_matching(vrb),
t2 = tcg_temp_new_vec_matching(vrb),
ones = tcg_constant_vec_matching(vrb, vece, -1);
/* Extract b and e */
tcg_gen_dupi_vec(vece, t2, (8 << vece) - 1);
tcg_gen_shri_vec(vece, t0, vrb, 16);
tcg_gen_and_vec(vece, t0, t0, t2);
tcg_gen_shri_vec(vece, t1, vrb, 8);
tcg_gen_and_vec(vece, t1, t1, t2);
/* Compare b and e to negate the mask where begin > end */
tcg_gen_cmp_vec(TCG_COND_GT, vece, t2, t0, t1);
/* Create the mask with (~0 >> b) ^ ((~0 >> e) >> 1) */
tcg_gen_shrv_vec(vece, t0, ones, t0);
tcg_gen_shrv_vec(vece, t1, ones, t1);
tcg_gen_shri_vec(vece, t1, t1, 1);
tcg_gen_xor_vec(vece, t0, t0, t1);
/* negate the mask */
tcg_gen_xor_vec(vece, t0, t0, t2);
tcg_temp_free_vec(t1);
tcg_temp_free_vec(t2);
return t0;
}
static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
TCGv_vec vrb)
{
TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt);
/* Create the mask */
mask = do_vrl_mask_vec(vece, vrb);
/* Extract n */
tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
tcg_gen_and_vec(vece, n, vrb, n);
/* Rotate and mask */
tcg_gen_rotlv_vec(vece, vrt, vra, n);
tcg_gen_and_vec(vece, vrt, vrt, mask);
tcg_temp_free_vec(n);
tcg_temp_free_vec(mask);
}
static bool do_vrlnm(DisasContext *ctx, arg_VX *a, int vece)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
};
static const GVecGen3 ops[2] = {
{
.fniv = gen_vrlnm_vec,
.fno = gen_helper_VRLWNM,
.opt_opc = vecop_list,
.load_dest = true,
.vece = MO_32
},
{
.fniv = gen_vrlnm_vec,
.fno = gen_helper_VRLDNM,
.opt_opc = vecop_list,
.load_dest = true,
.vece = MO_64
}
};
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
return true;
}
TRANS(VRLWNM, do_vrlnm, MO_32)
TRANS(VRLDNM, do_vrlnm, MO_64)
static void gen_vrlmi_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
TCGv_vec vrb)
{
TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt),
tmp = tcg_temp_new_vec_matching(vrt);
/* Create the mask */
mask = do_vrl_mask_vec(vece, vrb);
/* Extract n */
tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
tcg_gen_and_vec(vece, n, vrb, n);
/* Rotate and insert */
tcg_gen_rotlv_vec(vece, tmp, vra, n);
tcg_gen_bitsel_vec(vece, vrt, mask, tmp, vrt);
tcg_temp_free_vec(n);
tcg_temp_free_vec(tmp);
tcg_temp_free_vec(mask);
}
static bool do_vrlmi(DisasContext *ctx, arg_VX *a, int vece)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
};
static const GVecGen3 ops[2] = {
{
.fniv = gen_vrlmi_vec,
.fno = gen_helper_VRLWMI,
.opt_opc = vecop_list,
.load_dest = true,
.vece = MO_32
},
{
.fniv = gen_vrlnm_vec,
.fno = gen_helper_VRLDMI,
.opt_opc = vecop_list,
.load_dest = true,
.vece = MO_64
}
};
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
return true;
}
TRANS(VRLWMI, do_vrlmi, MO_32)
TRANS(VRLDMI, do_vrlmi, MO_64)
static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
bool alg)
{
TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx);
n = tcg_temp_new_i64();
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_const_i64(0);
get_avr64(lo, a->vra, false);