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armv7m_nvic.c
2771 lines (2530 loc) · 93.4 KB
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armv7m_nvic.c
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/*
* ARM Nested Vectored Interrupt Controller
*
* Copyright (c) 2006-2007 CodeSourcery.
* Written by Paul Brook
*
* This code is licensed under the GPL.
*
* The ARMv7M System controller is fairly tightly tied in with the
* NVIC. Much of that is also implemented here.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/timer.h"
#include "hw/intc/armv7m_nvic.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "target/arm/cpu.h"
#include "exec/exec-all.h"
#include "exec/memop.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
/* IRQ number counting:
*
* the num-irq property counts the number of external IRQ lines
*
* NVICState::num_irq counts the total number of exceptions
* (external IRQs, the 15 internal exceptions including reset,
* and one for the unused exception number 0).
*
* NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
*
* NVIC_MAX_VECTORS is the highest permitted number of exceptions.
*
* Iterating through all exceptions should typically be done with
* for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
*
* The external qemu_irq lines are the NVIC's external IRQ lines,
* so line 0 is exception 16.
*
* In the terminology of the architecture manual, "interrupts" are
* a subcategory of exception referring to the external interrupts
* (which are exception numbers NVIC_FIRST_IRQ and upward).
* For historical reasons QEMU tends to use "interrupt" and
* "exception" more or less interchangeably.
*/
#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
#define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
/* Effective running priority of the CPU when no exception is active
* (higher than the highest possible priority value)
*/
#define NVIC_NOEXC_PRIO 0x100
/* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
#define NVIC_NS_PRIO_LIMIT 0x80
static const uint8_t nvic_id[] = {
0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
};
static int nvic_pending_prio(NVICState *s)
{
/* return the group priority of the current pending interrupt,
* or NVIC_NOEXC_PRIO if no interrupt is pending
*/
return s->vectpending_prio;
}
/* Return the value of the ISCR RETTOBASE bit:
* 1 if there is exactly one active exception
* 0 if there is more than one active exception
* UNKNOWN if there are no active exceptions (we choose 1,
* which matches the choice Cortex-M3 is documented as making).
*
* NB: some versions of the documentation talk about this
* counting "active exceptions other than the one shown by IPSR";
* this is only different in the obscure corner case where guest
* code has manually deactivated an exception and is about
* to fail an exception-return integrity check. The definition
* above is the one from the v8M ARM ARM and is also in line
* with the behaviour documented for the Cortex-M3.
*/
static bool nvic_rettobase(NVICState *s)
{
int irq, nhand = 0;
bool check_sec = arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);
for (irq = ARMV7M_EXCP_RESET; irq < s->num_irq; irq++) {
if (s->vectors[irq].active ||
(check_sec && irq < NVIC_INTERNAL_VECTORS &&
s->sec_vectors[irq].active)) {
nhand++;
if (nhand == 2) {
return 0;
}
}
}
return 1;
}
/* Return the value of the ISCR ISRPENDING bit:
* 1 if an external interrupt is pending
* 0 if no external interrupt is pending
*/
static bool nvic_isrpending(NVICState *s)
{
int irq;
/* We can shortcut if the highest priority pending interrupt
* happens to be external or if there is nothing pending.
*/
if (s->vectpending > NVIC_FIRST_IRQ) {
return true;
}
if (s->vectpending == 0) {
return false;
}
for (irq = NVIC_FIRST_IRQ; irq < s->num_irq; irq++) {
if (s->vectors[irq].pending) {
return true;
}
}
return false;
}
static bool exc_is_banked(int exc)
{
/* Return true if this is one of the limited set of exceptions which
* are banked (and thus have state in sec_vectors[])
*/
return exc == ARMV7M_EXCP_HARD ||
exc == ARMV7M_EXCP_MEM ||
exc == ARMV7M_EXCP_USAGE ||
exc == ARMV7M_EXCP_SVC ||
exc == ARMV7M_EXCP_PENDSV ||
exc == ARMV7M_EXCP_SYSTICK;
}
/* Return a mask word which clears the subpriority bits from
* a priority value for an M-profile exception, leaving only
* the group priority.
*/
static inline uint32_t nvic_gprio_mask(NVICState *s, bool secure)
{
return ~0U << (s->prigroup[secure] + 1);
}
static bool exc_targets_secure(NVICState *s, int exc)
{
/* Return true if this non-banked exception targets Secure state. */
if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
return false;
}
if (exc >= NVIC_FIRST_IRQ) {
return !s->itns[exc];
}
/* Function shouldn't be called for banked exceptions. */
assert(!exc_is_banked(exc));
switch (exc) {
case ARMV7M_EXCP_NMI:
case ARMV7M_EXCP_BUS:
return !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK);
case ARMV7M_EXCP_SECURE:
return true;
case ARMV7M_EXCP_DEBUG:
/* TODO: controlled by DEMCR.SDME, which we don't yet implement */
return false;
default:
/* reset, and reserved (unused) low exception numbers.
* We'll get called by code that loops through all the exception
* numbers, but it doesn't matter what we return here as these
* non-existent exceptions will never be pended or active.
*/
return true;
}
}
static int exc_group_prio(NVICState *s, int rawprio, bool targets_secure)
{
/* Return the group priority for this exception, given its raw
* (group-and-subgroup) priority value and whether it is targeting
* secure state or not.
*/
if (rawprio < 0) {
return rawprio;
}
rawprio &= nvic_gprio_mask(s, targets_secure);
/* AIRCR.PRIS causes us to squash all NS priorities into the
* lower half of the total range
*/
if (!targets_secure &&
(s->cpu->env.v7m.aircr & R_V7M_AIRCR_PRIS_MASK)) {
rawprio = (rawprio >> 1) + NVIC_NS_PRIO_LIMIT;
}
return rawprio;
}
/* Recompute vectpending and exception_prio for a CPU which implements
* the Security extension
*/
static void nvic_recompute_state_secure(NVICState *s)
{
int i, bank;
int pend_prio = NVIC_NOEXC_PRIO;
int active_prio = NVIC_NOEXC_PRIO;
int pend_irq = 0;
bool pending_is_s_banked = false;
int pend_subprio = 0;
/* R_CQRV: precedence is by:
* - lowest group priority; if both the same then
* - lowest subpriority; if both the same then
* - lowest exception number; if both the same (ie banked) then
* - secure exception takes precedence
* Compare pseudocode RawExecutionPriority.
* Annoyingly, now we have two prigroup values (for S and NS)
* we can't do the loop comparison on raw priority values.
*/
for (i = 1; i < s->num_irq; i++) {
for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
VecInfo *vec;
int prio, subprio;
bool targets_secure;
if (bank == M_REG_S) {
if (!exc_is_banked(i)) {
continue;
}
vec = &s->sec_vectors[i];
targets_secure = true;
} else {
vec = &s->vectors[i];
targets_secure = !exc_is_banked(i) && exc_targets_secure(s, i);
}
prio = exc_group_prio(s, vec->prio, targets_secure);
subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure);
if (vec->enabled && vec->pending &&
((prio < pend_prio) ||
(prio == pend_prio && prio >= 0 && subprio < pend_subprio))) {
pend_prio = prio;
pend_subprio = subprio;
pend_irq = i;
pending_is_s_banked = (bank == M_REG_S);
}
if (vec->active && prio < active_prio) {
active_prio = prio;
}
}
}
s->vectpending_is_s_banked = pending_is_s_banked;
s->vectpending = pend_irq;
s->vectpending_prio = pend_prio;
s->exception_prio = active_prio;
trace_nvic_recompute_state_secure(s->vectpending,
s->vectpending_is_s_banked,
s->vectpending_prio,
s->exception_prio);
}
/* Recompute vectpending and exception_prio */
static void nvic_recompute_state(NVICState *s)
{
int i;
int pend_prio = NVIC_NOEXC_PRIO;
int active_prio = NVIC_NOEXC_PRIO;
int pend_irq = 0;
/* In theory we could write one function that handled both
* the "security extension present" and "not present"; however
* the security related changes significantly complicate the
* recomputation just by themselves and mixing both cases together
* would be even worse, so we retain a separate non-secure-only
* version for CPUs which don't implement the security extension.
*/
if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {
nvic_recompute_state_secure(s);
return;
}
for (i = 1; i < s->num_irq; i++) {
VecInfo *vec = &s->vectors[i];
if (vec->enabled && vec->pending && vec->prio < pend_prio) {
pend_prio = vec->prio;
pend_irq = i;
}
if (vec->active && vec->prio < active_prio) {
active_prio = vec->prio;
}
}
if (active_prio > 0) {
active_prio &= nvic_gprio_mask(s, false);
}
if (pend_prio > 0) {
pend_prio &= nvic_gprio_mask(s, false);
}
s->vectpending = pend_irq;
s->vectpending_prio = pend_prio;
s->exception_prio = active_prio;
trace_nvic_recompute_state(s->vectpending,
s->vectpending_prio,
s->exception_prio);
}
/* Return the current execution priority of the CPU
* (equivalent to the pseudocode ExecutionPriority function).
* This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
*/
static inline int nvic_exec_prio(NVICState *s)
{
CPUARMState *env = &s->cpu->env;
int running = NVIC_NOEXC_PRIO;
if (env->v7m.basepri[M_REG_NS] > 0) {
running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);
}
if (env->v7m.basepri[M_REG_S] > 0) {
int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);
if (running > basepri) {
running = basepri;
}
}
if (env->v7m.primask[M_REG_NS]) {
if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
if (running > NVIC_NS_PRIO_LIMIT) {
running = NVIC_NS_PRIO_LIMIT;
}
} else {
running = 0;
}
}
if (env->v7m.primask[M_REG_S]) {
running = 0;
}
if (env->v7m.faultmask[M_REG_NS]) {
if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
running = -1;
} else {
if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {
if (running > NVIC_NS_PRIO_LIMIT) {
running = NVIC_NS_PRIO_LIMIT;
}
} else {
running = 0;
}
}
}
if (env->v7m.faultmask[M_REG_S]) {
running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;
}
/* consider priority of active handler */
return MIN(running, s->exception_prio);
}
bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
{
/* Return true if the requested execution priority is negative
* for the specified security state, ie that security state
* has an active NMI or HardFault or has set its FAULTMASK.
* Note that this is not the same as whether the execution
* priority is actually negative (for instance AIRCR.PRIS may
* mean we don't allow FAULTMASK_NS to actually make the execution
* priority negative). Compare pseudocode IsReqExcPriNeg().
*/
NVICState *s = opaque;
if (s->cpu->env.v7m.faultmask[secure]) {
return true;
}
if (secure ? s->sec_vectors[ARMV7M_EXCP_HARD].active :
s->vectors[ARMV7M_EXCP_HARD].active) {
return true;
}
if (s->vectors[ARMV7M_EXCP_NMI].active &&
exc_targets_secure(s, ARMV7M_EXCP_NMI) == secure) {
return true;
}
return false;
}
bool armv7m_nvic_can_take_pending_exception(void *opaque)
{
NVICState *s = opaque;
return nvic_exec_prio(s) > nvic_pending_prio(s);
}
int armv7m_nvic_raw_execution_priority(void *opaque)
{
NVICState *s = opaque;
return s->exception_prio;
}
/* caller must call nvic_irq_update() after this.
* secure indicates the bank to use for banked exceptions (we assert if
* we are passed secure=true for a non-banked exception).
*/
static void set_prio(NVICState *s, unsigned irq, bool secure, uint8_t prio)
{
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
assert(irq < s->num_irq);
prio &= MAKE_64BIT_MASK(8 - s->num_prio_bits, s->num_prio_bits);
if (secure) {
assert(exc_is_banked(irq));
s->sec_vectors[irq].prio = prio;
} else {
s->vectors[irq].prio = prio;
}
trace_nvic_set_prio(irq, secure, prio);
}
/* Return the current raw priority register value.
* secure indicates the bank to use for banked exceptions (we assert if
* we are passed secure=true for a non-banked exception).
*/
static int get_prio(NVICState *s, unsigned irq, bool secure)
{
assert(irq > ARMV7M_EXCP_NMI); /* only use for configurable prios */
assert(irq < s->num_irq);
if (secure) {
assert(exc_is_banked(irq));
return s->sec_vectors[irq].prio;
} else {
return s->vectors[irq].prio;
}
}
/* Recompute state and assert irq line accordingly.
* Must be called after changes to:
* vec->active, vec->enabled, vec->pending or vec->prio for any vector
* prigroup
*/
static void nvic_irq_update(NVICState *s)
{
int lvl;
int pend_prio;
nvic_recompute_state(s);
pend_prio = nvic_pending_prio(s);
/* Raise NVIC output if this IRQ would be taken, except that we
* ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
* will be checked for in arm_v7m_cpu_exec_interrupt()); changes
* to those CPU registers don't cause us to recalculate the NVIC
* pending info.
*/
lvl = (pend_prio < s->exception_prio);
trace_nvic_irq_update(s->vectpending, pend_prio, s->exception_prio, lvl);
qemu_set_irq(s->excpout, lvl);
}
/**
* armv7m_nvic_clear_pending: mark the specified exception as not pending
* @opaque: the NVIC
* @irq: the exception number to mark as not pending
* @secure: false for non-banked exceptions or for the nonsecure
* version of a banked exception, true for the secure version of a banked
* exception.
*
* Marks the specified exception as not pending. Note that we will assert()
* if @secure is true and @irq does not specify one of the fixed set
* of architecturally banked exceptions.
*/
static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)
{
NVICState *s = (NVICState *)opaque;
VecInfo *vec;
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
if (secure) {
assert(exc_is_banked(irq));
vec = &s->sec_vectors[irq];
} else {
vec = &s->vectors[irq];
}
trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);
if (vec->pending) {
vec->pending = 0;
nvic_irq_update(s);
}
}
static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
bool derived)
{
/* Pend an exception, including possibly escalating it to HardFault.
*
* This function handles both "normal" pending of interrupts and
* exceptions, and also derived exceptions (ones which occur as
* a result of trying to take some other exception).
*
* If derived == true, the caller guarantees that we are part way through
* trying to take an exception (but have not yet called
* armv7m_nvic_acknowledge_irq() to make it active), and so:
* - s->vectpending is the "original exception" we were trying to take
* - irq is the "derived exception"
* - nvic_exec_prio(s) gives the priority before exception entry
* Here we handle the prioritization logic which the pseudocode puts
* in the DerivedLateArrival() function.
*/
NVICState *s = (NVICState *)opaque;
bool banked = exc_is_banked(irq);
VecInfo *vec;
bool targets_secure;
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
assert(!secure || banked);
vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
targets_secure = banked ? secure : exc_targets_secure(s, irq);
trace_nvic_set_pending(irq, secure, targets_secure,
derived, vec->enabled, vec->prio);
if (derived) {
/* Derived exceptions are always synchronous. */
assert(irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV);
if (irq == ARMV7M_EXCP_DEBUG &&
exc_group_prio(s, vec->prio, secure) >= nvic_exec_prio(s)) {
/* DebugMonitorFault, but its priority is lower than the
* preempted exception priority: just ignore it.
*/
return;
}
if (irq == ARMV7M_EXCP_HARD && vec->prio >= s->vectpending_prio) {
/* If this is a terminal exception (one which means we cannot
* take the original exception, like a failure to read its
* vector table entry), then we must take the derived exception.
* If the derived exception can't take priority over the
* original exception, then we go into Lockup.
*
* For QEMU, we rely on the fact that a derived exception is
* terminal if and only if it's reported to us as HardFault,
* which saves having to have an extra argument is_terminal
* that we'd only use in one place.
*/
cpu_abort(&s->cpu->parent_obj,
"Lockup: can't take terminal derived exception "
"(original exception priority %d)\n",
s->vectpending_prio);
}
/* We now continue with the same code as for a normal pending
* exception, which will cause us to pend the derived exception.
* We'll then take either the original or the derived exception
* based on which is higher priority by the usual mechanism
* for selecting the highest priority pending interrupt.
*/
}
if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {
/* If a synchronous exception is pending then it may be
* escalated to HardFault if:
* * it is equal or lower priority to current execution
* * it is disabled
* (ie we need to take it immediately but we can't do so).
* Asynchronous exceptions (and interrupts) simply remain pending.
*
* For QEMU, we don't have any imprecise (asynchronous) faults,
* so we can assume that PREFETCH_ABORT and DATA_ABORT are always
* synchronous.
* Debug exceptions are awkward because only Debug exceptions
* resulting from the BKPT instruction should be escalated,
* but we don't currently implement any Debug exceptions other
* than those that result from BKPT, so we treat all debug exceptions
* as needing escalation.
*
* This all means we can identify whether to escalate based only on
* the exception number and don't (yet) need the caller to explicitly
* tell us whether this exception is synchronous or not.
*/
int running = nvic_exec_prio(s);
bool escalate = false;
if (exc_group_prio(s, vec->prio, secure) >= running) {
trace_nvic_escalate_prio(irq, vec->prio, running);
escalate = true;
} else if (!vec->enabled) {
trace_nvic_escalate_disabled(irq);
escalate = true;
}
if (escalate) {
/* We need to escalate this exception to a synchronous HardFault.
* If BFHFNMINS is set then we escalate to the banked HF for
* the target security state of the original exception; otherwise
* we take a Secure HardFault.
*/
irq = ARMV7M_EXCP_HARD;
if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
(targets_secure ||
!(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
vec = &s->sec_vectors[irq];
} else {
vec = &s->vectors[irq];
}
if (running <= vec->prio) {
/* We want to escalate to HardFault but we can't take the
* synchronous HardFault at this point either. This is a
* Lockup condition due to a guest bug. We don't model
* Lockup, so report via cpu_abort() instead.
*/
cpu_abort(&s->cpu->parent_obj,
"Lockup: can't escalate %d to HardFault "
"(current priority %d)\n", irq, running);
}
/* HF may be banked but there is only one shared HFSR */
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
}
}
if (!vec->pending) {
vec->pending = 1;
nvic_irq_update(s);
}
}
void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)
{
do_armv7m_nvic_set_pending(opaque, irq, secure, false);
}
void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure)
{
do_armv7m_nvic_set_pending(opaque, irq, secure, true);
}
void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure)
{
/*
* Pend an exception during lazy FP stacking. This differs
* from the usual exception pending because the logic for
* whether we should escalate depends on the saved context
* in the FPCCR register, not on the current state of the CPU/NVIC.
*/
NVICState *s = (NVICState *)opaque;
bool banked = exc_is_banked(irq);
VecInfo *vec;
bool targets_secure;
bool escalate = false;
/*
* We will only look at bits in fpccr if this is a banked exception
* (in which case 'secure' tells us whether it is the S or NS version).
* All the bits for the non-banked exceptions are in fpccr_s.
*/
uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S];
uint32_t fpccr = s->cpu->env.v7m.fpccr[secure];
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
assert(!secure || banked);
vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
targets_secure = banked ? secure : exc_targets_secure(s, irq);
switch (irq) {
case ARMV7M_EXCP_DEBUG:
if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) {
/* Ignore DebugMonitor exception */
return;
}
break;
case ARMV7M_EXCP_MEM:
escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK);
break;
case ARMV7M_EXCP_USAGE:
escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK);
break;
case ARMV7M_EXCP_BUS:
escalate = !(fpccr_s & R_V7M_FPCCR_BFRDY_MASK);
break;
case ARMV7M_EXCP_SECURE:
escalate = !(fpccr_s & R_V7M_FPCCR_SFRDY_MASK);
break;
default:
g_assert_not_reached();
}
if (escalate) {
/*
* Escalate to HardFault: faults that initially targeted Secure
* continue to do so, even if HF normally targets NonSecure.
*/
irq = ARMV7M_EXCP_HARD;
if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
(targets_secure ||
!(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
vec = &s->sec_vectors[irq];
} else {
vec = &s->vectors[irq];
}
}
if (!vec->enabled ||
nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) {
if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) {
/*
* We want to escalate to HardFault but the context the
* FP state belongs to prevents the exception pre-empting.
*/
cpu_abort(&s->cpu->parent_obj,
"Lockup: can't escalate to HardFault during "
"lazy FP register stacking\n");
}
}
if (escalate) {
s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
}
if (!vec->pending) {
vec->pending = 1;
/*
* We do not call nvic_irq_update(), because we know our caller
* is going to handle causing us to take the exception by
* raising EXCP_LAZYFP, so raising the IRQ line would be
* pointless extra work. We just need to recompute the
* priorities so that armv7m_nvic_can_take_pending_exception()
* returns the right answer.
*/
nvic_recompute_state(s);
}
}
/* Make pending IRQ active. */
void armv7m_nvic_acknowledge_irq(void *opaque)
{
NVICState *s = (NVICState *)opaque;
CPUARMState *env = &s->cpu->env;
const int pending = s->vectpending;
const int running = nvic_exec_prio(s);
VecInfo *vec;
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
if (s->vectpending_is_s_banked) {
vec = &s->sec_vectors[pending];
} else {
vec = &s->vectors[pending];
}
assert(vec->enabled);
assert(vec->pending);
assert(s->vectpending_prio < running);
trace_nvic_acknowledge_irq(pending, s->vectpending_prio);
vec->active = 1;
vec->pending = 0;
write_v7m_exception(env, s->vectpending);
nvic_irq_update(s);
}
void armv7m_nvic_get_pending_irq_info(void *opaque,
int *pirq, bool *ptargets_secure)
{
NVICState *s = (NVICState *)opaque;
const int pending = s->vectpending;
bool targets_secure;
assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);
if (s->vectpending_is_s_banked) {
targets_secure = true;
} else {
targets_secure = !exc_is_banked(pending) &&
exc_targets_secure(s, pending);
}
trace_nvic_get_pending_irq_info(pending, targets_secure);
*ptargets_secure = targets_secure;
*pirq = pending;
}
int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
{
NVICState *s = (NVICState *)opaque;
VecInfo *vec = NULL;
int ret;
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
/*
* For negative priorities, v8M will forcibly deactivate the appropriate
* NMI or HardFault regardless of what interrupt we're being asked to
* deactivate (compare the DeActivate() pseudocode). This is a guard
* against software returning from NMI or HardFault with a corrupted
* IPSR and leaving the CPU in a negative-priority state.
* v7M does not do this, but simply deactivates the requested interrupt.
*/
if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
switch (armv7m_nvic_raw_execution_priority(s)) {
case -1:
if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {
vec = &s->vectors[ARMV7M_EXCP_HARD];
} else {
vec = &s->sec_vectors[ARMV7M_EXCP_HARD];
}
break;
case -2:
vec = &s->vectors[ARMV7M_EXCP_NMI];
break;
case -3:
vec = &s->sec_vectors[ARMV7M_EXCP_HARD];
break;
default:
break;
}
}
if (!vec) {
if (secure && exc_is_banked(irq)) {
vec = &s->sec_vectors[irq];
} else {
vec = &s->vectors[irq];
}
}
trace_nvic_complete_irq(irq, secure);
if (!vec->active) {
/* Tell the caller this was an illegal exception return */
return -1;
}
/*
* If this is a configurable exception and it is currently
* targeting the opposite security state from the one we're trying
* to complete it for, this counts as an illegal exception return.
* We still need to deactivate whatever vector the logic above has
* selected, though, as it might not be the same as the one for the
* requested exception number.
*/
if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
ret = -1;
} else {
ret = nvic_rettobase(s);
}
vec->active = 0;
if (vec->level) {
/* Re-pend the exception if it's still held high; only
* happens for extenal IRQs
*/
assert(irq >= NVIC_FIRST_IRQ);
vec->pending = 1;
}
nvic_irq_update(s);
return ret;
}
bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
{
/*
* Return whether an exception is "ready", i.e. it is enabled and is
* configured at a priority which would allow it to interrupt the
* current execution priority.
*
* irq and secure have the same semantics as for armv7m_nvic_set_pending():
* for non-banked exceptions secure is always false; for banked exceptions
* it indicates which of the exceptions is required.
*/
NVICState *s = (NVICState *)opaque;
bool banked = exc_is_banked(irq);
VecInfo *vec;
int running = nvic_exec_prio(s);
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
assert(!secure || banked);
/*
* HardFault is an odd special case: we always check against -1,
* even if we're secure and HardFault has priority -3; we never
* need to check for enabled state.
*/
if (irq == ARMV7M_EXCP_HARD) {
return running > -1;
}
vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
return vec->enabled &&
exc_group_prio(s, vec->prio, secure) < running;
}
/* callback when external interrupt line is changed */
static void set_irq_level(void *opaque, int n, int level)
{
NVICState *s = opaque;
VecInfo *vec;
n += NVIC_FIRST_IRQ;
assert(n >= NVIC_FIRST_IRQ && n < s->num_irq);
trace_nvic_set_irq_level(n, level);
/* The pending status of an external interrupt is
* latched on rising edge and exception handler return.
*
* Pulsing the IRQ will always run the handler
* once, and the handler will re-run until the
* level is low when the handler completes.
*/
vec = &s->vectors[n];
if (level != vec->level) {
vec->level = level;
if (level) {
armv7m_nvic_set_pending(s, n, false);
}
}
}
/* callback when external NMI line is changed */
static void nvic_nmi_trigger(void *opaque, int n, int level)
{
NVICState *s = opaque;
trace_nvic_set_nmi_level(level);
/*
* The architecture doesn't specify whether NMI should share
* the normal-interrupt behaviour of being resampled on
* exception handler return. We choose not to, so just
* set NMI pending here and don't track the current level.
*/
if (level) {
armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);
}
}
static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{
ARMCPU *cpu = s->cpu;
uint32_t val;
switch (offset) {
case 4: /* Interrupt Control Type. */
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
goto bad_offset;
}
return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;
case 0xc: /* CPPWR */
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset;
}
/* We make the IMPDEF choice that nothing can ever go into a
* non-retentive power state, which allows us to RAZ/WI this.
*/
return 0;
case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
{
int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;
int i;
if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {
goto bad_offset;