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pc.c
2902 lines (2502 loc) · 92.8 KB
/
pc.c
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/*
* QEMU PC System Emulator
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/hw.h"
#include "hw/i386/pc.h"
#include "hw/char/serial.h"
#include "hw/char/parallel.h"
#include "hw/i386/apic.h"
#include "hw/i386/topology.h"
#include "hw/i386/fw_cfg.h"
#include "sysemu/cpus.h"
#include "hw/block/fdc.h"
#include "hw/ide.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bus.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/timer/hpet.h"
#include "hw/firmware/smbios.h"
#include "hw/loader.h"
#include "elf.h"
#include "multiboot.h"
#include "hw/timer/mc146818rtc.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/input/i8042.h"
#include "hw/audio/pcspk.h"
#include "hw/pci/msi.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "sysemu/tcg.h"
#include "sysemu/numa.h"
#include "sysemu/kvm.h"
#include "sysemu/qtest.h"
#include "kvm_i386.h"
#include "hw/xen/xen.h"
#include "hw/xen/start_info.h"
#include "ui/qemu-spice.h"
#include "exec/memory.h"
#include "exec/address-spaces.h"
#include "sysemu/arch_init.h"
#include "qemu/bitmap.h"
#include "qemu/config-file.h"
#include "qemu/error-report.h"
#include "qemu/option.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/boards.h"
#include "acpi-build.h"
#include "hw/mem/pc-dimm.h"
#include "qapi/error.h"
#include "qapi/qapi-visit-common.h"
#include "qapi/visitor.h"
#include "qom/cpu.h"
#include "hw/nmi.h"
#include "hw/usb.h"
#include "hw/i386/intel_iommu.h"
#include "hw/net/ne2000-isa.h"
#include "standard-headers/asm-x86/bootparam.h"
#include "hw/virtio/virtio-pmem-pci.h"
#include "hw/mem/memory-device.h"
/* debug PC/ISA interrupts */
//#define DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DPRINTF(fmt, ...) \
do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif
#define E820_NR_ENTRIES 16
struct e820_entry {
uint64_t address;
uint64_t length;
uint32_t type;
} QEMU_PACKED __attribute((__aligned__(4)));
struct e820_table {
uint32_t count;
struct e820_entry entry[E820_NR_ENTRIES];
} QEMU_PACKED __attribute((__aligned__(4)));
static struct e820_table e820_reserve;
static struct e820_entry *e820_table;
static unsigned e820_entries;
struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
GlobalProperty pc_compat_4_0[] = {};
const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
GlobalProperty pc_compat_3_1[] = {
{ "intel-iommu", "dma-drain", "off" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "npt", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "npt", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "EPYC" "-" TYPE_X86_CPU, "npt", "off" },
{ "EPYC" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "EPYC-IBPB" "-" TYPE_X86_CPU, "npt", "off" },
{ "EPYC-IBPB" "-" TYPE_X86_CPU, "nrip-save", "off" },
{ "Skylake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Client-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Client" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Icelake-Server" "-" TYPE_X86_CPU, "mpx", "on" },
{ "Cascadelake-Server" "-" TYPE_X86_CPU, "stepping", "5" },
{ TYPE_X86_CPU, "x-intel-pt-auto-level", "off" },
};
const size_t pc_compat_3_1_len = G_N_ELEMENTS(pc_compat_3_1);
GlobalProperty pc_compat_3_0[] = {
{ TYPE_X86_CPU, "x-hv-synic-kvm-only", "on" },
{ "Skylake-Server" "-" TYPE_X86_CPU, "pku", "off" },
{ "Skylake-Server-IBRS" "-" TYPE_X86_CPU, "pku", "off" },
};
const size_t pc_compat_3_0_len = G_N_ELEMENTS(pc_compat_3_0);
GlobalProperty pc_compat_2_12[] = {
{ TYPE_X86_CPU, "legacy-cache", "on" },
{ TYPE_X86_CPU, "topoext", "off" },
{ "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
{ "EPYC-IBPB-" TYPE_X86_CPU, "xlevel", "0x8000000a" },
};
const size_t pc_compat_2_12_len = G_N_ELEMENTS(pc_compat_2_12);
GlobalProperty pc_compat_2_11[] = {
{ TYPE_X86_CPU, "x-migrate-smi-count", "off" },
{ "Skylake-Server" "-" TYPE_X86_CPU, "clflushopt", "off" },
};
const size_t pc_compat_2_11_len = G_N_ELEMENTS(pc_compat_2_11);
GlobalProperty pc_compat_2_10[] = {
{ TYPE_X86_CPU, "x-hv-max-vps", "0x40" },
{ "i440FX-pcihost", "x-pci-hole64-fix", "off" },
{ "q35-pcihost", "x-pci-hole64-fix", "off" },
};
const size_t pc_compat_2_10_len = G_N_ELEMENTS(pc_compat_2_10);
GlobalProperty pc_compat_2_9[] = {
{ "mch", "extended-tseg-mbytes", "0" },
};
const size_t pc_compat_2_9_len = G_N_ELEMENTS(pc_compat_2_9);
GlobalProperty pc_compat_2_8[] = {
{ TYPE_X86_CPU, "tcg-cpuid", "off" },
{ "kvmclock", "x-mach-use-reliable-get-clock", "off" },
{ "ICH9-LPC", "x-smi-broadcast", "off" },
{ TYPE_X86_CPU, "vmware-cpuid-freq", "off" },
{ "Haswell-" TYPE_X86_CPU, "stepping", "1" },
};
const size_t pc_compat_2_8_len = G_N_ELEMENTS(pc_compat_2_8);
GlobalProperty pc_compat_2_7[] = {
{ TYPE_X86_CPU, "l3-cache", "off" },
{ TYPE_X86_CPU, "full-cpuid-auto-level", "off" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "family", "15" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "model", "6" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "stepping", "1" },
{ "isa-pcspk", "migrate", "off" },
};
const size_t pc_compat_2_7_len = G_N_ELEMENTS(pc_compat_2_7);
GlobalProperty pc_compat_2_6[] = {
{ TYPE_X86_CPU, "cpuid-0xb", "off" },
{ "vmxnet3", "romfile", "" },
{ TYPE_X86_CPU, "fill-mtrr-mask", "off" },
{ "apic-common", "legacy-instance-id", "on", }
};
const size_t pc_compat_2_6_len = G_N_ELEMENTS(pc_compat_2_6);
GlobalProperty pc_compat_2_5[] = {};
const size_t pc_compat_2_5_len = G_N_ELEMENTS(pc_compat_2_5);
GlobalProperty pc_compat_2_4[] = {
PC_CPU_MODEL_IDS("2.4.0")
{ "Haswell-" TYPE_X86_CPU, "abm", "off" },
{ "Haswell-noTSX-" TYPE_X86_CPU, "abm", "off" },
{ "Broadwell-" TYPE_X86_CPU, "abm", "off" },
{ "Broadwell-noTSX-" TYPE_X86_CPU, "abm", "off" },
{ "host" "-" TYPE_X86_CPU, "host-cache-info", "on" },
{ TYPE_X86_CPU, "check", "off" },
{ "qemu64" "-" TYPE_X86_CPU, "sse4a", "on" },
{ "qemu64" "-" TYPE_X86_CPU, "abm", "on" },
{ "qemu64" "-" TYPE_X86_CPU, "popcnt", "on" },
{ "qemu32" "-" TYPE_X86_CPU, "popcnt", "on" },
{ "Opteron_G2" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "rdtscp", "on" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "rdtscp", "on", }
};
const size_t pc_compat_2_4_len = G_N_ELEMENTS(pc_compat_2_4);
GlobalProperty pc_compat_2_3[] = {
PC_CPU_MODEL_IDS("2.3.0")
{ TYPE_X86_CPU, "arat", "off" },
{ "qemu64" "-" TYPE_X86_CPU, "min-level", "4" },
{ "kvm64" "-" TYPE_X86_CPU, "min-level", "5" },
{ "pentium3" "-" TYPE_X86_CPU, "min-level", "2" },
{ "n270" "-" TYPE_X86_CPU, "min-level", "5" },
{ "Conroe" "-" TYPE_X86_CPU, "min-level", "4" },
{ "Penryn" "-" TYPE_X86_CPU, "min-level", "4" },
{ "Nehalem" "-" TYPE_X86_CPU, "min-level", "4" },
{ "n270" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Penryn" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Conroe" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Nehalem" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Westmere" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "SandyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "IvyBridge" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Haswell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Haswell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Broadwell" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ "Broadwell-noTSX" "-" TYPE_X86_CPU, "min-xlevel", "0x8000000a" },
{ TYPE_X86_CPU, "kvm-no-smi-migration", "on" },
};
const size_t pc_compat_2_3_len = G_N_ELEMENTS(pc_compat_2_3);
GlobalProperty pc_compat_2_2[] = {
PC_CPU_MODEL_IDS("2.2.0")
{ "kvm64" "-" TYPE_X86_CPU, "vme", "off" },
{ "kvm32" "-" TYPE_X86_CPU, "vme", "off" },
{ "Conroe" "-" TYPE_X86_CPU, "vme", "off" },
{ "Penryn" "-" TYPE_X86_CPU, "vme", "off" },
{ "Nehalem" "-" TYPE_X86_CPU, "vme", "off" },
{ "Westmere" "-" TYPE_X86_CPU, "vme", "off" },
{ "SandyBridge" "-" TYPE_X86_CPU, "vme", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "vme", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G1" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G2" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G3" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G4" "-" TYPE_X86_CPU, "vme", "off" },
{ "Opteron_G5" "-" TYPE_X86_CPU, "vme", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "f16c", "off" },
{ "Haswell" "-" TYPE_X86_CPU, "rdrand", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "f16c", "off" },
{ "Broadwell" "-" TYPE_X86_CPU, "rdrand", "off" },
};
const size_t pc_compat_2_2_len = G_N_ELEMENTS(pc_compat_2_2);
GlobalProperty pc_compat_2_1[] = {
PC_CPU_MODEL_IDS("2.1.0")
{ "coreduo" "-" TYPE_X86_CPU, "vmx", "on" },
{ "core2duo" "-" TYPE_X86_CPU, "vmx", "on" },
};
const size_t pc_compat_2_1_len = G_N_ELEMENTS(pc_compat_2_1);
GlobalProperty pc_compat_2_0[] = {
PC_CPU_MODEL_IDS("2.0.0")
{ "virtio-scsi-pci", "any_layout", "off" },
{ "PIIX4_PM", "memory-hotplug-support", "off" },
{ "apic", "version", "0x11" },
{ "nec-usb-xhci", "superspeed-ports-first", "off" },
{ "nec-usb-xhci", "force-pcie-endcap", "on" },
{ "pci-serial", "prog_if", "0" },
{ "pci-serial-2x", "prog_if", "0" },
{ "pci-serial-4x", "prog_if", "0" },
{ "virtio-net-pci", "guest_announce", "off" },
{ "ICH9-LPC", "memory-hotplug-support", "off" },
{ "xio3130-downstream", COMPAT_PROP_PCP, "off" },
{ "ioh3420", COMPAT_PROP_PCP, "off" },
};
const size_t pc_compat_2_0_len = G_N_ELEMENTS(pc_compat_2_0);
GlobalProperty pc_compat_1_7[] = {
PC_CPU_MODEL_IDS("1.7.0")
{ TYPE_USB_DEVICE, "msos-desc", "no" },
{ "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
{ "hpet", HPET_INTCAP, "4" },
};
const size_t pc_compat_1_7_len = G_N_ELEMENTS(pc_compat_1_7);
GlobalProperty pc_compat_1_6[] = {
PC_CPU_MODEL_IDS("1.6.0")
{ "e1000", "mitigation", "off" },
{ "qemu64-" TYPE_X86_CPU, "model", "2" },
{ "qemu32-" TYPE_X86_CPU, "model", "3" },
{ "i440FX-pcihost", "short_root_bus", "1" },
{ "q35-pcihost", "short_root_bus", "1" },
};
const size_t pc_compat_1_6_len = G_N_ELEMENTS(pc_compat_1_6);
GlobalProperty pc_compat_1_5[] = {
PC_CPU_MODEL_IDS("1.5.0")
{ "Conroe-" TYPE_X86_CPU, "model", "2" },
{ "Conroe-" TYPE_X86_CPU, "min-level", "2" },
{ "Penryn-" TYPE_X86_CPU, "model", "2" },
{ "Penryn-" TYPE_X86_CPU, "min-level", "2" },
{ "Nehalem-" TYPE_X86_CPU, "model", "2" },
{ "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
{ "virtio-net-pci", "any_layout", "off" },
{ TYPE_X86_CPU, "pmu", "on" },
{ "i440FX-pcihost", "short_root_bus", "0" },
{ "q35-pcihost", "short_root_bus", "0" },
};
const size_t pc_compat_1_5_len = G_N_ELEMENTS(pc_compat_1_5);
GlobalProperty pc_compat_1_4[] = {
PC_CPU_MODEL_IDS("1.4.0")
{ "scsi-hd", "discard_granularity", "0" },
{ "scsi-cd", "discard_granularity", "0" },
{ "scsi-disk", "discard_granularity", "0" },
{ "ide-hd", "discard_granularity", "0" },
{ "ide-cd", "discard_granularity", "0" },
{ "ide-drive", "discard_granularity", "0" },
{ "virtio-blk-pci", "discard_granularity", "0" },
/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string: */
{ "virtio-serial-pci", "vectors", "0xFFFFFFFF" },
{ "virtio-net-pci", "ctrl_guest_offloads", "off" },
{ "e1000", "romfile", "pxe-e1000.rom" },
{ "ne2k_pci", "romfile", "pxe-ne2k_pci.rom" },
{ "pcnet", "romfile", "pxe-pcnet.rom" },
{ "rtl8139", "romfile", "pxe-rtl8139.rom" },
{ "virtio-net-pci", "romfile", "pxe-virtio.rom" },
{ "486-" TYPE_X86_CPU, "model", "0" },
{ "n270" "-" TYPE_X86_CPU, "movbe", "off" },
{ "Westmere" "-" TYPE_X86_CPU, "pclmulqdq", "off" },
};
const size_t pc_compat_1_4_len = G_N_ELEMENTS(pc_compat_1_4);
void gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
if (n < ISA_NUM_IRQS) {
qemu_set_irq(s->i8259_irq[n], level);
}
qemu_set_irq(s->ioapic_irq[n], level);
}
static void ioport80_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
}
static uint64_t ioport80_read(void *opaque, hwaddr addr, unsigned size)
{
return 0xffffffffffffffffULL;
}
/* MSDOS compatibility mode FPU exception support */
static qemu_irq ferr_irq;
void pc_register_ferr_irq(qemu_irq irq)
{
ferr_irq = irq;
}
/* XXX: add IGNNE support */
void cpu_set_ferr(CPUX86State *s)
{
qemu_irq_raise(ferr_irq);
}
static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size)
{
qemu_irq_lower(ferr_irq);
}
static uint64_t ioportF0_read(void *opaque, hwaddr addr, unsigned size)
{
return 0xffffffffffffffffULL;
}
/* TSC handling */
uint64_t cpu_get_tsc(CPUX86State *env)
{
return cpu_get_ticks();
}
/* IRQ handling */
int cpu_get_pic_interrupt(CPUX86State *env)
{
X86CPU *cpu = env_archcpu(env);
int intno;
if (!kvm_irqchip_in_kernel()) {
intno = apic_get_interrupt(cpu->apic_state);
if (intno >= 0) {
return intno;
}
/* read the irq from the PIC */
if (!apic_accept_pic_intr(cpu->apic_state)) {
return -1;
}
}
intno = pic_read_irq(isa_pic);
return intno;
}
static void pic_irq_request(void *opaque, int irq, int level)
{
CPUState *cs = first_cpu;
X86CPU *cpu = X86_CPU(cs);
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
if (cpu->apic_state && !kvm_irqchip_in_kernel()) {
CPU_FOREACH(cs) {
cpu = X86_CPU(cs);
if (apic_accept_pic_intr(cpu->apic_state)) {
apic_deliver_pic_intr(cpu->apic_state, level);
}
}
} else {
if (level) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
}
/* PC cmos mappings */
#define REG_EQUIPMENT_BYTE 0x14
int cmos_get_fd_drive_type(FloppyDriveType fd0)
{
int val;
switch (fd0) {
case FLOPPY_DRIVE_TYPE_144:
/* 1.44 Mb 3"5 drive */
val = 4;
break;
case FLOPPY_DRIVE_TYPE_288:
/* 2.88 Mb 3"5 drive */
val = 5;
break;
case FLOPPY_DRIVE_TYPE_120:
/* 1.2 Mb 5"5 drive */
val = 2;
break;
case FLOPPY_DRIVE_TYPE_NONE:
default:
val = 0;
break;
}
return val;
}
static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
int16_t cylinders, int8_t heads, int8_t sectors)
{
rtc_set_memory(s, type_ofs, 47);
rtc_set_memory(s, info_ofs, cylinders);
rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
rtc_set_memory(s, info_ofs + 2, heads);
rtc_set_memory(s, info_ofs + 3, 0xff);
rtc_set_memory(s, info_ofs + 4, 0xff);
rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
rtc_set_memory(s, info_ofs + 6, cylinders);
rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
rtc_set_memory(s, info_ofs + 8, sectors);
}
/* convert boot_device letter to something recognizable by the bios */
static int boot_device2nibble(char boot_device)
{
switch(boot_device) {
case 'a':
case 'b':
return 0x01; /* floppy boot */
case 'c':
return 0x02; /* hard drive boot */
case 'd':
return 0x03; /* CD-ROM boot */
case 'n':
return 0x04; /* Network boot */
}
return 0;
}
static void set_boot_dev(ISADevice *s, const char *boot_device, Error **errp)
{
#define PC_MAX_BOOT_DEVICES 3
int nbds, bds[3] = { 0, };
int i;
nbds = strlen(boot_device);
if (nbds > PC_MAX_BOOT_DEVICES) {
error_setg(errp, "Too many boot devices for PC");
return;
}
for (i = 0; i < nbds; i++) {
bds[i] = boot_device2nibble(boot_device[i]);
if (bds[i] == 0) {
error_setg(errp, "Invalid boot device for PC: '%c'",
boot_device[i]);
return;
}
}
rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
}
static void pc_boot_set(void *opaque, const char *boot_device, Error **errp)
{
set_boot_dev(opaque, boot_device, errp);
}
static void pc_cmos_init_floppy(ISADevice *rtc_state, ISADevice *floppy)
{
int val, nb, i;
FloppyDriveType fd_type[2] = { FLOPPY_DRIVE_TYPE_NONE,
FLOPPY_DRIVE_TYPE_NONE };
/* floppy type */
if (floppy) {
for (i = 0; i < 2; i++) {
fd_type[i] = isa_fdc_get_drive_type(floppy, i);
}
}
val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
cmos_get_fd_drive_type(fd_type[1]);
rtc_set_memory(rtc_state, 0x10, val);
val = rtc_get_memory(rtc_state, REG_EQUIPMENT_BYTE);
nb = 0;
if (fd_type[0] != FLOPPY_DRIVE_TYPE_NONE) {
nb++;
}
if (fd_type[1] != FLOPPY_DRIVE_TYPE_NONE) {
nb++;
}
switch (nb) {
case 0:
break;
case 1:
val |= 0x01; /* 1 drive, ready for boot */
break;
case 2:
val |= 0x41; /* 2 drives, ready for boot */
break;
}
rtc_set_memory(rtc_state, REG_EQUIPMENT_BYTE, val);
}
typedef struct pc_cmos_init_late_arg {
ISADevice *rtc_state;
BusState *idebus[2];
} pc_cmos_init_late_arg;
typedef struct check_fdc_state {
ISADevice *floppy;
bool multiple;
} CheckFdcState;
static int check_fdc(Object *obj, void *opaque)
{
CheckFdcState *state = opaque;
Object *fdc;
uint32_t iobase;
Error *local_err = NULL;
fdc = object_dynamic_cast(obj, TYPE_ISA_FDC);
if (!fdc) {
return 0;
}
iobase = object_property_get_uint(obj, "iobase", &local_err);
if (local_err || iobase != 0x3f0) {
error_free(local_err);
return 0;
}
if (state->floppy) {
state->multiple = true;
} else {
state->floppy = ISA_DEVICE(obj);
}
return 0;
}
static const char * const fdc_container_path[] = {
"/unattached", "/peripheral", "/peripheral-anon"
};
/*
* Locate the FDC at IO address 0x3f0, in order to configure the CMOS registers
* and ACPI objects.
*/
ISADevice *pc_find_fdc0(void)
{
int i;
Object *container;
CheckFdcState state = { 0 };
for (i = 0; i < ARRAY_SIZE(fdc_container_path); i++) {
container = container_get(qdev_get_machine(), fdc_container_path[i]);
object_child_foreach(container, check_fdc, &state);
}
if (state.multiple) {
warn_report("multiple floppy disk controllers with "
"iobase=0x3f0 have been found");
error_printf("the one being picked for CMOS setup might not reflect "
"your intent");
}
return state.floppy;
}
static void pc_cmos_init_late(void *opaque)
{
pc_cmos_init_late_arg *arg = opaque;
ISADevice *s = arg->rtc_state;
int16_t cylinders;
int8_t heads, sectors;
int val;
int i, trans;
val = 0;
if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0,
&cylinders, &heads, §ors) >= 0) {
cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
val |= 0xf0;
}
if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1,
&cylinders, &heads, §ors) >= 0) {
cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
val |= 0x0f;
}
rtc_set_memory(s, 0x12, val);
val = 0;
for (i = 0; i < 4; i++) {
/* NOTE: ide_get_geometry() returns the physical
geometry. It is always such that: 1 <= sects <= 63, 1
<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
geometry can be different if a translation is done. */
if (arg->idebus[i / 2] &&
ide_get_geometry(arg->idebus[i / 2], i % 2,
&cylinders, &heads, §ors) >= 0) {
trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
assert((trans & ~3) == 0);
val |= trans << (i * 2);
}
}
rtc_set_memory(s, 0x39, val);
pc_cmos_init_floppy(s, pc_find_fdc0());
qemu_unregister_reset(pc_cmos_init_late, opaque);
}
void pc_cmos_init(PCMachineState *pcms,
BusState *idebus0, BusState *idebus1,
ISADevice *s)
{
int val;
static pc_cmos_init_late_arg arg;
/* various important CMOS locations needed by PC/Bochs bios */
/* memory size */
/* base memory (first MiB) */
val = MIN(pcms->below_4g_mem_size / KiB, 640);
rtc_set_memory(s, 0x15, val);
rtc_set_memory(s, 0x16, val >> 8);
/* extended memory (next 64MiB) */
if (pcms->below_4g_mem_size > 1 * MiB) {
val = (pcms->below_4g_mem_size - 1 * MiB) / KiB;
} else {
val = 0;
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x17, val);
rtc_set_memory(s, 0x18, val >> 8);
rtc_set_memory(s, 0x30, val);
rtc_set_memory(s, 0x31, val >> 8);
/* memory between 16MiB and 4GiB */
if (pcms->below_4g_mem_size > 16 * MiB) {
val = (pcms->below_4g_mem_size - 16 * MiB) / (64 * KiB);
} else {
val = 0;
}
if (val > 65535)
val = 65535;
rtc_set_memory(s, 0x34, val);
rtc_set_memory(s, 0x35, val >> 8);
/* memory above 4GiB */
val = pcms->above_4g_mem_size / 65536;
rtc_set_memory(s, 0x5b, val);
rtc_set_memory(s, 0x5c, val >> 8);
rtc_set_memory(s, 0x5d, val >> 16);
object_property_add_link(OBJECT(pcms), "rtc_state",
TYPE_ISA_DEVICE,
(Object **)&pcms->rtc,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG, &error_abort);
object_property_set_link(OBJECT(pcms), OBJECT(s),
"rtc_state", &error_abort);
set_boot_dev(s, MACHINE(pcms)->boot_order, &error_fatal);
val = 0;
val |= 0x02; /* FPU is there */
val |= 0x04; /* PS/2 mouse installed */
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
/* hard drives and FDC */
arg.rtc_state = s;
arg.idebus[0] = idebus0;
arg.idebus[1] = idebus1;
qemu_register_reset(pc_cmos_init_late, &arg);
}
#define TYPE_PORT92 "port92"
#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
/* port 92 stuff: could be split off */
typedef struct Port92State {
ISADevice parent_obj;
MemoryRegion io;
uint8_t outport;
qemu_irq a20_out;
} Port92State;
static void port92_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
Port92State *s = opaque;
int oldval = s->outport;
DPRINTF("port92: write 0x%02" PRIx64 "\n", val);
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
static uint64_t port92_read(void *opaque, hwaddr addr,
unsigned size)
{
Port92State *s = opaque;
uint32_t ret;
ret = s->outport;
DPRINTF("port92: read 0x%02x\n", ret);
return ret;
}
static void port92_init(ISADevice *dev, qemu_irq a20_out)
{
qdev_connect_gpio_out_named(DEVICE(dev), PORT92_A20_LINE, 0, a20_out);
}
static const VMStateDescription vmstate_port92_isa = {
.name = "port92",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(outport, Port92State),
VMSTATE_END_OF_LIST()
}
};
static void port92_reset(DeviceState *d)
{
Port92State *s = PORT92(d);
s->outport &= ~1;
}
static const MemoryRegionOps port92_ops = {
.read = port92_read,
.write = port92_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void port92_initfn(Object *obj)
{
Port92State *s = PORT92(obj);
memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
s->outport = 0;
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
}
static void port92_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
Port92State *s = PORT92(dev);
isa_register_ioport(isadev, &s->io, 0x92);
}
static void port92_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = port92_realizefn;
dc->reset = port92_reset;
dc->vmsd = &vmstate_port92_isa;
/*
* Reason: unlike ordinary ISA devices, this one needs additional
* wiring: its A20 output line needs to be wired up by
* port92_init().
*/
dc->user_creatable = false;
}
static const TypeInfo port92_info = {
.name = TYPE_PORT92,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(Port92State),
.instance_init = port92_initfn,
.class_init = port92_class_initfn,
};
static void port92_register_types(void)
{
type_register_static(&port92_info);
}
type_init(port92_register_types)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
X86CPU *cpu = opaque;
/* XXX: send to all CPUs ? */
/* XXX: add logic to handle multiple A20 line sources */
x86_cpu_set_a20(cpu, level);
}
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
{
int index = le32_to_cpu(e820_reserve.count);
struct e820_entry *entry;
if (type != E820_RAM) {
/* old FW_CFG_E820_TABLE entry -- reservations only */
if (index >= E820_NR_ENTRIES) {
return -EBUSY;
}
entry = &e820_reserve.entry[index++];
entry->address = cpu_to_le64(address);
entry->length = cpu_to_le64(length);
entry->type = cpu_to_le32(type);
e820_reserve.count = cpu_to_le32(index);
}
/* new "etc/e820" file -- include ram too */
e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1);
e820_table[e820_entries].address = cpu_to_le64(address);
e820_table[e820_entries].length = cpu_to_le64(length);
e820_table[e820_entries].type = cpu_to_le32(type);
e820_entries++;
return e820_entries;
}
int e820_get_num_entries(void)
{
return e820_entries;
}
bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length)
{
if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) {
*address = le64_to_cpu(e820_table[idx].address);
*length = le64_to_cpu(e820_table[idx].length);
return true;
}
return false;
}
/* Calculates initial APIC ID for a specific CPU index
*
* Currently we need to be able to calculate the APIC ID from the CPU index
* alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
* no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
* all CPUs up to max_cpus.
*/
static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms,
unsigned int cpu_index)
{
MachineState *ms = MACHINE(pcms);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
uint32_t correct_id;
static bool warned;
correct_id = x86_apicid_from_cpu_idx(ms->smp.cores,
ms->smp.threads, cpu_index);
if (pcmc->compat_apic_id_mode) {
if (cpu_index != correct_id && !warned && !qtest_enabled()) {
error_report("APIC IDs set in compatibility mode, "
"CPU topology won't match the configuration");
warned = true;
}
return cpu_index;
} else {
return correct_id;
}
}
static void pc_build_smbios(PCMachineState *pcms)
{
uint8_t *smbios_tables, *smbios_anchor;
size_t smbios_tables_len, smbios_anchor_len;
struct smbios_phys_mem_area *mem_array;
unsigned i, array_count;
MachineState *ms = MACHINE(pcms);
X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu);
/* tell smbios about cpuid version and features */
smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]);
smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len);
if (smbios_tables) {
fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES,
smbios_tables, smbios_tables_len);
}
/* build the array of physical mem area from e820 table */
mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries());
for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) {
uint64_t addr, len;
if (e820_get_entry(i, E820_RAM, &addr, &len)) {
mem_array[array_count].address = addr;
mem_array[array_count].length = len;
array_count++;
}
}
smbios_get_tables(ms, mem_array, array_count,
&smbios_tables, &smbios_tables_len,
&smbios_anchor, &smbios_anchor_len);
g_free(mem_array);
if (smbios_anchor) {
fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables",
smbios_tables, smbios_tables_len);
fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor",
smbios_anchor, smbios_anchor_len);
}
}
static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms)
{
FWCfgState *fw_cfg;
uint64_t *numa_fw_cfg;
int i;
const CPUArchIdList *cpus;
MachineClass *mc = MACHINE_GET_CLASS(pcms);
fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus);
/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: