/
tcg-target.c.inc
3864 lines (3527 loc) · 118 KB
/
tcg-target.c.inc
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/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2008 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "elf.h"
#include "../tcg-pool.c.inc"
#if defined _CALL_DARWIN || defined __APPLE__
#define TCG_TARGET_CALL_DARWIN
#endif
#ifdef _CALL_SYSV
# define TCG_TARGET_CALL_ALIGN_ARGS 1
#endif
/* For some memory operations, we need a scratch that isn't R0. For the AIX
calling convention, we can re-use the TOC register since we'll be reloading
it at every call. Otherwise R12 will do nicely as neither a call-saved
register nor a parameter register. */
#ifdef _CALL_AIX
# define TCG_REG_TMP1 TCG_REG_R2
#else
# define TCG_REG_TMP1 TCG_REG_R12
#endif
#define TCG_VEC_TMP1 TCG_REG_V0
#define TCG_VEC_TMP2 TCG_REG_V1
#define TCG_REG_TB TCG_REG_R31
#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
#define SZP ((int)sizeof(void *))
/* Shorthand for size of a register. */
#define SZR (TCG_TARGET_REG_BITS / 8)
#define TCG_CT_CONST_S16 0x100
#define TCG_CT_CONST_U16 0x200
#define TCG_CT_CONST_S32 0x400
#define TCG_CT_CONST_U32 0x800
#define TCG_CT_CONST_ZERO 0x1000
#define TCG_CT_CONST_MONE 0x2000
#define TCG_CT_CONST_WSZ 0x4000
static tcg_insn_unit *tb_ret_addr;
TCGPowerISA have_isa;
static bool have_isel;
bool have_altivec;
bool have_vsx;
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG 30
#endif
#ifdef CONFIG_DEBUG_TCG
static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
};
#endif
static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R14, /* call saved registers */
TCG_REG_R15,
TCG_REG_R16,
TCG_REG_R17,
TCG_REG_R18,
TCG_REG_R19,
TCG_REG_R20,
TCG_REG_R21,
TCG_REG_R22,
TCG_REG_R23,
TCG_REG_R24,
TCG_REG_R25,
TCG_REG_R26,
TCG_REG_R27,
TCG_REG_R28,
TCG_REG_R29,
TCG_REG_R30,
TCG_REG_R31,
TCG_REG_R12, /* call clobbered, non-arguments */
TCG_REG_R11,
TCG_REG_R2,
TCG_REG_R13,
TCG_REG_R10, /* call clobbered, arguments */
TCG_REG_R9,
TCG_REG_R8,
TCG_REG_R7,
TCG_REG_R6,
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
/* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
TCG_REG_V2, /* call clobbered, vectors */
TCG_REG_V3,
TCG_REG_V4,
TCG_REG_V5,
TCG_REG_V6,
TCG_REG_V7,
TCG_REG_V8,
TCG_REG_V9,
TCG_REG_V10,
TCG_REG_V11,
TCG_REG_V12,
TCG_REG_V13,
TCG_REG_V14,
TCG_REG_V15,
TCG_REG_V16,
TCG_REG_V17,
TCG_REG_V18,
TCG_REG_V19,
};
static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
TCG_REG_R6,
TCG_REG_R7,
TCG_REG_R8,
TCG_REG_R9,
TCG_REG_R10
};
static const int tcg_target_call_oarg_regs[] = {
TCG_REG_R3,
TCG_REG_R4
};
static const int tcg_target_callee_save_regs[] = {
#ifdef TCG_TARGET_CALL_DARWIN
TCG_REG_R11,
#endif
TCG_REG_R14,
TCG_REG_R15,
TCG_REG_R16,
TCG_REG_R17,
TCG_REG_R18,
TCG_REG_R19,
TCG_REG_R20,
TCG_REG_R21,
TCG_REG_R22,
TCG_REG_R23,
TCG_REG_R24,
TCG_REG_R25,
TCG_REG_R26,
TCG_REG_R27, /* currently used for the global env */
TCG_REG_R28,
TCG_REG_R29,
TCG_REG_R30,
TCG_REG_R31
};
static inline bool in_range_b(tcg_target_long target)
{
return target == sextract64(target, 0, 26);
}
static uint32_t reloc_pc24_val(tcg_insn_unit *pc, const tcg_insn_unit *target)
{
ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
tcg_debug_assert(in_range_b(disp));
return disp & 0x3fffffc;
}
static bool reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
{
ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
if (in_range_b(disp)) {
*pc = (*pc & ~0x3fffffc) | (disp & 0x3fffffc);
return true;
}
return false;
}
static uint16_t reloc_pc14_val(tcg_insn_unit *pc, const tcg_insn_unit *target)
{
ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
tcg_debug_assert(disp == (int16_t) disp);
return disp & 0xfffc;
}
static bool reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
{
ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
if (disp == (int16_t) disp) {
*pc = (*pc & ~0xfffc) | (disp & 0xfffc);
return true;
}
return false;
}
/* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
{
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
ct->regs = 0xffffffff;
break;
case 'v':
ct->regs = 0xffffffff00000000ull;
break;
case 'L': /* qemu_ld constraint */
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
#endif
break;
case 'S': /* qemu_st constraint */
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
#endif
break;
case 'I':
ct->ct |= TCG_CT_CONST_S16;
break;
case 'J':
ct->ct |= TCG_CT_CONST_U16;
break;
case 'M':
ct->ct |= TCG_CT_CONST_MONE;
break;
case 'T':
ct->ct |= TCG_CT_CONST_S32;
break;
case 'U':
ct->ct |= TCG_CT_CONST_U32;
break;
case 'W':
ct->ct |= TCG_CT_CONST_WSZ;
break;
case 'Z':
ct->ct |= TCG_CT_CONST_ZERO;
break;
default:
return NULL;
}
return ct_str;
}
/* test if a constant matches the constraint */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
{
int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
/* The only 32-bit constraint we use aside from
TCG_CT_CONST is TCG_CT_CONST_S16. */
if (type == TCG_TYPE_I32) {
val = (int32_t)val;
}
if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
return 1;
} else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
return 1;
} else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
return 1;
} else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
return 1;
} else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
} else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
return 1;
} else if ((ct & TCG_CT_CONST_WSZ)
&& val == (type == TCG_TYPE_I32 ? 32 : 64)) {
return 1;
}
return 0;
}
#define OPCD(opc) ((opc)<<26)
#define XO19(opc) (OPCD(19)|((opc)<<1))
#define MD30(opc) (OPCD(30)|((opc)<<2))
#define MDS30(opc) (OPCD(30)|((opc)<<1))
#define XO31(opc) (OPCD(31)|((opc)<<1))
#define XO58(opc) (OPCD(58)|(opc))
#define XO62(opc) (OPCD(62)|(opc))
#define VX4(opc) (OPCD(4)|(opc))
#define B OPCD( 18)
#define BC OPCD( 16)
#define LBZ OPCD( 34)
#define LHZ OPCD( 40)
#define LHA OPCD( 42)
#define LWZ OPCD( 32)
#define LWZUX XO31( 55)
#define STB OPCD( 38)
#define STH OPCD( 44)
#define STW OPCD( 36)
#define STD XO62( 0)
#define STDU XO62( 1)
#define STDX XO31(149)
#define LD XO58( 0)
#define LDX XO31( 21)
#define LDU XO58( 1)
#define LDUX XO31( 53)
#define LWA XO58( 2)
#define LWAX XO31(341)
#define ADDIC OPCD( 12)
#define ADDI OPCD( 14)
#define ADDIS OPCD( 15)
#define ORI OPCD( 24)
#define ORIS OPCD( 25)
#define XORI OPCD( 26)
#define XORIS OPCD( 27)
#define ANDI OPCD( 28)
#define ANDIS OPCD( 29)
#define MULLI OPCD( 7)
#define CMPLI OPCD( 10)
#define CMPI OPCD( 11)
#define SUBFIC OPCD( 8)
#define LWZU OPCD( 33)
#define STWU OPCD( 37)
#define RLWIMI OPCD( 20)
#define RLWINM OPCD( 21)
#define RLWNM OPCD( 23)
#define RLDICL MD30( 0)
#define RLDICR MD30( 1)
#define RLDIMI MD30( 3)
#define RLDCL MDS30( 8)
#define BCLR XO19( 16)
#define BCCTR XO19(528)
#define CRAND XO19(257)
#define CRANDC XO19(129)
#define CRNAND XO19(225)
#define CROR XO19(449)
#define CRNOR XO19( 33)
#define EXTSB XO31(954)
#define EXTSH XO31(922)
#define EXTSW XO31(986)
#define ADD XO31(266)
#define ADDE XO31(138)
#define ADDME XO31(234)
#define ADDZE XO31(202)
#define ADDC XO31( 10)
#define AND XO31( 28)
#define SUBF XO31( 40)
#define SUBFC XO31( 8)
#define SUBFE XO31(136)
#define SUBFME XO31(232)
#define SUBFZE XO31(200)
#define OR XO31(444)
#define XOR XO31(316)
#define MULLW XO31(235)
#define MULHW XO31( 75)
#define MULHWU XO31( 11)
#define DIVW XO31(491)
#define DIVWU XO31(459)
#define CMP XO31( 0)
#define CMPL XO31( 32)
#define LHBRX XO31(790)
#define LWBRX XO31(534)
#define LDBRX XO31(532)
#define STHBRX XO31(918)
#define STWBRX XO31(662)
#define STDBRX XO31(660)
#define MFSPR XO31(339)
#define MTSPR XO31(467)
#define SRAWI XO31(824)
#define NEG XO31(104)
#define MFCR XO31( 19)
#define MFOCRF (MFCR | (1u << 20))
#define NOR XO31(124)
#define CNTLZW XO31( 26)
#define CNTLZD XO31( 58)
#define CNTTZW XO31(538)
#define CNTTZD XO31(570)
#define CNTPOPW XO31(378)
#define CNTPOPD XO31(506)
#define ANDC XO31( 60)
#define ORC XO31(412)
#define EQV XO31(284)
#define NAND XO31(476)
#define ISEL XO31( 15)
#define MULLD XO31(233)
#define MULHD XO31( 73)
#define MULHDU XO31( 9)
#define DIVD XO31(489)
#define DIVDU XO31(457)
#define LBZX XO31( 87)
#define LHZX XO31(279)
#define LHAX XO31(343)
#define LWZX XO31( 23)
#define STBX XO31(215)
#define STHX XO31(407)
#define STWX XO31(151)
#define EIEIO XO31(854)
#define HWSYNC XO31(598)
#define LWSYNC (HWSYNC | (1u << 21))
#define SPR(a, b) ((((a)<<5)|(b))<<11)
#define LR SPR(8, 0)
#define CTR SPR(9, 0)
#define SLW XO31( 24)
#define SRW XO31(536)
#define SRAW XO31(792)
#define SLD XO31( 27)
#define SRD XO31(539)
#define SRAD XO31(794)
#define SRADI XO31(413<<1)
#define TW XO31( 4)
#define TRAP (TW | TO(31))
#define NOP ORI /* ori 0,0,0 */
#define LVX XO31(103)
#define LVEBX XO31(7)
#define LVEHX XO31(39)
#define LVEWX XO31(71)
#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */
#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */
#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */
#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */
#define LXSD (OPCD(57) | 2) /* v3.00 */
#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */
#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */
#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */
#define STXSD (OPCD(61) | 2) /* v3.00 */
#define VADDSBS VX4(768)
#define VADDUBS VX4(512)
#define VADDUBM VX4(0)
#define VADDSHS VX4(832)
#define VADDUHS VX4(576)
#define VADDUHM VX4(64)
#define VADDSWS VX4(896)
#define VADDUWS VX4(640)
#define VADDUWM VX4(128)
#define VADDUDM VX4(192) /* v2.07 */
#define VSUBSBS VX4(1792)
#define VSUBUBS VX4(1536)
#define VSUBUBM VX4(1024)
#define VSUBSHS VX4(1856)
#define VSUBUHS VX4(1600)
#define VSUBUHM VX4(1088)
#define VSUBSWS VX4(1920)
#define VSUBUWS VX4(1664)
#define VSUBUWM VX4(1152)
#define VSUBUDM VX4(1216) /* v2.07 */
#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
#define VMAXSD VX4(450) /* v2.07 */
#define VMAXUB VX4(2)
#define VMAXUH VX4(66)
#define VMAXUW VX4(130)
#define VMAXUD VX4(194) /* v2.07 */
#define VMINSB VX4(770)
#define VMINSH VX4(834)
#define VMINSW VX4(898)
#define VMINSD VX4(962) /* v2.07 */
#define VMINUB VX4(514)
#define VMINUH VX4(578)
#define VMINUW VX4(642)
#define VMINUD VX4(706) /* v2.07 */
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
#define VCMPEQUD VX4(199) /* v2.07 */
#define VCMPGTSB VX4(774)
#define VCMPGTSH VX4(838)
#define VCMPGTSW VX4(902)
#define VCMPGTSD VX4(967) /* v2.07 */
#define VCMPGTUB VX4(518)
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
#define VCMPGTUD VX4(711) /* v2.07 */
#define VCMPNEB VX4(7) /* v3.00 */
#define VCMPNEH VX4(71) /* v3.00 */
#define VCMPNEW VX4(135) /* v3.00 */
#define VSLB VX4(260)
#define VSLH VX4(324)
#define VSLW VX4(388)
#define VSLD VX4(1476) /* v2.07 */
#define VSRB VX4(516)
#define VSRH VX4(580)
#define VSRW VX4(644)
#define VSRD VX4(1732) /* v2.07 */
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
#define VSRAD VX4(964) /* v2.07 */
#define VRLB VX4(4)
#define VRLH VX4(68)
#define VRLW VX4(132)
#define VRLD VX4(196) /* v2.07 */
#define VMULEUB VX4(520)
#define VMULEUH VX4(584)
#define VMULEUW VX4(648) /* v2.07 */
#define VMULOUB VX4(8)
#define VMULOUH VX4(72)
#define VMULOUW VX4(136) /* v2.07 */
#define VMULUWM VX4(137) /* v2.07 */
#define VMULLD VX4(457) /* v3.10 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
#define VMRGHH VX4(76)
#define VMRGHW VX4(140)
#define VMRGLB VX4(268)
#define VMRGLH VX4(332)
#define VMRGLW VX4(396)
#define VPKUHUM VX4(14)
#define VPKUWUM VX4(78)
#define VAND VX4(1028)
#define VANDC VX4(1092)
#define VNOR VX4(1284)
#define VOR VX4(1156)
#define VXOR VX4(1220)
#define VEQV VX4(1668) /* v2.07 */
#define VNAND VX4(1412) /* v2.07 */
#define VORC VX4(1348) /* v2.07 */
#define VSPLTB VX4(524)
#define VSPLTH VX4(588)
#define VSPLTW VX4(652)
#define VSPLTISB VX4(780)
#define VSPLTISH VX4(844)
#define VSPLTISW VX4(908)
#define VSLDOI VX4(44)
#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */
#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */
#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */
#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */
#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */
#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */
#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */
#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */
#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
#define RB(r) ((r)<<11)
#define TO(t) ((t)<<21)
#define SH(s) ((s)<<11)
#define MB(b) ((b)<<6)
#define ME(e) ((e)<<1)
#define BO(o) ((o)<<21)
#define MB64(b) ((b)<<5)
#define FXM(b) (1 << (19 - (b)))
#define VRT(r) (((r) & 31) << 21)
#define VRA(r) (((r) & 31) << 16)
#define VRB(r) (((r) & 31) << 11)
#define VRC(r) (((r) & 31) << 6)
#define LK 1
#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
#define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
#define BF(n) ((n)<<23)
#define BI(n, c) (((c)+((n)*4))<<16)
#define BT(n, c) (((c)+((n)*4))<<21)
#define BA(n, c) (((c)+((n)*4))<<16)
#define BB(n, c) (((c)+((n)*4))<<11)
#define BC_(n, c) (((c)+((n)*4))<<6)
#define BO_COND_TRUE BO(12)
#define BO_COND_FALSE BO( 4)
#define BO_ALWAYS BO(20)
enum {
CR_LT,
CR_GT,
CR_EQ,
CR_SO
};
static const uint32_t tcg_to_bc[] = {
[TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
[TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
[TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
[TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
[TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
[TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
[TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
[TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
[TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
[TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
};
/* The low bit here is set if the RA and RB fields must be inverted. */
static const uint32_t tcg_to_isel[] = {
[TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
[TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
[TCG_COND_LT] = ISEL | BC_(7, CR_LT),
[TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
[TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
[TCG_COND_GT] = ISEL | BC_(7, CR_GT),
[TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
[TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
[TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
[TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
};
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
tcg_insn_unit *target;
int16_t lo;
int32_t hi;
value += addend;
target = (tcg_insn_unit *)value;
switch (type) {
case R_PPC_REL14:
return reloc_pc14(code_ptr, target);
case R_PPC_REL24:
return reloc_pc24(code_ptr, target);
case R_PPC_ADDR16:
/*
* We are (slightly) abusing this relocation type. In particular,
* assert that the low 2 bits are zero, and do not modify them.
* That way we can use this with LD et al that have opcode bits
* in the low 2 bits of the insn.
*/
if ((value & 3) || value != (int16_t)value) {
return false;
}
*code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
break;
case R_PPC_ADDR32:
/*
* We are abusing this relocation type. Again, this points to
* a pair of insns, lis + load. This is an absolute address
* relocation for PPC32 so the lis cannot be removed.
*/
lo = value;
hi = value - lo;
if (hi + lo != value) {
return false;
}
code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
break;
default:
g_assert_not_reached();
}
return true;
}
static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
TCGReg base, tcg_target_long offset);
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (ret == arg) {
return true;
}
switch (type) {
case TCG_TYPE_I64:
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
/* fallthru */
case TCG_TYPE_I32:
if (ret < TCG_REG_V0) {
if (arg < TCG_REG_V0) {
tcg_out32(s, OR | SAB(arg, ret, arg));
break;
} else if (have_isa_2_07) {
tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
| VRT(arg) | RA(ret));
break;
} else {
/* Altivec does not support vector->integer moves. */
return false;
}
} else if (arg < TCG_REG_V0) {
if (have_isa_2_07) {
tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
| VRT(ret) | RA(arg));
break;
} else {
/* Altivec does not support integer->vector moves. */
return false;
}
}
/* fallthru */
case TCG_TYPE_V64:
case TCG_TYPE_V128:
tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0);
tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
break;
default:
g_assert_not_reached();
}
return true;
}
static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
int sh, int mb)
{
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
}
static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
int sh, int mb, int me)
{
tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
}
static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
{
tcg_out_rld(s, RLDICL, dst, src, 0, 32);
}
static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
}
static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
}
static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
}
static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
{
tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
}
/* Emit a move into ret of arg, if it can be done in one insn. */
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
{
if (arg == (int16_t)arg) {
tcg_out32(s, ADDI | TAI(ret, 0, arg));
return true;
}
if (arg == (int32_t)arg && (arg & 0xffff) == 0) {
tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
return true;
}
return false;
}
static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long arg, bool in_prologue)
{
intptr_t tb_diff;
tcg_target_long tmp;
int shift;
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
/* Load 16-bit immediates with one insn. */
if (tcg_out_movi_one(s, ret, arg)) {
return;
}
/* Load addresses within the TB with one insn. */
tb_diff = tcg_tbrel_diff(s, (void *)arg);
if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) {
tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff));
return;
}
/* Load 32-bit immediates with two insns. Note that we've already
eliminated bare ADDIS, so we know both insns are required. */
if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
tcg_out32(s, ORI | SAI(ret, ret, arg));
return;
}
if (arg == (uint32_t)arg && !(arg & 0x8000)) {
tcg_out32(s, ADDI | TAI(ret, 0, arg));
tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
return;
}
/* Load masked 16-bit value. */
if (arg > 0 && (arg & 0x8000)) {
tmp = arg | 0x7fff;
if ((tmp & (tmp + 1)) == 0) {
int mb = clz64(tmp + 1) + 1;
tcg_out32(s, ADDI | TAI(ret, 0, arg));
tcg_out_rld(s, RLDICL, ret, ret, 0, mb);
return;
}
}
/* Load common masks with 2 insns. */
shift = ctz64(arg);
tmp = arg >> shift;
if (tmp == (int16_t)tmp) {
tcg_out32(s, ADDI | TAI(ret, 0, tmp));
tcg_out_shli64(s, ret, ret, shift);
return;
}
shift = clz64(arg);
if (tcg_out_movi_one(s, ret, arg << shift)) {
tcg_out_shri64(s, ret, ret, shift);
return;
}
/* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */
if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) {
tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff);
return;
}
/* Use the constant pool, if possible. */
if (!in_prologue && USE_REG_TB) {
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
tcg_tbrel_diff(s, NULL));
tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
return;
}
tmp = arg >> 31 >> 1;
tcg_out_movi(s, TCG_TYPE_I32, ret, tmp);
if (tmp) {
tcg_out_shli64(s, ret, ret, 32);
}
if (arg & 0xffff0000) {
tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
}
if (arg & 0xffff) {
tcg_out32(s, ORI | SAI(ret, ret, arg));
}
}
static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long val)
{
uint32_t load_insn;
int rel, low;
intptr_t add;
low = (int8_t)val;
if (low >= -16 && low < 16) {
if (val == (tcg_target_long)dup_const(MO_8, low)) {
tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
return;
}
if (val == (tcg_target_long)dup_const(MO_16, low)) {
tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
return;
}
if (val == (tcg_target_long)dup_const(MO_32, low)) {
tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
return;
}
}
if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
return;
}
/*
* Otherwise we must load the value from the constant pool.
*/
if (USE_REG_TB) {
rel = R_PPC_ADDR16;
add = tcg_tbrel_diff(s, NULL);
} else {
rel = R_PPC_ADDR32;
add = 0;
}
if (have_vsx) {
load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
if (TCG_TARGET_REG_BITS == 64) {
new_pool_label(s, val, rel, s->code_ptr, add);
} else {
new_pool_l2(s, rel, s->code_ptr, add, val, val);
}
} else {
load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
if (TCG_TARGET_REG_BITS == 64) {
new_pool_l2(s, rel, s->code_ptr, add, val, val);
} else {
new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
}
}
if (USE_REG_TB) {
tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
load_insn |= RA(TCG_REG_TB);
} else {
tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
}
tcg_out32(s, load_insn);
}
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long arg)
{
switch (type) {
case TCG_TYPE_I32:
case TCG_TYPE_I64:
tcg_debug_assert(ret < TCG_REG_V0);
tcg_out_movi_int(s, type, ret, arg, false);
break;
case TCG_TYPE_V64:
case TCG_TYPE_V128:
tcg_debug_assert(ret >= TCG_REG_V0);
tcg_out_dupi_vec(s, type, ret, arg);
break;
default:
g_assert_not_reached();
}
}
static bool mask_operand(uint32_t c, int *mb, int *me)
{
uint32_t lsb, test;