/
translate.c
2389 lines (2260 loc) · 77.1 KB
/
translate.c
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/*
* SH4 translation
*
* Copyright (c) 2005 Samuel Tardieu
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#define DEBUG_DISAS
#include "qemu/osdep.h"
#include "cpu.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "trace-tcg.h"
#include "exec/log.h"
typedef struct DisasContext {
struct TranslationBlock *tb;
target_ulong pc;
uint16_t opcode;
uint32_t tbflags; /* should stay unmodified during the TB translation */
uint32_t envflags; /* should stay in sync with env->flags using TCG ops */
DisasJumpType bstate;
int memidx;
int gbank;
int fbank;
uint32_t delayed_pc;
int singlestep_enabled;
uint32_t features;
int has_movcal;
} DisasContext;
#if defined(CONFIG_USER_ONLY)
#define IS_USER(ctx) 1
#else
#define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
#endif
/* Target-specific values for ctx->bstate. */
/* We want to exit back to the cpu loop for some reason.
Usually this is to recognize interrupts immediately. */
#define DISAS_STOP DISAS_TARGET_0
/* global register indexes */
static TCGv cpu_gregs[32];
static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;
static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
static TCGv cpu_lock_addr, cpu_lock_value;
static TCGv cpu_fregs[32];
/* internal register indexes */
static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond;
#include "exec/gen-icount.h"
void sh4_translate_init(void)
{
int i;
static const char * const gregnames[24] = {
"R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
"R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
"R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
};
static const char * const fregnames[32] = {
"FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0",
"FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0",
"FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0",
"FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0",
"FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1",
"FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1",
"FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1",
"FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1",
};
for (i = 0; i < 24; i++) {
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, gregs[i]),
gregnames[i]);
}
memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv));
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, pc), "PC");
cpu_sr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, sr), "SR");
cpu_sr_m = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, sr_m), "SR_M");
cpu_sr_q = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, sr_q), "SR_Q");
cpu_sr_t = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, sr_t), "SR_T");
cpu_ssr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, ssr), "SSR");
cpu_spc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, spc), "SPC");
cpu_gbr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, gbr), "GBR");
cpu_vbr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, vbr), "VBR");
cpu_sgr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, sgr), "SGR");
cpu_dbr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, dbr), "DBR");
cpu_mach = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, mach), "MACH");
cpu_macl = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, macl), "MACL");
cpu_pr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, pr), "PR");
cpu_fpscr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, fpscr), "FPSCR");
cpu_fpul = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, fpul), "FPUL");
cpu_flags = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, flags), "_flags_");
cpu_delayed_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, delayed_pc),
"_delayed_pc_");
cpu_delayed_cond = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State,
delayed_cond),
"_delayed_cond_");
cpu_lock_addr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, lock_addr),
"_lock_addr_");
cpu_lock_value = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, lock_value),
"_lock_value_");
for (i = 0; i < 32; i++)
cpu_fregs[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUSH4State, fregs[i]),
fregnames[i]);
}
void superh_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
int i;
cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
env->pc, cpu_read_sr(env), env->pr, env->fpscr);
cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
env->spc, env->ssr, env->gbr, env->vbr);
cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
env->sgr, env->dbr, env->delayed_pc, env->fpul);
for (i = 0; i < 24; i += 4) {
cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
i, env->gregs[i], i + 1, env->gregs[i + 1],
i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
}
if (env->flags & DELAY_SLOT) {
cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
env->delayed_pc);
} else if (env->flags & DELAY_SLOT_CONDITIONAL) {
cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
env->delayed_pc);
} else if (env->flags & DELAY_SLOT_RTE) {
cpu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n",
env->delayed_pc);
}
}
static void gen_read_sr(TCGv dst)
{
TCGv t0 = tcg_temp_new();
tcg_gen_shli_i32(t0, cpu_sr_q, SR_Q);
tcg_gen_or_i32(dst, dst, t0);
tcg_gen_shli_i32(t0, cpu_sr_m, SR_M);
tcg_gen_or_i32(dst, dst, t0);
tcg_gen_shli_i32(t0, cpu_sr_t, SR_T);
tcg_gen_or_i32(dst, cpu_sr, t0);
tcg_temp_free_i32(t0);
}
static void gen_write_sr(TCGv src)
{
tcg_gen_andi_i32(cpu_sr, src,
~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T)));
tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1);
tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1);
tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1);
}
static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
{
if (save_pc) {
tcg_gen_movi_i32(cpu_pc, ctx->pc);
}
if (ctx->delayed_pc != (uint32_t) -1) {
tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc);
}
if ((ctx->tbflags & TB_FLAG_ENVFLAGS_MASK) != ctx->envflags) {
tcg_gen_movi_i32(cpu_flags, ctx->envflags);
}
}
static inline bool use_exit_tb(DisasContext *ctx)
{
return (ctx->tbflags & GUSA_EXCLUSIVE) != 0;
}
static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
{
/* Use a direct jump if in same page and singlestep not enabled */
if (unlikely(ctx->singlestep_enabled || use_exit_tb(ctx))) {
return false;
}
#ifndef CONFIG_USER_ONLY
return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
}
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
if (use_goto_tb(ctx, dest)) {
tcg_gen_goto_tb(n);
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
if (ctx->singlestep_enabled) {
gen_helper_debug(cpu_env);
} else if (use_exit_tb(ctx)) {
tcg_gen_exit_tb(0);
} else {
tcg_gen_lookup_and_goto_ptr();
}
}
ctx->bstate = DISAS_NORETURN;
}
static void gen_jump(DisasContext * ctx)
{
if (ctx->delayed_pc == -1) {
/* Target is not statically known, it comes necessarily from a
delayed jump as immediate jump are conditinal jumps */
tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
tcg_gen_discard_i32(cpu_delayed_pc);
if (ctx->singlestep_enabled) {
gen_helper_debug(cpu_env);
} else if (use_exit_tb(ctx)) {
tcg_gen_exit_tb(0);
} else {
tcg_gen_lookup_and_goto_ptr();
}
ctx->bstate = DISAS_NORETURN;
} else {
gen_goto_tb(ctx, 0, ctx->delayed_pc);
}
}
/* Immediate conditional jump (bt or bf) */
static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
bool jump_if_true)
{
TCGLabel *l1 = gen_new_label();
TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE;
if (ctx->tbflags & GUSA_EXCLUSIVE) {
/* When in an exclusive region, we must continue to the end.
Therefore, exit the region on a taken branch, but otherwise
fall through to the next instruction. */
tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);
tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
/* Note that this won't actually use a goto_tb opcode because we
disallow it in use_goto_tb, but it handles exit + singlestep. */
gen_goto_tb(ctx, 0, dest);
gen_set_label(l1);
return;
}
gen_save_cpu_state(ctx, false);
tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);
gen_goto_tb(ctx, 0, dest);
gen_set_label(l1);
gen_goto_tb(ctx, 1, ctx->pc + 2);
ctx->bstate = DISAS_NORETURN;
}
/* Delayed conditional jump (bt or bf) */
static void gen_delayed_conditional_jump(DisasContext * ctx)
{
TCGLabel *l1 = gen_new_label();
TCGv ds = tcg_temp_new();
tcg_gen_mov_i32(ds, cpu_delayed_cond);
tcg_gen_discard_i32(cpu_delayed_cond);
if (ctx->tbflags & GUSA_EXCLUSIVE) {
/* When in an exclusive region, we must continue to the end.
Therefore, exit the region on a taken branch, but otherwise
fall through to the next instruction. */
tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1);
/* Leave the gUSA region. */
tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
gen_jump(ctx);
gen_set_label(l1);
ctx->bstate = DISAS_NEXT;
return;
}
tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
gen_goto_tb(ctx, 1, ctx->pc + 2);
gen_set_label(l1);
gen_jump(ctx);
}
static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
/* We have already signaled illegal instruction for odd Dr. */
tcg_debug_assert((reg & 1) == 0);
reg ^= ctx->fbank;
tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
}
static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
/* We have already signaled illegal instruction for odd Dr. */
tcg_debug_assert((reg & 1) == 0);
reg ^= ctx->fbank;
tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
}
#define B3_0 (ctx->opcode & 0xf)
#define B6_4 ((ctx->opcode >> 4) & 0x7)
#define B7_4 ((ctx->opcode >> 4) & 0xf)
#define B7_0 (ctx->opcode & 0xff)
#define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
#define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
(ctx->opcode & 0xfff))
#define B11_8 ((ctx->opcode >> 8) & 0xf)
#define B15_12 ((ctx->opcode >> 12) & 0xf)
#define REG(x) cpu_gregs[(x) ^ ctx->gbank]
#define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
#define FREG(x) cpu_fregs[(x) ^ ctx->fbank]
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
#define CHECK_NOT_DELAY_SLOT \
if (ctx->envflags & DELAY_SLOT_MASK) { \
goto do_illegal_slot; \
}
#define CHECK_PRIVILEGED \
if (IS_USER(ctx)) { \
goto do_illegal; \
}
#define CHECK_FPU_ENABLED \
if (ctx->tbflags & (1u << SR_FD)) { \
goto do_fpu_disabled; \
}
#define CHECK_FPSCR_PR_0 \
if (ctx->tbflags & FPSCR_PR) { \
goto do_illegal; \
}
#define CHECK_FPSCR_PR_1 \
if (!(ctx->tbflags & FPSCR_PR)) { \
goto do_illegal; \
}
#define CHECK_SH4A \
if (!(ctx->features & SH_FEATURE_SH4A)) { \
goto do_illegal; \
}
static void _decode_opc(DisasContext * ctx)
{
/* This code tries to make movcal emulation sufficiently
accurate for Linux purposes. This instruction writes
memory, and prior to that, always allocates a cache line.
It is used in two contexts:
- in memcpy, where data is copied in blocks, the first write
of to a block uses movca.l for performance.
- in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
to flush the cache. Here, the data written by movcal.l is never
written to memory, and the data written is just bogus.
To simulate this, we simulate movcal.l, we store the value to memory,
but we also remember the previous content. If we see ocbi, we check
if movcal.l for that address was done previously. If so, the write should
not have hit the memory, so we restore the previous content.
When we see an instruction that is neither movca.l
nor ocbi, the previous content is discarded.
To optimize, we only try to flush stores when we're at the start of
TB, or if we already saw movca.l in this TB and did not flush stores
yet. */
if (ctx->has_movcal)
{
int opcode = ctx->opcode & 0xf0ff;
if (opcode != 0x0093 /* ocbi */
&& opcode != 0x00c3 /* movca.l */)
{
gen_helper_discard_movcal_backup(cpu_env);
ctx->has_movcal = 0;
}
}
#if 0
fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
#endif
switch (ctx->opcode) {
case 0x0019: /* div0u */
tcg_gen_movi_i32(cpu_sr_m, 0);
tcg_gen_movi_i32(cpu_sr_q, 0);
tcg_gen_movi_i32(cpu_sr_t, 0);
return;
case 0x000b: /* rts */
CHECK_NOT_DELAY_SLOT
tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
ctx->envflags |= DELAY_SLOT;
ctx->delayed_pc = (uint32_t) - 1;
return;
case 0x0028: /* clrmac */
tcg_gen_movi_i32(cpu_mach, 0);
tcg_gen_movi_i32(cpu_macl, 0);
return;
case 0x0048: /* clrs */
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S));
return;
case 0x0008: /* clrt */
tcg_gen_movi_i32(cpu_sr_t, 0);
return;
case 0x0038: /* ldtlb */
CHECK_PRIVILEGED
gen_helper_ldtlb(cpu_env);
return;
case 0x002b: /* rte */
CHECK_PRIVILEGED
CHECK_NOT_DELAY_SLOT
gen_write_sr(cpu_ssr);
tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
ctx->envflags |= DELAY_SLOT_RTE;
ctx->delayed_pc = (uint32_t) - 1;
ctx->bstate = DISAS_STOP;
return;
case 0x0058: /* sets */
tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));
return;
case 0x0018: /* sett */
tcg_gen_movi_i32(cpu_sr_t, 1);
return;
case 0xfbfd: /* frchg */
CHECK_FPSCR_PR_0
tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
ctx->bstate = DISAS_STOP;
return;
case 0xf3fd: /* fschg */
CHECK_FPSCR_PR_0
tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
ctx->bstate = DISAS_STOP;
return;
case 0xf7fd: /* fpchg */
CHECK_SH4A
tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_PR);
ctx->bstate = DISAS_STOP;
return;
case 0x0009: /* nop */
return;
case 0x001b: /* sleep */
CHECK_PRIVILEGED
tcg_gen_movi_i32(cpu_pc, ctx->pc + 2);
gen_helper_sleep(cpu_env);
return;
}
switch (ctx->opcode & 0xf000) {
case 0x1000: /* mov.l Rm,@(disp,Rn) */
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
tcg_temp_free(addr);
}
return;
case 0x5000: /* mov.l @(disp,Rm),Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
tcg_temp_free(addr);
}
return;
case 0xe000: /* mov #imm,Rn */
#ifdef CONFIG_USER_ONLY
/* Detect the start of a gUSA region. If so, update envflags
and end the TB. This will allow us to see the end of the
region (stored in R0) in the next TB. */
if (B11_8 == 15 && B7_0s < 0 && (tb_cflags(ctx->tb) & CF_PARALLEL)) {
ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
ctx->bstate = DISAS_STOP;
}
#endif
tcg_gen_movi_i32(REG(B11_8), B7_0s);
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
tcg_temp_free(addr);
}
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3);
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
tcg_temp_free(addr);
}
return;
case 0x7000: /* add #imm,Rn */
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s);
return;
case 0xa000: /* bra disp */
CHECK_NOT_DELAY_SLOT
ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
ctx->envflags |= DELAY_SLOT;
return;
case 0xb000: /* bsr disp */
CHECK_NOT_DELAY_SLOT
tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2;
ctx->envflags |= DELAY_SLOT;
return;
}
switch (ctx->opcode & 0xf00f) {
case 0x6003: /* mov Rm,Rn */
tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
return;
case 0x2000: /* mov.b Rm,@Rn */
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
return;
case 0x2001: /* mov.w Rm,@Rn */
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
return;
case 0x2002: /* mov.l Rm,@Rn */
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
return;
case 0x6000: /* mov.b @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
return;
case 0x6001: /* mov.w @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
return;
case 0x6002: /* mov.l @Rm,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
return;
case 0x2004: /* mov.b Rm,@-Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 1);
/* might cause re-execution */
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB);
tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
tcg_temp_free(addr);
}
return;
case 0x2005: /* mov.w Rm,@-Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
return;
case 0x2006: /* mov.l Rm,@-Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
return;
case 0x6004: /* mov.b @Rm+,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
return;
case 0x6005: /* mov.w @Rm+,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
case 0x6006: /* mov.l @Rm+,Rn */
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
return;
case 0x0004: /* mov.b Rm,@(R0,Rn) */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB);
tcg_temp_free(addr);
}
return;
case 0x0005: /* mov.w Rm,@(R0,Rn) */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
tcg_temp_free(addr);
}
return;
case 0x0006: /* mov.l Rm,@(R0,Rn) */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B11_8), REG(0));
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
tcg_temp_free(addr);
}
return;
case 0x000c: /* mov.b @(R0,Rm),Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB);
tcg_temp_free(addr);
}
return;
case 0x000d: /* mov.w @(R0,Rm),Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
tcg_temp_free(addr);
}
return;
case 0x000e: /* mov.l @(R0,Rm),Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_add_i32(addr, REG(B7_4), REG(0));
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
tcg_temp_free(addr);
}
return;
case 0x6008: /* swap.b Rm,Rn */
{
TCGv low = tcg_temp_new();
tcg_gen_ext16u_i32(low, REG(B7_4));
tcg_gen_bswap16_i32(low, low);
tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16);
tcg_temp_free(low);
}
return;
case 0x6009: /* swap.w Rm,Rn */
tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16);
return;
case 0x200d: /* xtrct Rm,Rn */
{
TCGv high, low;
high = tcg_temp_new();
tcg_gen_shli_i32(high, REG(B7_4), 16);
low = tcg_temp_new();
tcg_gen_shri_i32(low, REG(B11_8), 16);
tcg_gen_or_i32(REG(B11_8), high, low);
tcg_temp_free(low);
tcg_temp_free(high);
}
return;
case 0x300c: /* add Rm,Rn */
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300e: /* addc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
REG(B11_8), t0, t1, cpu_sr_t);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
return;
case 0x300f: /* addv Rm,Rn */
{
TCGv t0, t1, t2;
t0 = tcg_temp_new();
tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
t1 = tcg_temp_new();
tcg_gen_xor_i32(t1, t0, REG(B11_8));
t2 = tcg_temp_new();
tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
tcg_gen_andc_i32(cpu_sr_t, t1, t2);
tcg_temp_free(t2);
tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
tcg_temp_free(t1);
tcg_gen_mov_i32(REG(B7_4), t0);
tcg_temp_free(t0);
}
return;
case 0x2009: /* and Rm,Rn */
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x3000: /* cmp/eq Rm,Rn */
tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4));
return;
case 0x3003: /* cmp/ge Rm,Rn */
tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4));
return;
case 0x3007: /* cmp/gt Rm,Rn */
tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4));
return;
case 0x3006: /* cmp/hi Rm,Rn */
tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4));
return;
case 0x3002: /* cmp/hs Rm,Rn */
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4));
return;
case 0x200c: /* cmp/str Rm,Rn */
{
TCGv cmp1 = tcg_temp_new();
TCGv cmp2 = tcg_temp_new();
tcg_gen_xor_i32(cmp2, REG(B7_4), REG(B11_8));
tcg_gen_subi_i32(cmp1, cmp2, 0x01010101);
tcg_gen_andc_i32(cmp1, cmp1, cmp2);
tcg_gen_andi_i32(cmp1, cmp1, 0x80808080);
tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0);
tcg_temp_free(cmp2);
tcg_temp_free(cmp1);
}
return;
case 0x2007: /* div0s Rm,Rn */
tcg_gen_shri_i32(cpu_sr_q, REG(B11_8), 31); /* SR_Q */
tcg_gen_shri_i32(cpu_sr_m, REG(B7_4), 31); /* SR_M */
tcg_gen_xor_i32(cpu_sr_t, cpu_sr_q, cpu_sr_m); /* SR_T */
return;
case 0x3004: /* div1 Rm,Rn */
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
TCGv zero = tcg_const_i32(0);
/* shift left arg1, saving the bit being pushed out and inserting
T on the right */
tcg_gen_shri_i32(t0, REG(B11_8), 31);
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
tcg_gen_or_i32(REG(B11_8), REG(B11_8), cpu_sr_t);
/* Add or subtract arg0 from arg1 depending if Q == M. To avoid
using 64-bit temps, we compute arg0's high part from q ^ m, so
that it is 0x00000000 when adding the value or 0xffffffff when
subtracting it. */
tcg_gen_xor_i32(t1, cpu_sr_q, cpu_sr_m);
tcg_gen_subi_i32(t1, t1, 1);
tcg_gen_neg_i32(t2, REG(B7_4));
tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2);
tcg_gen_add2_i32(REG(B11_8), t1, REG(B11_8), zero, t2, t1);
/* compute T and Q depending on carry */
tcg_gen_andi_i32(t1, t1, 1);
tcg_gen_xor_i32(t1, t1, t0);
tcg_gen_xori_i32(cpu_sr_t, t1, 1);
tcg_gen_xor_i32(cpu_sr_q, cpu_sr_m, t1);
tcg_temp_free(zero);
tcg_temp_free(t2);
tcg_temp_free(t1);
tcg_temp_free(t0);
}
return;
case 0x300d: /* dmuls.l Rm,Rn */
tcg_gen_muls2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8));
return;
case 0x3005: /* dmulu.l Rm,Rn */
tcg_gen_mulu2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8));
return;
case 0x600e: /* exts.b Rm,Rn */
tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4));
return;
case 0x600f: /* exts.w Rm,Rn */
tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4));
return;
case 0x600c: /* extu.b Rm,Rn */
tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4));
return;
case 0x600d: /* extu.w Rm,Rn */
tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4));
return;
case 0x000f: /* mac.l @Rm+,@Rn+ */
{
TCGv arg0, arg1;
arg0 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
gen_helper_macl(cpu_env, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
}
return;
case 0x400f: /* mac.w @Rm+,@Rn+ */
{
TCGv arg0, arg1;
arg0 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
arg1 = tcg_temp_new();
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
gen_helper_macw(cpu_env, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
}
return;
case 0x0007: /* mul.l Rm,Rn */
tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8));
return;
case 0x200f: /* muls.w Rm,Rn */
{
TCGv arg0, arg1;
arg0 = tcg_temp_new();
tcg_gen_ext16s_i32(arg0, REG(B7_4));
arg1 = tcg_temp_new();
tcg_gen_ext16s_i32(arg1, REG(B11_8));
tcg_gen_mul_i32(cpu_macl, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
}
return;
case 0x200e: /* mulu.w Rm,Rn */
{
TCGv arg0, arg1;
arg0 = tcg_temp_new();
tcg_gen_ext16u_i32(arg0, REG(B7_4));
arg1 = tcg_temp_new();
tcg_gen_ext16u_i32(arg1, REG(B11_8));
tcg_gen_mul_i32(cpu_macl, arg0, arg1);
tcg_temp_free(arg1);
tcg_temp_free(arg0);
}
return;
case 0x600b: /* neg Rm,Rn */
tcg_gen_neg_i32(REG(B11_8), REG(B7_4));
return;
case 0x600a: /* negc Rm,Rn */
{
TCGv t0 = tcg_const_i32(0);
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
REG(B7_4), t0, cpu_sr_t, t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
t0, t0, REG(B11_8), cpu_sr_t);
tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
tcg_temp_free(t0);
}
return;
case 0x6007: /* not Rm,Rn */
tcg_gen_not_i32(REG(B11_8), REG(B7_4));
return;
case 0x200b: /* or Rm,Rn */
tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x400c: /* shad Rm,Rn */
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_andi_i32(t0, REG(B7_4), 0x1f);
/* positive case: shift to the left */
tcg_gen_shl_i32(t1, REG(B11_8), t0);
/* negative case: shift to the right in two steps to
correctly handle the -32 case */
tcg_gen_xori_i32(t0, t0, 0x1f);
tcg_gen_sar_i32(t2, REG(B11_8), t0);
tcg_gen_sari_i32(t2, t2, 1);
/* select between the two cases */
tcg_gen_movi_i32(t0, 0);
tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
return;
case 0x400d: /* shld Rm,Rn */
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_andi_i32(t0, REG(B7_4), 0x1f);
/* positive case: shift to the left */
tcg_gen_shl_i32(t1, REG(B11_8), t0);
/* negative case: shift to the right in two steps to
correctly handle the -32 case */
tcg_gen_xori_i32(t0, t0, 0x1f);
tcg_gen_shr_i32(t2, REG(B11_8), t0);
tcg_gen_shri_i32(t2, t2, 1);
/* select between the two cases */
tcg_gen_movi_i32(t0, 0);
tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2);
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
}
return;
case 0x3008: /* sub Rm,Rn */
tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300a: /* subc Rm,Rn */
{
TCGv t0, t1;
t0 = tcg_const_tl(0);
t1 = tcg_temp_new();
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
REG(B11_8), t0, t1, cpu_sr_t);
tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
return;
case 0x300b: /* subv Rm,Rn */
{
TCGv t0, t1, t2;
t0 = tcg_temp_new();
tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4));
t1 = tcg_temp_new();
tcg_gen_xor_i32(t1, t0, REG(B7_4));
t2 = tcg_temp_new();
tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4));
tcg_gen_and_i32(t1, t1, t2);
tcg_temp_free(t2);
tcg_gen_shri_i32(cpu_sr_t, t1, 31);
tcg_temp_free(t1);
tcg_gen_mov_i32(REG(B11_8), t0);
tcg_temp_free(t0);
}
return;
case 0x2008: /* tst Rm,Rn */
{
TCGv val = tcg_temp_new();
tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
tcg_temp_free(val);
}
return;
case 0x200a: /* xor Rm,Rn */
tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
if (ctx->tbflags & FPSCR_SZ) {
int xsrc = XHACK(B7_4);
int xdst = XHACK(B11_8);
tcg_gen_mov_i32(FREG(xdst), FREG(xsrc));
tcg_gen_mov_i32(FREG(xdst + 1), FREG(xsrc + 1));
} else {
tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
}
return;
case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */