/
msa_helper.c
4508 lines (3965 loc) · 157 KB
/
msa_helper.c
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/*
* MIPS SIMD Architecture Module Instruction emulation helpers for QEMU.
*
* Copyright (c) 2014 Imagination Technologies
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "internal.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
/* Data format min and max values */
#define DF_BITS(df) (1 << ((df) + 3))
#define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1)
#define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1)
#define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1)))
#define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1)))
#define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df)))
#define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m)))
#define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df))
#define SIGNED(x, df) \
((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df)))
/* Element-by-element access macros */
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
/*
* Bit Count
* ---------
*
* +---------------+----------------------------------------------------------+
* | NLOC.B | Vector Leading Ones Count (byte) |
* | NLOC.H | Vector Leading Ones Count (halfword) |
* | NLOC.W | Vector Leading Ones Count (word) |
* | NLOC.D | Vector Leading Ones Count (doubleword) |
* | NLZC.B | Vector Leading Zeros Count (byte) |
* | NLZC.H | Vector Leading Zeros Count (halfword) |
* | NLZC.W | Vector Leading Zeros Count (word) |
* | NLZC.D | Vector Leading Zeros Count (doubleword) |
* | PCNT.B | Vector Population Count (byte) |
* | PCNT.H | Vector Population Count (halfword) |
* | PCNT.W | Vector Population Count (word) |
* | PCNT.D | Vector Population Count (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Bit Count group helpers here */
/*
* Bit Move
* --------
*
* +---------------+----------------------------------------------------------+
* | BMNZ.V | Vector Bit Move If Not Zero |
* | BMZ.V | Vector Bit Move If Zero |
* | BSEL.V | Vector Bit Select |
* | BINSL.B | Vector Bit Insert Left (byte) |
* | BINSL.H | Vector Bit Insert Left (halfword) |
* | BINSL.W | Vector Bit Insert Left (word) |
* | BINSL.D | Vector Bit Insert Left (doubleword) |
* | BINSR.B | Vector Bit Insert Right (byte) |
* | BINSR.H | Vector Bit Insert Right (halfword) |
* | BINSR.W | Vector Bit Insert Right (word) |
* | BINSR.D | Vector Bit Insert Right (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Bit Move group helpers here */
/*
* Bit Set
* -------
*
* +---------------+----------------------------------------------------------+
* | BCLR.B | Vector Bit Clear (byte) |
* | BCLR.H | Vector Bit Clear (halfword) |
* | BCLR.W | Vector Bit Clear (word) |
* | BCLR.D | Vector Bit Clear (doubleword) |
* | BNEG.B | Vector Bit Negate (byte) |
* | BNEG.H | Vector Bit Negate (halfword) |
* | BNEG.W | Vector Bit Negate (word) |
* | BNEG.D | Vector Bit Negate (doubleword) |
* | BSET.B | Vector Bit Set (byte) |
* | BSET.H | Vector Bit Set (halfword) |
* | BSET.W | Vector Bit Set (word) |
* | BSET.D | Vector Bit Set (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Bit Set group helpers here */
/*
* Fixed Multiply
* --------------
*
* +---------------+----------------------------------------------------------+
* | MADD_Q.H | Vector Fixed-Point Multiply and Add (halfword) |
* | MADD_Q.W | Vector Fixed-Point Multiply and Add (word) |
* | MADDR_Q.H | Vector Fixed-Point Multiply and Add Rounded (halfword) |
* | MADDR_Q.W | Vector Fixed-Point Multiply and Add Rounded (word) |
* | MSUB_Q.H | Vector Fixed-Point Multiply and Subtr. (halfword) |
* | MSUB_Q.W | Vector Fixed-Point Multiply and Subtr. (word) |
* | MSUBR_Q.H | Vector Fixed-Point Multiply and Subtr. Rounded (halfword)|
* | MSUBR_Q.W | Vector Fixed-Point Multiply and Subtr. Rounded (word) |
* | MUL_Q.H | Vector Fixed-Point Multiply (halfword) |
* | MUL_Q.W | Vector Fixed-Point Multiply (word) |
* | MULR_Q.H | Vector Fixed-Point Multiply Rounded (halfword) |
* | MULR_Q.W | Vector Fixed-Point Multiply Rounded (word) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Fixed Multiply group helpers here */
/*
* Float Max Min
* -------------
*
* +---------------+----------------------------------------------------------+
* | FMAX_A.W | Vector Floating-Point Maximum (Absolute) (word) |
* | FMAX_A.D | Vector Floating-Point Maximum (Absolute) (doubleword) |
* | FMAX.W | Vector Floating-Point Maximum (word) |
* | FMAX.D | Vector Floating-Point Maximum (doubleword) |
* | FMIN_A.W | Vector Floating-Point Minimum (Absolute) (word) |
* | FMIN_A.D | Vector Floating-Point Minimum (Absolute) (doubleword) |
* | FMIN.W | Vector Floating-Point Minimum (word) |
* | FMIN.D | Vector Floating-Point Minimum (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Float Max Min group helpers here */
/*
* Int Add
* -------
*
* +---------------+----------------------------------------------------------+
* | ADD_A.B | Vector Add Absolute Values (byte) |
* | ADD_A.H | Vector Add Absolute Values (halfword) |
* | ADD_A.W | Vector Add Absolute Values (word) |
* | ADD_A.D | Vector Add Absolute Values (doubleword) |
* | ADDS_A.B | Vector Signed Saturated Add (of Absolute) (byte) |
* | ADDS_A.H | Vector Signed Saturated Add (of Absolute) (halfword) |
* | ADDS_A.W | Vector Signed Saturated Add (of Absolute) (word) |
* | ADDS_A.D | Vector Signed Saturated Add (of Absolute) (doubleword) |
* | ADDS_S.B | Vector Signed Saturated Add (of Signed) (byte) |
* | ADDS_S.H | Vector Signed Saturated Add (of Signed) (halfword) |
* | ADDS_S.W | Vector Signed Saturated Add (of Signed) (word) |
* | ADDS_S.D | Vector Signed Saturated Add (of Signed) (doubleword) |
* | ADDS_U.B | Vector Unsigned Saturated Add (of Unsigned) (byte) |
* | ADDS_U.H | Vector Unsigned Saturated Add (of Unsigned) (halfword) |
* | ADDS_U.W | Vector Unsigned Saturated Add (of Unsigned) (word) |
* | ADDS_U.D | Vector Unsigned Saturated Add (of Unsigned) (doubleword) |
* | ADDV.B | Vector Add (byte) |
* | ADDV.H | Vector Add (halfword) |
* | ADDV.W | Vector Add (word) |
* | ADDV.D | Vector Add (doubleword) |
* | HSUB_S.H | Vector Signed Horizontal Add (halfword) |
* | HSUB_S.W | Vector Signed Horizontal Add (word) |
* | HSUB_S.D | Vector Signed Horizontal Add (doubleword) |
* | HSUB_U.H | Vector Unigned Horizontal Add (halfword) |
* | HSUB_U.W | Vector Unigned Horizontal Add (word) |
* | HSUB_U.D | Vector Unigned Horizontal Add (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Add group helpers here */
/*
* Int Average
* -----------
*
* +---------------+----------------------------------------------------------+
* | AVE_S.B | Vector Signed Average (byte) |
* | AVE_S.H | Vector Signed Average (halfword) |
* | AVE_S.W | Vector Signed Average (word) |
* | AVE_S.D | Vector Signed Average (doubleword) |
* | AVE_U.B | Vector Unsigned Average (byte) |
* | AVE_U.H | Vector Unsigned Average (halfword) |
* | AVE_U.W | Vector Unsigned Average (word) |
* | AVE_U.D | Vector Unsigned Average (doubleword) |
* | AVER_S.B | Vector Signed Average Rounded (byte) |
* | AVER_S.H | Vector Signed Average Rounded (halfword) |
* | AVER_S.W | Vector Signed Average Rounded (word) |
* | AVER_S.D | Vector Signed Average Rounded (doubleword) |
* | AVER_U.B | Vector Unsigned Average Rounded (byte) |
* | AVER_U.H | Vector Unsigned Average Rounded (halfword) |
* | AVER_U.W | Vector Unsigned Average Rounded (word) |
* | AVER_U.D | Vector Unsigned Average Rounded (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Average group helpers here */
/*
* Int Compare
* -----------
*
* +---------------+----------------------------------------------------------+
* | CEQ.B | Vector Compare Equal (byte) |
* | CEQ.H | Vector Compare Equal (halfword) |
* | CEQ.W | Vector Compare Equal (word) |
* | CEQ.D | Vector Compare Equal (doubleword) |
* | CLE_S.B | Vector Compare Signed Less Than or Equal (byte) |
* | CLE_S.H | Vector Compare Signed Less Than or Equal (halfword) |
* | CLE_S.W | Vector Compare Signed Less Than or Equal (word) |
* | CLE_S.D | Vector Compare Signed Less Than or Equal (doubleword) |
* | CLE_U.B | Vector Compare Unsigned Less Than or Equal (byte) |
* | CLE_U.H | Vector Compare Unsigned Less Than or Equal (halfword) |
* | CLE_U.W | Vector Compare Unsigned Less Than or Equal (word) |
* | CLE_U.D | Vector Compare Unsigned Less Than or Equal (doubleword) |
* | CLT_S.B | Vector Compare Signed Less Than (byte) |
* | CLT_S.H | Vector Compare Signed Less Than (halfword) |
* | CLT_S.W | Vector Compare Signed Less Than (word) |
* | CLT_S.D | Vector Compare Signed Less Than (doubleword) |
* | CLT_U.B | Vector Compare Unsigned Less Than (byte) |
* | CLT_U.H | Vector Compare Unsigned Less Than (halfword) |
* | CLT_U.W | Vector Compare Unsigned Less Than (word) |
* | CLT_U.D | Vector Compare Unsigned Less Than (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Compare group helpers here */
/*
* Int Divide
* ----------
*
* +---------------+----------------------------------------------------------+
* | DIV_S.B | Vector Signed Divide (byte) |
* | DIV_S.H | Vector Signed Divide (halfword) |
* | DIV_S.W | Vector Signed Divide (word) |
* | DIV_S.D | Vector Signed Divide (doubleword) |
* | DIV_U.B | Vector Unsigned Divide (byte) |
* | DIV_U.H | Vector Unsigned Divide (halfword) |
* | DIV_U.W | Vector Unsigned Divide (word) |
* | DIV_U.D | Vector Unsigned Divide (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Divide group helpers here */
/*
* Int Dot Product
* ---------------
*
* +---------------+----------------------------------------------------------+
* | DOTP_S.H | Vector Signed Dot Product (halfword) |
* | DOTP_S.W | Vector Signed Dot Product (word) |
* | DOTP_S.D | Vector Signed Dot Product (doubleword) |
* | DOTP_U.H | Vector Unsigned Dot Product (halfword) |
* | DOTP_U.W | Vector Unsigned Dot Product (word) |
* | DOTP_U.D | Vector Unsigned Dot Product (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Dot Product group helpers here */
/*
* Int Max Min
* -----------
*
* +---------------+----------------------------------------------------------+
* | MAX_A.B | Vector Maximum Based on Absolute Value (byte) |
* | MAX_A.H | Vector Maximum Based on Absolute Value (halfword) |
* | MAX_A.W | Vector Maximum Based on Absolute Value (word) |
* | MAX_A.D | Vector Maximum Based on Absolute Value (doubleword) |
* | MAX_S.B | Vector Signed Maximum (byte) |
* | MAX_S.H | Vector Signed Maximum (halfword) |
* | MAX_S.W | Vector Signed Maximum (word) |
* | MAX_S.D | Vector Signed Maximum (doubleword) |
* | MAX_U.B | Vector Unsigned Maximum (byte) |
* | MAX_U.H | Vector Unsigned Maximum (halfword) |
* | MAX_U.W | Vector Unsigned Maximum (word) |
* | MAX_U.D | Vector Unsigned Maximum (doubleword) |
* | MIN_A.B | Vector Minimum Based on Absolute Value (byte) |
* | MIN_A.H | Vector Minimum Based on Absolute Value (halfword) |
* | MIN_A.W | Vector Minimum Based on Absolute Value (word) |
* | MIN_A.D | Vector Minimum Based on Absolute Value (doubleword) |
* | MIN_S.B | Vector Signed Minimum (byte) |
* | MIN_S.H | Vector Signed Minimum (halfword) |
* | MIN_S.W | Vector Signed Minimum (word) |
* | MIN_S.D | Vector Signed Minimum (doubleword) |
* | MIN_U.B | Vector Unsigned Minimum (byte) |
* | MIN_U.H | Vector Unsigned Minimum (halfword) |
* | MIN_U.W | Vector Unsigned Minimum (word) |
* | MIN_U.D | Vector Unsigned Minimum (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Max Min group helpers here */
/*
* Int Modulo
* ----------
*
* +---------------+----------------------------------------------------------+
* | MOD_S.B | Vector Signed Modulo (byte) |
* | MOD_S.H | Vector Signed Modulo (halfword) |
* | MOD_S.W | Vector Signed Modulo (word) |
* | MOD_S.D | Vector Signed Modulo (doubleword) |
* | MOD_U.B | Vector Unsigned Modulo (byte) |
* | MOD_U.H | Vector Unsigned Modulo (halfword) |
* | MOD_U.W | Vector Unsigned Modulo (word) |
* | MOD_U.D | Vector Unsigned Modulo (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Modulo group helpers here */
/*
* Int Multiply
* ------------
*
* +---------------+----------------------------------------------------------+
* | MADDV.B | Vector Multiply and Add (byte) |
* | MADDV.H | Vector Multiply and Add (halfword) |
* | MADDV.W | Vector Multiply and Add (word) |
* | MADDV.D | Vector Multiply and Add (doubleword) |
* | MSUBV.B | Vector Multiply and Subtract (byte) |
* | MSUBV.H | Vector Multiply and Subtract (halfword) |
* | MSUBV.W | Vector Multiply and Subtract (word) |
* | MSUBV.D | Vector Multiply and Subtract (doubleword) |
* | MULV.B | Vector Multiply (byte) |
* | MULV.H | Vector Multiply (halfword) |
* | MULV.W | Vector Multiply (word) |
* | MULV.D | Vector Multiply (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Multiply group helpers here */
/*
* Int Subtract
* ------------
*
* +---------------+----------------------------------------------------------+
* | ASUB_S.B | Vector Absolute Values of Signed Subtract (byte) |
* | ASUB_S.H | Vector Absolute Values of Signed Subtract (halfword) |
* | ASUB_S.W | Vector Absolute Values of Signed Subtract (word) |
* | ASUB_S.D | Vector Absolute Values of Signed Subtract (doubleword) |
* | ASUB_U.B | Vector Absolute Values of Unsigned Subtract (byte) |
* | ASUB_U.H | Vector Absolute Values of Unsigned Subtract (halfword) |
* | ASUB_U.W | Vector Absolute Values of Unsigned Subtract (word) |
* | ASUB_U.D | Vector Absolute Values of Unsigned Subtract (doubleword) |
* | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) |
* | HSUB_S.W | Vector Signed Horizontal Subtract (word) |
* | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) |
* | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) |
* | HSUB_U.W | Vector Unigned Horizontal Subtract (word) |
* | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) |
* | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) |
* | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) |
* | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) |
* | SUBS_S.D | Vector Signed Saturated Subtract (of Signed) (doubleword)|
* | SUBS_U.B | Vector Unsigned Saturated Subtract (of Uns.) (byte) |
* | SUBS_U.H | Vector Unsigned Saturated Subtract (of Uns.) (halfword) |
* | SUBS_U.W | Vector Unsigned Saturated Subtract (of Uns.) (word) |
* | SUBS_U.D | Vector Unsigned Saturated Subtract (of Uns.) (doubleword)|
* | SUBSUS_S.B | Vector Uns. Sat. Subtract (of S. from Uns.) (byte) |
* | SUBSUS_S.H | Vector Uns. Sat. Subtract (of S. from Uns.) (halfword) |
* | SUBSUS_S.W | Vector Uns. Sat. Subtract (of S. from Uns.) (word) |
* | SUBSUS_S.D | Vector Uns. Sat. Subtract (of S. from Uns.) (doubleword) |
* | SUBSUU_U.B | Vector Signed Saturated Subtract (of Uns.) (byte) |
* | SUBSUU_U.H | Vector Signed Saturated Subtract (of Uns.) (halfword) |
* | SUBSUU_U.W | Vector Signed Saturated Subtract (of Uns.) (word) |
* | SUBSUU_U.D | Vector Signed Saturated Subtract (of Uns.) (doubleword) |
* | SUBV.B | Vector Subtract (byte) |
* | SUBV.H | Vector Subtract (halfword) |
* | SUBV.W | Vector Subtract (word) |
* | SUBV.D | Vector Subtract (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Int Subtract group helpers here */
/*
* Interleave
* ----------
*
* +---------------+----------------------------------------------------------+
* | ILVEV.B | Vector Interleave Even (byte) |
* | ILVEV.H | Vector Interleave Even (halfword) |
* | ILVEV.W | Vector Interleave Even (word) |
* | ILVEV.D | Vector Interleave Even (doubleword) |
* | ILVOD.B | Vector Interleave Odd (byte) |
* | ILVOD.H | Vector Interleave Odd (halfword) |
* | ILVOD.W | Vector Interleave Odd (word) |
* | ILVOD.D | Vector Interleave Odd (doubleword) |
* | ILVL.B | Vector Interleave Left (byte) |
* | ILVL.H | Vector Interleave Left (halfword) |
* | ILVL.W | Vector Interleave Left (word) |
* | ILVL.D | Vector Interleave Left (doubleword) |
* | ILVR.B | Vector Interleave Right (byte) |
* | ILVR.H | Vector Interleave Right (halfword) |
* | ILVR.W | Vector Interleave Right (word) |
* | ILVR.D | Vector Interleave Right (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Interleave group helpers here */
/*
* Logic
* -----
*
* +---------------+----------------------------------------------------------+
* | AND.V | Vector Logical And |
* | NOR.V | Vector Logical Negated Or |
* | OR.V | Vector Logical Or |
* | XOR.V | Vector Logical Exclusive Or |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Logic group helpers here */
/*
* Pack
* ----
*
* +---------------+----------------------------------------------------------+
* | PCKEV.B | Vector Pack Even (byte) |
* | PCKEV.H | Vector Pack Even (halfword) |
* | PCKEV.W | Vector Pack Even (word) |
* | PCKEV.D | Vector Pack Even (doubleword) |
* | PCKOD.B | Vector Pack Odd (byte) |
* | PCKOD.H | Vector Pack Odd (halfword) |
* | PCKOD.W | Vector Pack Odd (word) |
* | PCKOD.D | Vector Pack Odd (doubleword) |
* | VSHF.B | Vector Data Preserving Shuffle (byte) |
* | VSHF.H | Vector Data Preserving Shuffle (halfword) |
* | VSHF.W | Vector Data Preserving Shuffle (word) |
* | VSHF.D | Vector Data Preserving Shuffle (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Pack group helpers here */
/*
* Shift
* -----
*
* +---------------+----------------------------------------------------------+
* | SLL.B | Vector Shift Left (byte) |
* | SLL.H | Vector Shift Left (halfword) |
* | SLL.W | Vector Shift Left (word) |
* | SLL.D | Vector Shift Left (doubleword) |
* | SRA.B | Vector Shift Right Arithmetic (byte) |
* | SRA.H | Vector Shift Right Arithmetic (halfword) |
* | SRA.W | Vector Shift Right Arithmetic (word) |
* | SRA.D | Vector Shift Right Arithmetic (doubleword) |
* | SRAR.B | Vector Shift Right Arithmetic Rounded (byte) |
* | SRAR.H | Vector Shift Right Arithmetic Rounded (halfword) |
* | SRAR.W | Vector Shift Right Arithmetic Rounded (word) |
* | SRAR.D | Vector Shift Right Arithmetic Rounded (doubleword) |
* | SRL.B | Vector Shift Right Logical (byte) |
* | SRL.H | Vector Shift Right Logical (halfword) |
* | SRL.W | Vector Shift Right Logical (word) |
* | SRL.D | Vector Shift Right Logical (doubleword) |
* | SRLR.B | Vector Shift Right Logical Rounded (byte) |
* | SRLR.H | Vector Shift Right Logical Rounded (halfword) |
* | SRLR.W | Vector Shift Right Logical Rounded (word) |
* | SRLR.D | Vector Shift Right Logical Rounded (doubleword) |
* +---------------+----------------------------------------------------------+
*/
/* TODO: insert Shift group helpers here */
static inline void msa_move_v(wr_t *pwd, wr_t *pws)
{
uint32_t i;
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
pwd->d[i] = pws->d[i];
}
}
#define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
uint32_t i8) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
uint32_t i; \
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
DEST = OPERATION; \
} \
}
MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
#define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
MSA_FN_IMM8(bmnzi_b, pwd->b[i],
BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
#define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
MSA_FN_IMM8(bmzi_b, pwd->b[i],
BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
#define BIT_SELECT(dest, arg1, arg2, df) \
UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
MSA_FN_IMM8(bseli_b, pwd->b[i],
BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
#undef MSA_FN_IMM8
#define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t imm)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t wx, *pwx = &wx;
uint32_t i;
switch (df) {
case DF_BYTE:
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
pwx->b[i] = pws->b[SHF_POS(i, imm)];
}
break;
case DF_HALF:
for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
pwx->h[i] = pws->h[SHF_POS(i, imm)];
}
break;
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
pwx->w[i] = pws->w[SHF_POS(i, imm)];
}
break;
default:
assert(0);
}
msa_move_v(pwd, pwx);
}
#define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
uint32_t wt) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
uint32_t i; \
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
DEST = OPERATION; \
} \
}
MSA_FN_VECTOR(bmnz_v, pwd->d[i],
BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
MSA_FN_VECTOR(bmz_v, pwd->d[i],
BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
MSA_FN_VECTOR(bsel_v, pwd->d[i],
BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
#undef BIT_MOVE_IF_NOT_ZERO
#undef BIT_MOVE_IF_ZERO
#undef BIT_SELECT
#undef MSA_FN_VECTOR
void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
pwd->d[0] = pws->d[0] & pwt->d[0];
pwd->d[1] = pws->d[1] & pwt->d[1];
}
void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
pwd->d[0] = pws->d[0] | pwt->d[0];
pwd->d[1] = pws->d[1] | pwt->d[1];
}
void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
pwd->d[0] = ~(pws->d[0] | pwt->d[0]);
pwd->d[1] = ~(pws->d[1] | pwt->d[1]);
}
void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
wr_t *pws = &(env->active_fpu.fpr[ws].wr);
wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
pwd->d[0] = pws->d[0] ^ pwt->d[0];
pwd->d[1] = pws->d[1] ^ pwt->d[1];
}
static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 + arg2;
}
static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 - arg2;
}
static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 == arg2 ? -1 : 0;
}
static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 <= arg2 ? -1 : 0;
}
static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
return u_arg1 <= u_arg2 ? -1 : 0;
}
static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 < arg2 ? -1 : 0;
}
static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
return u_arg1 < u_arg2 ? -1 : 0;
}
static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 > arg2 ? arg1 : arg2;
}
static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
return u_arg1 > u_arg2 ? arg1 : arg2;
}
static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 < arg2 ? arg1 : arg2;
}
static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_arg2 = UNSIGNED(arg2, df);
return u_arg1 < u_arg2 ? arg1 : arg2;
}
#define MSA_BINOP_IMM_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
uint32_t wd, uint32_t ws, int32_t u5) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
uint32_t i; \
\
switch (df) { \
case DF_BYTE: \
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
} \
break; \
case DF_HALF: \
for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
} \
break; \
case DF_WORD: \
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
} \
break; \
case DF_DOUBLE: \
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
} \
break; \
default: \
assert(0); \
} \
}
MSA_BINOP_IMM_DF(addvi, addv)
MSA_BINOP_IMM_DF(subvi, subv)
MSA_BINOP_IMM_DF(ceqi, ceq)
MSA_BINOP_IMM_DF(clei_s, cle_s)
MSA_BINOP_IMM_DF(clei_u, cle_u)
MSA_BINOP_IMM_DF(clti_s, clt_s)
MSA_BINOP_IMM_DF(clti_u, clt_u)
MSA_BINOP_IMM_DF(maxi_s, max_s)
MSA_BINOP_IMM_DF(maxi_u, max_u)
MSA_BINOP_IMM_DF(mini_s, min_s)
MSA_BINOP_IMM_DF(mini_u, min_u)
#undef MSA_BINOP_IMM_DF
void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
int32_t s10)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
uint32_t i;
switch (df) {
case DF_BYTE:
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
pwd->b[i] = (int8_t)s10;
}
break;
case DF_HALF:
for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
pwd->h[i] = (int16_t)s10;
}
break;
case DF_WORD:
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
pwd->w[i] = (int32_t)s10;
}
break;
case DF_DOUBLE:
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
pwd->d[i] = (int64_t)s10;
}
break;
default:
assert(0);
}
}
/* Data format bit position and unsigned values */
#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
return arg1 << b_arg2;
}
static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
return arg1 >> b_arg2;
}
static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
int32_t b_arg2 = BIT_POSITION(arg2, df);
return u_arg1 >> b_arg2;
}
static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
}
static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
return UNSIGNED(arg1 | (1LL << b_arg2), df);
}
static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
}
static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_dest = UNSIGNED(dest, df);
int32_t sh_d = BIT_POSITION(arg2, df) + 1;
int32_t sh_a = DF_BITS(df) - sh_d;
if (sh_d == DF_BITS(df)) {
return u_arg1;
} else {
return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
}
}
static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
uint64_t u_dest = UNSIGNED(dest, df);
int32_t sh_d = BIT_POSITION(arg2, df) + 1;
int32_t sh_a = DF_BITS(df) - sh_d;
if (sh_d == DF_BITS(df)) {
return u_arg1;
} else {
return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
}
}
static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
{
return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
arg > M_MAX_INT(m + 1) ? M_MAX_INT(m + 1) :
arg;
}
static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
{
uint64_t u_arg = UNSIGNED(arg, df);
return u_arg < M_MAX_UINT(m + 1) ? u_arg :
M_MAX_UINT(m + 1);
}
static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
if (b_arg2 == 0) {
return arg1;
} else {
int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
return (arg1 >> b_arg2) + r_bit;
}
}
static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t u_arg1 = UNSIGNED(arg1, df);
int32_t b_arg2 = BIT_POSITION(arg2, df);
if (b_arg2 == 0) {
return u_arg1;
} else {
uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
return (u_arg1 >> b_arg2) + r_bit;
}
}
#define MSA_BINOP_IMMU_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
uint32_t ws, uint32_t u5) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
uint32_t i; \
\
switch (df) { \
case DF_BYTE: \
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \
} \
break; \
case DF_HALF: \
for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \
} \
break; \
case DF_WORD: \
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \
} \
break; \
case DF_DOUBLE: \
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \
} \
break; \
default: \
assert(0); \
} \
}
MSA_BINOP_IMMU_DF(slli, sll)
MSA_BINOP_IMMU_DF(srai, sra)
MSA_BINOP_IMMU_DF(srli, srl)
MSA_BINOP_IMMU_DF(bclri, bclr)
MSA_BINOP_IMMU_DF(bseti, bset)
MSA_BINOP_IMMU_DF(bnegi, bneg)
MSA_BINOP_IMMU_DF(sat_s, sat_s)
MSA_BINOP_IMMU_DF(sat_u, sat_u)
MSA_BINOP_IMMU_DF(srari, srar)
MSA_BINOP_IMMU_DF(srlri, srlr)
#undef MSA_BINOP_IMMU_DF
#define MSA_TEROP_IMMU_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
uint32_t wd, uint32_t ws, uint32_t u5) \
{ \
wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
uint32_t i; \
\
switch (df) { \
case DF_BYTE: \
for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \
u5); \
} \
break; \
case DF_HALF: \
for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \
pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \
u5); \
} \
break; \
case DF_WORD: \
for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \
pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \
u5); \
} \
break; \
case DF_DOUBLE: \
for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \
u5); \
} \
break; \
default: \
assert(0); \
} \
}
MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
return abs_arg1 > abs_arg2 ? arg1 : arg2;
}
static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
return abs_arg1 < abs_arg2 ? arg1 : arg2;
}
static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;