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translate.c
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translate.c
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/*
* Xtensa ISA:
* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
*
* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of the Open Source and Linux Lab nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "disas/disas.h"
#include "tcg/tcg-op.h"
#include "qemu/log.h"
#include "qemu/qemu-print.h"
#include "exec/cpu_ldst.h"
#include "semihosting/semihost.h"
#include "exec/translator.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/log.h"
struct DisasContext {
DisasContextBase base;
const XtensaConfig *config;
uint32_t pc;
int cring;
int ring;
uint32_t lbeg_off;
uint32_t lend;
bool sar_5bit;
bool sar_m32_5bit;
bool sar_m32_allocated;
TCGv_i32 sar_m32;
unsigned window;
unsigned callinc;
bool cwoe;
bool debug;
bool icount;
TCGv_i32 next_icount;
unsigned cpenable;
uint32_t op_flags;
xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH];
xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH];
};
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];
static TCGv_i32 cpu_FR[16];
static TCGv_i64 cpu_FRD[16];
static TCGv_i32 cpu_MR[4];
static TCGv_i32 cpu_BR[16];
static TCGv_i32 cpu_BR4[4];
static TCGv_i32 cpu_BR8[2];
static TCGv_i32 cpu_SR[256];
static TCGv_i32 cpu_UR[256];
static TCGv_i32 cpu_windowbase_next;
static TCGv_i32 cpu_exclusive_addr;
static TCGv_i32 cpu_exclusive_val;
static GHashTable *xtensa_regfile_table;
#include "exec/gen-icount.h"
static char *sr_name[256];
static char *ur_name[256];
void xtensa_collect_sr_names(const XtensaConfig *config)
{
xtensa_isa isa = config->isa;
int n = xtensa_isa_num_sysregs(isa);
int i;
for (i = 0; i < n; ++i) {
int sr = xtensa_sysreg_number(isa, i);
if (sr >= 0 && sr < 256) {
const char *name = xtensa_sysreg_name(isa, i);
char **pname =
(xtensa_sysreg_is_user(isa, i) ? ur_name : sr_name) + sr;
if (*pname) {
if (strstr(*pname, name) == NULL) {
char *new_name =
malloc(strlen(*pname) + strlen(name) + 2);
strcpy(new_name, *pname);
strcat(new_name, "/");
strcat(new_name, name);
free(*pname);
*pname = new_name;
}
} else {
*pname = strdup(name);
}
}
}
}
void xtensa_translate_init(void)
{
static const char * const regnames[] = {
"ar0", "ar1", "ar2", "ar3",
"ar4", "ar5", "ar6", "ar7",
"ar8", "ar9", "ar10", "ar11",
"ar12", "ar13", "ar14", "ar15",
};
static const char * const fregnames[] = {
"f0", "f1", "f2", "f3",
"f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11",
"f12", "f13", "f14", "f15",
};
static const char * const mregnames[] = {
"m0", "m1", "m2", "m3",
};
static const char * const bregnames[] = {
"b0", "b1", "b2", "b3",
"b4", "b5", "b6", "b7",
"b8", "b9", "b10", "b11",
"b12", "b13", "b14", "b15",
};
int i;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
fregs[i].f32[FP_F32_LOW]),
fregnames[i]);
}
for (i = 0; i < 16; i++) {
cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUXtensaState,
fregs[i].f64),
fregnames[i]);
}
for (i = 0; i < 4; i++) {
cpu_MR[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
sregs[MR + i]),
mregnames[i]);
}
for (i = 0; i < 16; i++) {
cpu_BR[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
if (i % 4 == 0) {
cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
}
if (i % 8 == 0) {
cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
sregs[BR]),
bregnames[i]);
}
}
for (i = 0; i < 256; ++i) {
if (sr_name[i]) {
cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
sregs[i]),
sr_name[i]);
}
}
for (i = 0; i < 256; ++i) {
if (ur_name[i]) {
cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState,
uregs[i]),
ur_name[i]);
}
}
cpu_windowbase_next =
tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, windowbase_next),
"windowbase_next");
cpu_exclusive_addr =
tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, exclusive_addr),
"exclusive_addr");
cpu_exclusive_val =
tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, exclusive_val),
"exclusive_val");
}
void **xtensa_get_regfile_by_name(const char *name, int entries, int bits)
{
char *geometry_name;
void **res;
if (xtensa_regfile_table == NULL) {
xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal);
/*
* AR is special. Xtensa translator uses it as a current register
* window, but configuration overlays represent it as a complete
* physical register file.
*/
g_hash_table_insert(xtensa_regfile_table,
(void *)"AR 16x32", (void *)cpu_R);
g_hash_table_insert(xtensa_regfile_table,
(void *)"AR 32x32", (void *)cpu_R);
g_hash_table_insert(xtensa_regfile_table,
(void *)"AR 64x32", (void *)cpu_R);
g_hash_table_insert(xtensa_regfile_table,
(void *)"MR 4x32", (void *)cpu_MR);
g_hash_table_insert(xtensa_regfile_table,
(void *)"FR 16x32", (void *)cpu_FR);
g_hash_table_insert(xtensa_regfile_table,
(void *)"FR 16x64", (void *)cpu_FRD);
g_hash_table_insert(xtensa_regfile_table,
(void *)"BR 16x1", (void *)cpu_BR);
g_hash_table_insert(xtensa_regfile_table,
(void *)"BR4 4x4", (void *)cpu_BR4);
g_hash_table_insert(xtensa_regfile_table,
(void *)"BR8 2x8", (void *)cpu_BR8);
}
geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits);
res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name);
g_free(geometry_name);
return res;
}
static inline bool option_enabled(DisasContext *dc, int opt)
{
return xtensa_option_enabled(dc->config, opt);
}
static void init_sar_tracker(DisasContext *dc)
{
dc->sar_5bit = false;
dc->sar_m32_5bit = false;
dc->sar_m32_allocated = false;
}
static void reset_sar_tracker(DisasContext *dc)
{
if (dc->sar_m32_allocated) {
tcg_temp_free(dc->sar_m32);
}
}
static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
if (dc->sar_m32_5bit) {
tcg_gen_discard_i32(dc->sar_m32);
}
dc->sar_5bit = true;
dc->sar_m32_5bit = false;
}
static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
{
if (!dc->sar_m32_allocated) {
dc->sar_m32 = tcg_temp_local_new_i32();
dc->sar_m32_allocated = true;
}
tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
tcg_gen_sub_i32(cpu_SR[SAR], tcg_constant_i32(32), dc->sar_m32);
dc->sar_5bit = false;
dc->sar_m32_5bit = true;
}
static void gen_exception(DisasContext *dc, int excp)
{
gen_helper_exception(cpu_env, tcg_constant_i32(excp));
}
static void gen_exception_cause(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause));
if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
cause == SYSCALL_CAUSE) {
dc->base.is_jmp = DISAS_NORETURN;
}
}
static void gen_debug_exception(DisasContext *dc, uint32_t cause)
{
TCGv_i32 pc = tcg_constant_i32(dc->pc);
gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause));
if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
dc->base.is_jmp = DISAS_NORETURN;
}
}
static bool gen_check_privilege(DisasContext *dc)
{
#ifndef CONFIG_USER_ONLY
if (!dc->cring) {
return true;
}
#endif
gen_exception_cause(dc, PRIVILEGED_CAUSE);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask)
{
cp_mask &= ~dc->cpenable;
if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && cp_mask) {
gen_exception_cause(dc, COPROCESSOR0_DISABLED + ctz32(cp_mask));
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
return true;
}
static int gen_postprocess(DisasContext *dc, int slot);
static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
{
tcg_gen_mov_i32(cpu_pc, dest);
if (dc->icount) {
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
}
if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
slot = gen_postprocess(dc, slot);
}
if (slot >= 0) {
tcg_gen_goto_tb(slot);
tcg_gen_exit_tb(dc->base.tb, slot);
} else {
tcg_gen_exit_tb(NULL, 0);
}
dc->base.is_jmp = DISAS_NORETURN;
}
static void gen_jump(DisasContext *dc, TCGv dest)
{
gen_jump_slot(dc, dest, -1);
}
static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot)
{
return translator_use_goto_tb(&dc->base, dest) ? slot : -1;
}
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
{
gen_jump_slot(dc, tcg_constant_i32(dest),
adjust_jump_slot(dc, dest, slot));
}
static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
int slot)
{
tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
tcg_constant_i32(callinc), PS_CALLINC_SHIFT, PS_CALLINC_LEN);
tcg_gen_movi_i32(cpu_R[callinc << 2],
(callinc << 30) | (dc->base.pc_next & 0x3fffffff));
gen_jump_slot(dc, dest, slot);
}
static bool gen_check_loop_end(DisasContext *dc, int slot)
{
if (dc->base.pc_next == dc->lend) {
TCGLabel *label = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
if (dc->lbeg_off) {
gen_jumpi(dc, dc->base.pc_next - dc->lbeg_off, slot);
} else {
gen_jump(dc, cpu_SR[LBEG]);
}
gen_set_label(label);
gen_jumpi(dc, dc->base.pc_next, -1);
return true;
}
return false;
}
static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
{
if (!gen_check_loop_end(dc, slot)) {
gen_jumpi(dc, dc->base.pc_next, slot);
}
}
static void gen_brcond(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, TCGv_i32 t1, uint32_t addr)
{
TCGLabel *label = gen_new_label();
tcg_gen_brcond_i32(cond, t0, t1, label);
gen_jumpi_check_loop_end(dc, 0);
gen_set_label(label);
gen_jumpi(dc, addr, 1);
}
static void gen_brcondi(DisasContext *dc, TCGCond cond,
TCGv_i32 t0, uint32_t t1, uint32_t addr)
{
gen_brcond(dc, cond, t0, tcg_constant_i32(t1), addr);
}
static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL;
}
static uint32_t test_exceptions_ccompare(DisasContext *dc,
const OpcodeArg arg[],
const uint32_t par[])
{
unsigned n = par[0] - CCOMPARE;
if (n >= dc->config->nccompare) {
return XTENSA_OP_ILL;
}
return test_exceptions_sr(dc, arg, par);
}
static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
unsigned n = MAX_NDBREAK;
if (par[0] >= DBREAKA && par[0] < DBREAKA + MAX_NDBREAK) {
n = par[0] - DBREAKA;
}
if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) {
n = par[0] - DBREAKC;
}
if (n >= dc->config->ndbreak) {
return XTENSA_OP_ILL;
}
return test_exceptions_sr(dc, arg, par);
}
static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
unsigned n = par[0] - IBREAKA;
if (n >= dc->config->nibreak) {
return XTENSA_OP_ILL;
}
return test_exceptions_sr(dc, arg, par);
}
static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
unsigned n = MAX_NLEVEL + 1;
if (par[0] >= EXCSAVE1 && par[0] < EXCSAVE1 + MAX_NLEVEL) {
n = par[0] - EXCSAVE1 + 1;
}
if (par[0] >= EPC1 && par[0] < EPC1 + MAX_NLEVEL) {
n = par[0] - EPC1 + 1;
}
if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) {
n = par[0] - EPS2 + 2;
}
if (n > dc->config->nlevel) {
return XTENSA_OP_ILL;
}
return test_exceptions_sr(dc, arg, par);
}
static MemOp gen_load_store_alignment(DisasContext *dc, MemOp mop,
TCGv_i32 addr)
{
if ((mop & MO_SIZE) == MO_8) {
return mop;
}
if ((mop & MO_AMASK) == MO_UNALN &&
!option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT)) {
mop |= MO_ALIGN;
}
if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
tcg_gen_andi_i32(addr, addr, ~0 << get_alignment_bits(mop));
}
return mop;
}
static bool gen_window_check(DisasContext *dc, uint32_t mask)
{
unsigned r = 31 - clz32(mask);
if (r / 4 > dc->window) {
TCGv_i32 pc = tcg_constant_i32(dc->pc);
TCGv_i32 w = tcg_constant_i32(r / 4);
gen_helper_window_check(cpu_env, pc, w);
dc->base.is_jmp = DISAS_NORETURN;
return false;
}
return true;
}
static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
{
TCGv_i32 m = tcg_temp_new_i32();
if (hi) {
(is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
} else {
(is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
}
return m;
}
static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[])
{
TCGLabel *label = gen_new_label();
tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label);
gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
gen_set_label(label);
}
static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0)
{
return xtensa_isa_length_from_chars(dc->config->isa, &op0);
}
static int gen_postprocess(DisasContext *dc, int slot)
{
uint32_t op_flags = dc->op_flags;
#ifndef CONFIG_USER_ONLY
if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) {
if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
}
gen_helper_check_interrupts(cpu_env);
}
#endif
if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) {
gen_helper_sync_windowbase(cpu_env);
}
if (op_flags & XTENSA_OP_EXIT_TB_M1) {
slot = -1;
}
return slot;
}
struct opcode_arg_copy {
uint32_t resource;
void *temp;
OpcodeArg *arg;
};
struct opcode_arg_info {
uint32_t resource;
int index;
};
struct slot_prop {
XtensaOpcodeOps *ops;
OpcodeArg arg[MAX_OPCODE_ARGS];
struct opcode_arg_info in[MAX_OPCODE_ARGS];
struct opcode_arg_info out[MAX_OPCODE_ARGS];
unsigned n_in;
unsigned n_out;
uint32_t op_flags;
};
enum resource_type {
RES_REGFILE,
RES_STATE,
RES_MAX,
};
static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n)
{
assert(r < RES_MAX && g < 256 && n < 65536);
return (r << 24) | (g << 16) | n;
}
static enum resource_type get_resource_type(uint32_t resource)
{
return resource >> 24;
}
/*
* a depends on b if b must be executed before a,
* because a's side effects will destroy b's inputs.
*/
static bool op_depends_on(const struct slot_prop *a,
const struct slot_prop *b)
{
unsigned i = 0;
unsigned j = 0;
if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
return true;
}
if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
(b->op_flags & XTENSA_OP_LOAD_STORE)) {
return true;
}
while (i < a->n_out && j < b->n_in) {
if (a->out[i].resource < b->in[j].resource) {
++i;
} else if (a->out[i].resource > b->in[j].resource) {
++j;
} else {
return true;
}
}
return false;
}
/*
* Try to break a dependency on b, append temporary register copy records
* to the end of copy and update n_copy in case of success.
* This is not always possible: e.g. control flow must always be the last,
* load/store must be first and state dependencies are not supported yet.
*/
static bool break_dependency(struct slot_prop *a,
struct slot_prop *b,
struct opcode_arg_copy *copy,
unsigned *n_copy)
{
unsigned i = 0;
unsigned j = 0;
unsigned n = *n_copy;
bool rv = false;
if (a->op_flags & XTENSA_OP_CONTROL_FLOW) {
return false;
}
if ((a->op_flags & XTENSA_OP_LOAD_STORE) <
(b->op_flags & XTENSA_OP_LOAD_STORE)) {
return false;
}
while (i < a->n_out && j < b->n_in) {
if (a->out[i].resource < b->in[j].resource) {
++i;
} else if (a->out[i].resource > b->in[j].resource) {
++j;
} else {
int index = b->in[j].index;
if (get_resource_type(a->out[i].resource) != RES_REGFILE ||
index < 0) {
return false;
}
copy[n].resource = b->in[j].resource;
copy[n].arg = b->arg + index;
++n;
++j;
rv = true;
}
}
*n_copy = n;
return rv;
}
/*
* Calculate evaluation order for slot opcodes.
* Build opcode order graph and output its nodes in topological sort order.
* An edge a -> b in the graph means that opcode a must be followed by
* opcode b.
*/
static bool tsort(struct slot_prop *slot,
struct slot_prop *sorted[],
unsigned n,
struct opcode_arg_copy *copy,
unsigned *n_copy)
{
struct tsnode {
unsigned n_in_edge;
unsigned n_out_edge;
unsigned out_edge[MAX_INSN_SLOTS];
} node[MAX_INSN_SLOTS];
unsigned in[MAX_INSN_SLOTS];
unsigned i, j;
unsigned n_in = 0;
unsigned n_out = 0;
unsigned n_edge = 0;
unsigned in_idx = 0;
unsigned node_idx = 0;
for (i = 0; i < n; ++i) {
node[i].n_in_edge = 0;
node[i].n_out_edge = 0;
}
for (i = 0; i < n; ++i) {
unsigned n_out_edge = 0;
for (j = 0; j < n; ++j) {
if (i != j && op_depends_on(slot + j, slot + i)) {
node[i].out_edge[n_out_edge] = j;
++node[j].n_in_edge;
++n_out_edge;
++n_edge;
}
}
node[i].n_out_edge = n_out_edge;
}
for (i = 0; i < n; ++i) {
if (!node[i].n_in_edge) {
in[n_in] = i;
++n_in;
}
}
again:
for (; in_idx < n_in; ++in_idx) {
i = in[in_idx];
sorted[n_out] = slot + i;
++n_out;
for (j = 0; j < node[i].n_out_edge; ++j) {
--n_edge;
if (--node[node[i].out_edge[j]].n_in_edge == 0) {
in[n_in] = node[i].out_edge[j];
++n_in;
}
}
}
if (n_edge) {
for (; node_idx < n; ++node_idx) {
struct tsnode *cnode = node + node_idx;
if (cnode->n_in_edge) {
for (j = 0; j < cnode->n_out_edge; ++j) {
unsigned k = cnode->out_edge[j];
if (break_dependency(slot + k, slot + node_idx,
copy, n_copy) &&
--node[k].n_in_edge == 0) {
in[n_in] = k;
++n_in;
--n_edge;
cnode->out_edge[j] =
cnode->out_edge[cnode->n_out_edge - 1];
--cnode->n_out_edge;
goto again;
}
}
}
}
}
return n_edge == 0;
}
static void opcode_add_resource(struct slot_prop *op,
uint32_t resource, char direction,
int index)
{
switch (direction) {
case 'm':
case 'i':
assert(op->n_in < ARRAY_SIZE(op->in));
op->in[op->n_in].resource = resource;
op->in[op->n_in].index = index;
++op->n_in;
/* fall through */
case 'o':
if (direction == 'm' || direction == 'o') {
assert(op->n_out < ARRAY_SIZE(op->out));
op->out[op->n_out].resource = resource;
op->out[op->n_out].index = index;
++op->n_out;
}
break;
default:
g_assert_not_reached();
}
}
static int resource_compare(const void *a, const void *b)
{
const struct opcode_arg_info *pa = a;
const struct opcode_arg_info *pb = b;
return pa->resource < pb->resource ?
-1 : (pa->resource > pb->resource ? 1 : 0);
}
static int arg_copy_compare(const void *a, const void *b)
{
const struct opcode_arg_copy *pa = a;
const struct opcode_arg_copy *pb = b;
return pa->resource < pb->resource ?
-1 : (pa->resource > pb->resource ? 1 : 0);
}
static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
{
xtensa_isa isa = dc->config->isa;
unsigned char b[MAX_INSN_LENGTH] = {translator_ldub(env, &dc->base,
dc->pc)};
unsigned len = xtensa_op0_insn_len(dc, b[0]);
xtensa_format fmt;
int slot, slots;
unsigned i;
uint32_t op_flags = 0;
struct slot_prop slot_prop[MAX_INSN_SLOTS];
struct slot_prop *ordered[MAX_INSN_SLOTS];
struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS];
unsigned n_arg_copy = 0;
uint32_t debug_cause = 0;
uint32_t windowed_register = 0;
uint32_t coprocessor = 0;
if (len == XTENSA_UNDEFINED) {
qemu_log_mask(LOG_GUEST_ERROR,
"unknown instruction length (pc = %08x)\n",
dc->pc);
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
dc->base.pc_next = dc->pc + 1;
return;
}
dc->base.pc_next = dc->pc + len;
for (i = 1; i < len; ++i) {
b[i] = translator_ldub(env, &dc->base, dc->pc + i);
}
xtensa_insnbuf_from_chars(isa, dc->insnbuf, b, len);
fmt = xtensa_format_decode(isa, dc->insnbuf);
if (fmt == XTENSA_UNDEFINED) {
qemu_log_mask(LOG_GUEST_ERROR,
"unrecognized instruction format (pc = %08x)\n",
dc->pc);
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return;
}
slots = xtensa_format_num_slots(isa, fmt);
for (slot = 0; slot < slots; ++slot) {
xtensa_opcode opc;
int opnd, vopnd, opnds;
OpcodeArg *arg = slot_prop[slot].arg;
XtensaOpcodeOps *ops;
xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf);
opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf);
if (opc == XTENSA_UNDEFINED) {
qemu_log_mask(LOG_GUEST_ERROR,
"unrecognized opcode in slot %d (pc = %08x)\n",
slot, dc->pc);
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return;
}
opnds = xtensa_opcode_num_operands(isa, opc);
for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
void **register_file = NULL;
xtensa_regfile rf;
if (xtensa_operand_is_register(isa, opc, opnd)) {
rf = xtensa_operand_regfile(isa, opc, opnd);
register_file = dc->config->regfile[rf];
if (rf == dc->config->a_regfile) {
uint32_t v;
xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
dc->slotbuf, &v);
xtensa_operand_decode(isa, opc, opnd, &v);
windowed_register |= 1u << v;
}
}
if (xtensa_operand_is_visible(isa, opc, opnd)) {
uint32_t v;
xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
dc->slotbuf, &v);
xtensa_operand_decode(isa, opc, opnd, &v);
arg[vopnd].raw_imm = v;
if (xtensa_operand_is_PCrelative(isa, opc, opnd)) {
xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc);
}
arg[vopnd].imm = v;
if (register_file) {
arg[vopnd].in = register_file[v];
arg[vopnd].out = register_file[v];
arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf);
} else {
arg[vopnd].num_bits = 32;
}
++vopnd;
}
}
ops = dc->config->opcode_ops[opc];
slot_prop[slot].ops = ops;
if (ops) {
op_flags |= ops->op_flags;
if (ops->test_exceptions) {
op_flags |= ops->test_exceptions(dc, arg, ops->par);
}
} else {
qemu_log_mask(LOG_UNIMP,
"unimplemented opcode '%s' in slot %d (pc = %08x)\n",
xtensa_opcode_name(isa, opc), slot, dc->pc);
op_flags |= XTENSA_OP_ILL;
}
if (op_flags & XTENSA_OP_ILL) {
gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
return;
}
if (op_flags & XTENSA_OP_DEBUG_BREAK) {
debug_cause |= ops->par[0];
}
if (ops->test_overflow) {
windowed_register |= ops->test_overflow(dc, arg, ops->par);
}
coprocessor |= ops->coprocessor;
if (slots > 1) {
slot_prop[slot].n_in = 0;
slot_prop[slot].n_out = 0;
slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE;
opnds = xtensa_opcode_num_operands(isa, opc);
for (opnd = vopnd = 0; opnd < opnds; ++opnd) {
bool visible = xtensa_operand_is_visible(isa, opc, opnd);
if (xtensa_operand_is_register(isa, opc, opnd)) {
xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd);
uint32_t v = 0;
xtensa_operand_get_field(isa, opc, opnd, fmt, slot,
dc->slotbuf, &v);
xtensa_operand_decode(isa, opc, opnd, &v);
opcode_add_resource(slot_prop + slot,
encode_resource(RES_REGFILE, rf, v),
xtensa_operand_inout(isa, opc, opnd),
visible ? vopnd : -1);
}
if (visible) {
++vopnd;
}
}
opnds = xtensa_opcode_num_stateOperands(isa, opc);
for (opnd = 0; opnd < opnds; ++opnd) {
xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd);