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tcg-target.c.inc
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tcg-target.c.inc
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/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
* Copyright (c) 2009 Alexander Graf <agraf@suse.de>
* Copyright (c) 2010 Richard Henderson <rth@twiddle.net>
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/* We only support generating code for 64-bit mode. */
#if TCG_TARGET_REG_BITS != 64
#error "unsupported code generation mode"
#endif
#include "../tcg-pool.c.inc"
#include "elf.h"
/* ??? The translation blocks produced by TCG are generally small enough to
be entirely reachable with a 16-bit displacement. Leaving the option for
a 32-bit displacement here Just In Case. */
#define USE_LONG_BRANCHES 0
#define TCG_CT_CONST_S16 0x100
#define TCG_CT_CONST_S32 0x200
#define TCG_CT_CONST_S33 0x400
#define TCG_CT_CONST_ZERO 0x800
/* Several places within the instruction set 0 means "no register"
rather than TCG_REG_R0. */
#define TCG_REG_NONE 0
/* A scratch register that may be be used throughout the backend. */
#define TCG_TMP0 TCG_REG_R1
/* A scratch register that holds a pointer to the beginning of the TB.
We don't need this when we have pc-relative loads with the general
instructions extension facility. */
#define TCG_REG_TB TCG_REG_R12
#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT))
#ifndef CONFIG_SOFTMMU
#define TCG_GUEST_BASE_REG TCG_REG_R13
#endif
/* All of the following instructions are prefixed with their instruction
format, and are defined as 8- or 16-bit quantities, even when the two
halves of the 16-bit quantity may appear 32 bits apart in the insn.
This makes it easy to copy the values from the tables in Appendix B. */
typedef enum S390Opcode {
RIL_AFI = 0xc209,
RIL_AGFI = 0xc208,
RIL_ALFI = 0xc20b,
RIL_ALGFI = 0xc20a,
RIL_BRASL = 0xc005,
RIL_BRCL = 0xc004,
RIL_CFI = 0xc20d,
RIL_CGFI = 0xc20c,
RIL_CLFI = 0xc20f,
RIL_CLGFI = 0xc20e,
RIL_CLRL = 0xc60f,
RIL_CLGRL = 0xc60a,
RIL_CRL = 0xc60d,
RIL_CGRL = 0xc608,
RIL_IIHF = 0xc008,
RIL_IILF = 0xc009,
RIL_LARL = 0xc000,
RIL_LGFI = 0xc001,
RIL_LGRL = 0xc408,
RIL_LLIHF = 0xc00e,
RIL_LLILF = 0xc00f,
RIL_LRL = 0xc40d,
RIL_MSFI = 0xc201,
RIL_MSGFI = 0xc200,
RIL_NIHF = 0xc00a,
RIL_NILF = 0xc00b,
RIL_OIHF = 0xc00c,
RIL_OILF = 0xc00d,
RIL_SLFI = 0xc205,
RIL_SLGFI = 0xc204,
RIL_XIHF = 0xc006,
RIL_XILF = 0xc007,
RI_AGHI = 0xa70b,
RI_AHI = 0xa70a,
RI_BRC = 0xa704,
RI_CHI = 0xa70e,
RI_CGHI = 0xa70f,
RI_IIHH = 0xa500,
RI_IIHL = 0xa501,
RI_IILH = 0xa502,
RI_IILL = 0xa503,
RI_LGHI = 0xa709,
RI_LLIHH = 0xa50c,
RI_LLIHL = 0xa50d,
RI_LLILH = 0xa50e,
RI_LLILL = 0xa50f,
RI_MGHI = 0xa70d,
RI_MHI = 0xa70c,
RI_NIHH = 0xa504,
RI_NIHL = 0xa505,
RI_NILH = 0xa506,
RI_NILL = 0xa507,
RI_OIHH = 0xa508,
RI_OIHL = 0xa509,
RI_OILH = 0xa50a,
RI_OILL = 0xa50b,
RIE_CGIJ = 0xec7c,
RIE_CGRJ = 0xec64,
RIE_CIJ = 0xec7e,
RIE_CLGRJ = 0xec65,
RIE_CLIJ = 0xec7f,
RIE_CLGIJ = 0xec7d,
RIE_CLRJ = 0xec77,
RIE_CRJ = 0xec76,
RIE_LOCGHI = 0xec46,
RIE_RISBG = 0xec55,
RRE_AGR = 0xb908,
RRE_ALGR = 0xb90a,
RRE_ALCR = 0xb998,
RRE_ALCGR = 0xb988,
RRE_CGR = 0xb920,
RRE_CLGR = 0xb921,
RRE_DLGR = 0xb987,
RRE_DLR = 0xb997,
RRE_DSGFR = 0xb91d,
RRE_DSGR = 0xb90d,
RRE_FLOGR = 0xb983,
RRE_LGBR = 0xb906,
RRE_LCGR = 0xb903,
RRE_LGFR = 0xb914,
RRE_LGHR = 0xb907,
RRE_LGR = 0xb904,
RRE_LLGCR = 0xb984,
RRE_LLGFR = 0xb916,
RRE_LLGHR = 0xb985,
RRE_LRVR = 0xb91f,
RRE_LRVGR = 0xb90f,
RRE_LTGR = 0xb902,
RRE_MLGR = 0xb986,
RRE_MSGR = 0xb90c,
RRE_MSR = 0xb252,
RRE_NGR = 0xb980,
RRE_OGR = 0xb981,
RRE_SGR = 0xb909,
RRE_SLGR = 0xb90b,
RRE_SLBR = 0xb999,
RRE_SLBGR = 0xb989,
RRE_XGR = 0xb982,
RRF_LOCR = 0xb9f2,
RRF_LOCGR = 0xb9e2,
RRF_NRK = 0xb9f4,
RRF_NGRK = 0xb9e4,
RRF_ORK = 0xb9f6,
RRF_OGRK = 0xb9e6,
RRF_SRK = 0xb9f9,
RRF_SGRK = 0xb9e9,
RRF_SLRK = 0xb9fb,
RRF_SLGRK = 0xb9eb,
RRF_XRK = 0xb9f7,
RRF_XGRK = 0xb9e7,
RR_AR = 0x1a,
RR_ALR = 0x1e,
RR_BASR = 0x0d,
RR_BCR = 0x07,
RR_CLR = 0x15,
RR_CR = 0x19,
RR_DR = 0x1d,
RR_LCR = 0x13,
RR_LR = 0x18,
RR_LTR = 0x12,
RR_NR = 0x14,
RR_OR = 0x16,
RR_SR = 0x1b,
RR_SLR = 0x1f,
RR_XR = 0x17,
RSY_RLL = 0xeb1d,
RSY_RLLG = 0xeb1c,
RSY_SLLG = 0xeb0d,
RSY_SLLK = 0xebdf,
RSY_SRAG = 0xeb0a,
RSY_SRAK = 0xebdc,
RSY_SRLG = 0xeb0c,
RSY_SRLK = 0xebde,
RS_SLL = 0x89,
RS_SRA = 0x8a,
RS_SRL = 0x88,
RXY_AG = 0xe308,
RXY_AY = 0xe35a,
RXY_CG = 0xe320,
RXY_CLG = 0xe321,
RXY_CLY = 0xe355,
RXY_CY = 0xe359,
RXY_LAY = 0xe371,
RXY_LB = 0xe376,
RXY_LG = 0xe304,
RXY_LGB = 0xe377,
RXY_LGF = 0xe314,
RXY_LGH = 0xe315,
RXY_LHY = 0xe378,
RXY_LLGC = 0xe390,
RXY_LLGF = 0xe316,
RXY_LLGH = 0xe391,
RXY_LMG = 0xeb04,
RXY_LRV = 0xe31e,
RXY_LRVG = 0xe30f,
RXY_LRVH = 0xe31f,
RXY_LY = 0xe358,
RXY_NG = 0xe380,
RXY_OG = 0xe381,
RXY_STCY = 0xe372,
RXY_STG = 0xe324,
RXY_STHY = 0xe370,
RXY_STMG = 0xeb24,
RXY_STRV = 0xe33e,
RXY_STRVG = 0xe32f,
RXY_STRVH = 0xe33f,
RXY_STY = 0xe350,
RXY_XG = 0xe382,
RX_A = 0x5a,
RX_C = 0x59,
RX_L = 0x58,
RX_LA = 0x41,
RX_LH = 0x48,
RX_ST = 0x50,
RX_STC = 0x42,
RX_STH = 0x40,
NOP = 0x0707,
} S390Opcode;
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
"%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15"
};
#endif
/* Since R6 is a potential argument register, choose it last of the
call-saved registers. Likewise prefer the call-clobbered registers
in reverse order to maximize the chance of avoiding the arguments. */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
TCG_REG_R13,
TCG_REG_R12,
TCG_REG_R11,
TCG_REG_R10,
TCG_REG_R9,
TCG_REG_R8,
TCG_REG_R7,
TCG_REG_R6,
/* Call clobbered registers. */
TCG_REG_R14,
TCG_REG_R0,
TCG_REG_R1,
/* Argument registers, in reverse order of allocation. */
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
TCG_REG_R2,
};
static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R2,
TCG_REG_R3,
TCG_REG_R4,
TCG_REG_R5,
TCG_REG_R6,
};
static const int tcg_target_call_oarg_regs[] = {
TCG_REG_R2,
};
#define S390_CC_EQ 8
#define S390_CC_LT 4
#define S390_CC_GT 2
#define S390_CC_OV 1
#define S390_CC_NE (S390_CC_LT | S390_CC_GT)
#define S390_CC_LE (S390_CC_LT | S390_CC_EQ)
#define S390_CC_GE (S390_CC_GT | S390_CC_EQ)
#define S390_CC_NEVER 0
#define S390_CC_ALWAYS 15
/* Condition codes that result from a COMPARE and COMPARE LOGICAL. */
static const uint8_t tcg_cond_to_s390_cond[] = {
[TCG_COND_EQ] = S390_CC_EQ,
[TCG_COND_NE] = S390_CC_NE,
[TCG_COND_LT] = S390_CC_LT,
[TCG_COND_LE] = S390_CC_LE,
[TCG_COND_GT] = S390_CC_GT,
[TCG_COND_GE] = S390_CC_GE,
[TCG_COND_LTU] = S390_CC_LT,
[TCG_COND_LEU] = S390_CC_LE,
[TCG_COND_GTU] = S390_CC_GT,
[TCG_COND_GEU] = S390_CC_GE,
};
/* Condition codes that result from a LOAD AND TEST. Here, we have no
unsigned instruction variation, however since the test is vs zero we
can re-map the outcomes appropriately. */
static const uint8_t tcg_cond_to_ltr_cond[] = {
[TCG_COND_EQ] = S390_CC_EQ,
[TCG_COND_NE] = S390_CC_NE,
[TCG_COND_LT] = S390_CC_LT,
[TCG_COND_LE] = S390_CC_LE,
[TCG_COND_GT] = S390_CC_GT,
[TCG_COND_GE] = S390_CC_GE,
[TCG_COND_LTU] = S390_CC_NEVER,
[TCG_COND_LEU] = S390_CC_EQ,
[TCG_COND_GTU] = S390_CC_NE,
[TCG_COND_GEU] = S390_CC_ALWAYS,
};
#ifdef CONFIG_SOFTMMU
static void * const qemu_ld_helpers[16] = {
[MO_UB] = helper_ret_ldub_mmu,
[MO_SB] = helper_ret_ldsb_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LESW] = helper_le_ldsw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
[MO_LESL] = helper_le_ldsl_mmu,
[MO_LEQ] = helper_le_ldq_mmu,
[MO_BEUW] = helper_be_lduw_mmu,
[MO_BESW] = helper_be_ldsw_mmu,
[MO_BEUL] = helper_be_ldul_mmu,
[MO_BESL] = helper_be_ldsl_mmu,
[MO_BEQ] = helper_be_ldq_mmu,
};
static void * const qemu_st_helpers[16] = {
[MO_UB] = helper_ret_stb_mmu,
[MO_LEUW] = helper_le_stw_mmu,
[MO_LEUL] = helper_le_stl_mmu,
[MO_LEQ] = helper_le_stq_mmu,
[MO_BEUW] = helper_be_stw_mmu,
[MO_BEUL] = helper_be_stl_mmu,
[MO_BEQ] = helper_be_stq_mmu,
};
#endif
static tcg_insn_unit *tb_ret_addr;
uint64_t s390_facilities;
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
intptr_t pcrel2;
uint32_t old;
value += addend;
pcrel2 = (tcg_insn_unit *)value - code_ptr;
switch (type) {
case R_390_PC16DBL:
if (pcrel2 == (int16_t)pcrel2) {
tcg_patch16(code_ptr, pcrel2);
return true;
}
break;
case R_390_PC32DBL:
if (pcrel2 == (int32_t)pcrel2) {
tcg_patch32(code_ptr, pcrel2);
return true;
}
break;
case R_390_20:
if (value == sextract64(value, 0, 20)) {
old = *(uint32_t *)code_ptr & 0xf00000ff;
old |= ((value & 0xfff) << 16) | ((value & 0xff000) >> 4);
tcg_patch32(code_ptr, old);
return true;
}
break;
default:
g_assert_not_reached();
}
return false;
}
/* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
{
switch (*ct_str++) {
case 'r': /* all registers */
ct->regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
ct->regs = 0xffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;
case 'A':
ct->ct |= TCG_CT_CONST_S33;
break;
case 'I':
ct->ct |= TCG_CT_CONST_S16;
break;
case 'J':
ct->ct |= TCG_CT_CONST_S32;
break;
case 'Z':
ct->ct |= TCG_CT_CONST_ZERO;
break;
default:
return NULL;
}
return ct_str;
}
/* Test if a constant matches the constraint. */
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
{
int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
if (type == TCG_TYPE_I32) {
val = (int32_t)val;
}
/* The following are mutually exclusive. */
if (ct & TCG_CT_CONST_S16) {
return val == (int16_t)val;
} else if (ct & TCG_CT_CONST_S32) {
return val == (int32_t)val;
} else if (ct & TCG_CT_CONST_S33) {
return val >= -0xffffffffll && val <= 0xffffffffll;
} else if (ct & TCG_CT_CONST_ZERO) {
return val == 0;
}
return 0;
}
/* Emit instructions according to the given instruction format. */
static void tcg_out_insn_RR(TCGContext *s, S390Opcode op, TCGReg r1, TCGReg r2)
{
tcg_out16(s, (op << 8) | (r1 << 4) | r2);
}
static void tcg_out_insn_RRE(TCGContext *s, S390Opcode op,
TCGReg r1, TCGReg r2)
{
tcg_out32(s, (op << 16) | (r1 << 4) | r2);
}
static void tcg_out_insn_RRF(TCGContext *s, S390Opcode op,
TCGReg r1, TCGReg r2, int m3)
{
tcg_out32(s, (op << 16) | (m3 << 12) | (r1 << 4) | r2);
}
static void tcg_out_insn_RI(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
{
tcg_out32(s, (op << 16) | (r1 << 20) | (i2 & 0xffff));
}
static void tcg_out_insn_RIE(TCGContext *s, S390Opcode op, TCGReg r1,
int i2, int m3)
{
tcg_out16(s, (op & 0xff00) | (r1 << 4) | m3);
tcg_out32(s, (i2 << 16) | (op & 0xff));
}
static void tcg_out_insn_RIL(TCGContext *s, S390Opcode op, TCGReg r1, int i2)
{
tcg_out16(s, op | (r1 << 4));
tcg_out32(s, i2);
}
static void tcg_out_insn_RS(TCGContext *s, S390Opcode op, TCGReg r1,
TCGReg b2, TCGReg r3, int disp)
{
tcg_out32(s, (op << 24) | (r1 << 20) | (r3 << 16) | (b2 << 12)
| (disp & 0xfff));
}
static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1,
TCGReg b2, TCGReg r3, int disp)
{
tcg_out16(s, (op & 0xff00) | (r1 << 4) | r3);
tcg_out32(s, (op & 0xff) | (b2 << 28)
| ((disp & 0xfff) << 16) | ((disp & 0xff000) >> 4));
}
#define tcg_out_insn_RX tcg_out_insn_RS
#define tcg_out_insn_RXY tcg_out_insn_RSY
/* Emit an opcode with "type-checking" of the format. */
#define tcg_out_insn(S, FMT, OP, ...) \
glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__)
/* emit 64-bit shifts */
static void tcg_out_sh64(TCGContext* s, S390Opcode op, TCGReg dest,
TCGReg src, TCGReg sh_reg, int sh_imm)
{
tcg_out_insn_RSY(s, op, dest, sh_reg, src, sh_imm);
}
/* emit 32-bit shifts */
static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest,
TCGReg sh_reg, int sh_imm)
{
tcg_out_insn_RS(s, op, dest, sh_reg, 0, sh_imm);
}
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
{
if (src != dst) {
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, LR, dst, src);
} else {
tcg_out_insn(s, RRE, LGR, dst, src);
}
}
return true;
}
static const S390Opcode lli_insns[4] = {
RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH
};
static bool maybe_out_small_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long sval)
{
tcg_target_ulong uval = sval;
int i;
if (type == TCG_TYPE_I32) {
uval = (uint32_t)sval;
sval = (int32_t)sval;
}
/* Try all 32-bit insns that can load it in one go. */
if (sval >= -0x8000 && sval < 0x8000) {
tcg_out_insn(s, RI, LGHI, ret, sval);
return true;
}
for (i = 0; i < 4; i++) {
tcg_target_long mask = 0xffffull << i*16;
if ((uval & mask) == uval) {
tcg_out_insn_RI(s, lli_insns[i], ret, uval >> i*16);
return true;
}
}
return false;
}
/* load a register with an immediate value */
static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long sval, bool in_prologue)
{
tcg_target_ulong uval;
/* Try all 32-bit insns that can load it in one go. */
if (maybe_out_small_movi(s, type, ret, sval)) {
return;
}
uval = sval;
if (type == TCG_TYPE_I32) {
uval = (uint32_t)sval;
sval = (int32_t)sval;
}
/* Try all 48-bit insns that can load it in one go. */
if (s390_facilities & FACILITY_EXT_IMM) {
if (sval == (int32_t)sval) {
tcg_out_insn(s, RIL, LGFI, ret, sval);
return;
}
if (uval <= 0xffffffff) {
tcg_out_insn(s, RIL, LLILF, ret, uval);
return;
}
if ((uval & 0xffffffff) == 0) {
tcg_out_insn(s, RIL, LLIHF, ret, uval >> 32);
return;
}
}
/* Try for PC-relative address load. For odd addresses,
attempt to use an offset from the start of the TB. */
if ((sval & 1) == 0) {
ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;
if (off == (int32_t)off) {
tcg_out_insn(s, RIL, LARL, ret, off);
return;
}
} else if (USE_REG_TB && !in_prologue) {
ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;
if (off == sextract64(off, 0, 20)) {
/* This is certain to be an address within TB, and therefore
OFF will be negative; don't try RX_LA. */
tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);
return;
}
}
/* A 32-bit unsigned value can be loaded in 2 insns. And given
that LLILL, LLIHL, LLILF above did not succeed, we know that
both insns are required. */
if (uval <= 0xffffffff) {
tcg_out_insn(s, RI, LLILL, ret, uval);
tcg_out_insn(s, RI, IILH, ret, uval >> 16);
return;
}
/* Otherwise, stuff it in the constant pool. */
if (s390_facilities & FACILITY_GEN_INST_EXT) {
tcg_out_insn(s, RIL, LGRL, ret, 0);
new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
} else if (USE_REG_TB && !in_prologue) {
tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0);
new_pool_label(s, sval, R_390_20, s->code_ptr - 2,
-(intptr_t)s->code_gen_ptr);
} else {
TCGReg base = ret ? ret : TCG_TMP0;
tcg_out_insn(s, RIL, LARL, base, 0);
new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2);
tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0);
}
}
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long sval)
{
tcg_out_movi_int(s, type, ret, sval, false);
}
/* Emit a load/store type instruction. Inputs are:
DATA: The register to be loaded or stored.
BASE+OFS: The effective address.
OPC_RX: If the operation has an RX format opcode (e.g. STC), otherwise 0.
OPC_RXY: The RXY format opcode for the operation (e.g. STCY). */
static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy,
TCGReg data, TCGReg base, TCGReg index,
tcg_target_long ofs)
{
if (ofs < -0x80000 || ofs >= 0x80000) {
/* Combine the low 20 bits of the offset with the actual load insn;
the high 44 bits must come from an immediate load. */
tcg_target_long low = ((ofs & 0xfffff) ^ 0x80000) - 0x80000;
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - low);
ofs = low;
/* If we were already given an index register, add it in. */
if (index != TCG_REG_NONE) {
tcg_out_insn(s, RRE, AGR, TCG_TMP0, index);
}
index = TCG_TMP0;
}
if (opc_rx && ofs >= 0 && ofs < 0x1000) {
tcg_out_insn_RX(s, opc_rx, data, base, index, ofs);
} else {
tcg_out_insn_RXY(s, opc_rxy, data, base, index, ofs);
}
}
/* load data without address translation or endianness conversion */
static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, intptr_t ofs)
{
if (type == TCG_TYPE_I32) {
tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs);
} else {
tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs);
}
}
static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, intptr_t ofs)
{
if (type == TCG_TYPE_I32) {
tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs);
} else {
tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs);
}
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
TCGReg base, intptr_t ofs)
{
return false;
}
/* load data from an absolute host address */
static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)
{
intptr_t addr = (intptr_t)abs;
if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) {
ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1;
if (disp == (int32_t)disp) {
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RIL, LRL, dest, disp);
} else {
tcg_out_insn(s, RIL, LGRL, dest, disp);
}
return;
}
}
if (USE_REG_TB) {
ptrdiff_t disp = abs - (void *)s->code_gen_ptr;
if (disp == sextract64(disp, 0, 20)) {
tcg_out_ld(s, type, dest, TCG_REG_TB, disp);
return;
}
}
tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);
tcg_out_ld(s, type, dest, dest, addr & 0xffff);
}
static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src,
int msb, int lsb, int ofs, int z)
{
/* Format RIE-f */
tcg_out16(s, (RIE_RISBG & 0xff00) | (dest << 4) | src);
tcg_out16(s, (msb << 8) | (z << 7) | lsb);
tcg_out16(s, (ofs << 8) | (RIE_RISBG & 0xff));
}
static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
{
if (s390_facilities & FACILITY_EXT_IMM) {
tcg_out_insn(s, RRE, LGBR, dest, src);
return;
}
if (type == TCG_TYPE_I32) {
if (dest == src) {
tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 24);
} else {
tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 24);
}
tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 24);
} else {
tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 56);
tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 56);
}
}
static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
{
if (s390_facilities & FACILITY_EXT_IMM) {
tcg_out_insn(s, RRE, LLGCR, dest, src);
return;
}
if (dest == src) {
tcg_out_movi(s, type, TCG_TMP0, 0xff);
src = TCG_TMP0;
} else {
tcg_out_movi(s, type, dest, 0xff);
}
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, NR, dest, src);
} else {
tcg_out_insn(s, RRE, NGR, dest, src);
}
}
static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
{
if (s390_facilities & FACILITY_EXT_IMM) {
tcg_out_insn(s, RRE, LGHR, dest, src);
return;
}
if (type == TCG_TYPE_I32) {
if (dest == src) {
tcg_out_sh32(s, RS_SLL, dest, TCG_REG_NONE, 16);
} else {
tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 16);
}
tcg_out_sh32(s, RS_SRA, dest, TCG_REG_NONE, 16);
} else {
tcg_out_sh64(s, RSY_SLLG, dest, src, TCG_REG_NONE, 48);
tcg_out_sh64(s, RSY_SRAG, dest, dest, TCG_REG_NONE, 48);
}
}
static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src)
{
if (s390_facilities & FACILITY_EXT_IMM) {
tcg_out_insn(s, RRE, LLGHR, dest, src);
return;
}
if (dest == src) {
tcg_out_movi(s, type, TCG_TMP0, 0xffff);
src = TCG_TMP0;
} else {
tcg_out_movi(s, type, dest, 0xffff);
}
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, NR, dest, src);
} else {
tcg_out_insn(s, RRE, NGR, dest, src);
}
}
static inline void tgen_ext32s(TCGContext *s, TCGReg dest, TCGReg src)
{
tcg_out_insn(s, RRE, LGFR, dest, src);
}
static inline void tgen_ext32u(TCGContext *s, TCGReg dest, TCGReg src)
{
tcg_out_insn(s, RRE, LLGFR, dest, src);
}
/* Accept bit patterns like these:
0....01....1
1....10....0
1..10..01..1
0..01..10..0
Copied from gcc sources. */
static inline bool risbg_mask(uint64_t c)
{
uint64_t lsb;
/* We don't change the number of transitions by inverting,
so make sure we start with the LSB zero. */
if (c & 1) {
c = ~c;
}
/* Reject all zeros or all ones. */
if (c == 0) {
return false;
}
/* Find the first transition. */
lsb = c & -c;
/* Invert to look for a second transition. */
c = ~c;
/* Erase the first transition. */
c &= -lsb;
/* Find the second transition, if any. */
lsb = c & -c;
/* Match if all the bits are 1's, or if c is zero. */
return c == -lsb;
}
static void tgen_andi_risbg(TCGContext *s, TCGReg out, TCGReg in, uint64_t val)
{
int msb, lsb;
if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) {
/* Achieve wraparound by swapping msb and lsb. */
msb = 64 - ctz64(~val);
lsb = clz64(~val) - 1;
} else {
msb = clz64(val);
lsb = 63 - ctz64(val);
}
tcg_out_risbg(s, out, in, msb, lsb, 0, 1);
}
static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
{
static const S390Opcode ni_insns[4] = {
RI_NILL, RI_NILH, RI_NIHL, RI_NIHH
};
static const S390Opcode nif_insns[2] = {
RIL_NILF, RIL_NIHF
};
uint64_t valid = (type == TCG_TYPE_I32 ? 0xffffffffull : -1ull);
int i;
/* Look for the zero-extensions. */
if ((val & valid) == 0xffffffff) {
tgen_ext32u(s, dest, dest);
return;
}
if (s390_facilities & FACILITY_EXT_IMM) {
if ((val & valid) == 0xff) {
tgen_ext8u(s, TCG_TYPE_I64, dest, dest);
return;
}
if ((val & valid) == 0xffff) {
tgen_ext16u(s, TCG_TYPE_I64, dest, dest);
return;
}
}
/* Try all 32-bit insns that can perform it in one go. */
for (i = 0; i < 4; i++) {
tcg_target_ulong mask = ~(0xffffull << i*16);
if (((val | ~valid) & mask) == mask) {
tcg_out_insn_RI(s, ni_insns[i], dest, val >> i*16);
return;
}
}
/* Try all 48-bit insns that can perform it in one go. */
if (s390_facilities & FACILITY_EXT_IMM) {
for (i = 0; i < 2; i++) {
tcg_target_ulong mask = ~(0xffffffffull << i*32);
if (((val | ~valid) & mask) == mask) {
tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);
return;
}
}
}
if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) {
tgen_andi_risbg(s, dest, dest, val);
return;
}
/* Use the constant pool if USE_REG_TB, but not for small constants. */
if (USE_REG_TB) {
if (!maybe_out_small_movi(s, type, TCG_TMP0, val)) {
tcg_out_insn(s, RXY, NG, dest, TCG_REG_TB, TCG_REG_NONE, 0);
new_pool_label(s, val & valid, R_390_20, s->code_ptr - 2,
-(intptr_t)s->code_gen_ptr);
return;
}
} else {
tcg_out_movi(s, type, TCG_TMP0, val);
}
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RR, NR, dest, TCG_TMP0);
} else {
tcg_out_insn(s, RRE, NGR, dest, TCG_TMP0);
}
}
static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val)
{
static const S390Opcode oi_insns[4] = {
RI_OILL, RI_OILH, RI_OIHL, RI_OIHH
};
static const S390Opcode oif_insns[2] = {
RIL_OILF, RIL_OIHF
};
int i;
/* Look for no-op. */
if (unlikely(val == 0)) {
return;
}
/* Try all 32-bit insns that can perform it in one go. */
for (i = 0; i < 4; i++) {
tcg_target_ulong mask = (0xffffull << i*16);
if ((val & mask) != 0 && (val & ~mask) == 0) {
tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);
return;
}
}
/* Try all 48-bit insns that can perform it in one go. */
if (s390_facilities & FACILITY_EXT_IMM) {
for (i = 0; i < 2; i++) {
tcg_target_ulong mask = (0xffffffffull << i*32);